sys/arch/hp700/dev/apic.c

   1 /*      $NetBSD: apic.c,v 1.5 2009/12/03 11:54:09 skrll Exp $   */
   2
   3 /*      $OpenBSD: apic.c,v 1.7 2007/10/06 23:50:54 krw Exp $    */
   4
   5 /*
   6  * Copyright (c) 2005 Michael Shalayeff
   7  * Copyright (c) 2007 Mark Kettenis
   8  * All rights reserved.
   9  *
  10  * Permission to use, copy, modify, and distribute this software for any
  11  * purpose with or without fee is hereby granted, provided that the above
  12  * copyright notice and this permission notice appear in all copies.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  18  * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
  19  * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
  20  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */
  21
  22 #include <sys/param.h>
  23 #include <sys/systm.h>
  24 #include <sys/device.h>
  25 #include <sys/malloc.h>
  26
  27 #include <machine/autoconf.h>
  28 #include <machine/pdc.h>
  29 #include <machine/intr.h>
  30
  31 #include <hp700/hp700/intr.h>
  32
  33 #include <dev/pci/pcireg.h>
  34 #include <dev/pci/pcivar.h>
  35 #include <dev/pci/pcidevs.h>
  36
  37 #include <hp700/dev/elroyreg.h>
  38 #include <hp700/dev/elroyvar.h>
  39
  40 #define APIC_INT_LINE_MASK      0x0000ff00
  41 #define APIC_INT_LINE_SHIFT     8
  42 #define APIC_INT_IRQ_MASK       0x0000001f
  43
  44 #define APIC_INT_LINE(x) (((x) & APIC_INT_LINE_MASK) >> APIC_INT_LINE_SHIFT)
  45 #define APIC_INT_IRQ(x) ((x) & APIC_INT_IRQ_MASK)
  46
  47 /*
  48  * Interrupt types match the Intel MP Specification.
  49  */
  50
  51 #define MPS_INTPO_DEF           0
  52 #define MPS_INTPO_ACTHI         1
  53 #define MPS_INTPO_ACTLO         3
  54 #define MPS_INTPO_SHIFT         0
  55 #define MPS_INTPO_MASK          3
  56
  57 #define MPS_INTTR_DEF           0
  58 #define MPS_INTTR_EDGE          1
  59 #define MPS_INTTR_LEVEL         3
  60 #define MPS_INTTR_SHIFT         2
  61 #define MPS_INTTR_MASK          3
  62
  63 #define MPS_INT(p,t) \
  64     ((((p) & MPS_INTPO_MASK) << MPS_INTPO_SHIFT) | \
  65      (((t) & MPS_INTTR_MASK) << MPS_INTTR_SHIFT))
  66
  67 struct apic_iv {
  68         struct elroy_softc *sc;
  69         pci_intr_handle_t ih;
  70         int (*handler)(void *);
  71         void *arg;
  72         struct apic_iv *next;
  73         struct evcnt *cnt;
  74 };
  75
  76 struct apic_iv *apic_intr_list[CPU_NINTS];
  77
  78 void apic_write(volatile struct elroy_regs *, uint32_t, uint32_t);
  79 uint32_t apic_read(volatile struct elroy_regs *, uint32_t reg);
  80
  81 void    apic_get_int_tbl(struct elroy_softc *);
  82 uint32_t apic_get_int_ent0(struct elroy_softc *, int);
  83 #ifdef DEBUG
  84 void    apic_dump(struct elroy_softc *);
  85 #endif
  86
  87 void
  88 apic_write(volatile struct elroy_regs *r, uint32_t reg, uint32_t val)
  89 {
  90         elroy_write32(&r->apic_addr, htole32(reg));
  91         elroy_write32(&r->apic_data, htole32(val));
  92         elroy_read32(&r->apic_data);
  93 }
  94
  95 uint32_t
  96 apic_read(volatile struct elroy_regs *r, uint32_t reg)
  97 {
  98         elroy_write32(&r->apic_addr, htole32(reg));
  99         return le32toh(elroy_read32(&r->apic_data));
 100 }
 101
 102 void
 103 apic_attach(struct elroy_softc *sc)
 104 {
 105         volatile struct elroy_regs *r = sc->sc_regs;
 106         uint32_t data;
 107
 108         data = apic_read(r, APIC_VERSION);
 109         sc->sc_nints = (data & APIC_VERSION_NENT) >> APIC_VERSION_NENT_SHIFT;
 110         aprint_normal(" APIC ver %x, %d pins",
 111             data & APIC_VERSION_MASK, sc->sc_nints);
 112
 113         sc->sc_irq = malloc(sc->sc_nints * sizeof(int), M_DEVBUF,
 114             M_NOWAIT | M_ZERO);
 115         if (sc->sc_irq == NULL)
 116                 panic("apic_attach: can't allocate irq table\n");
 117
 118         apic_get_int_tbl(sc);
 119
 120 #ifdef DEBUG
 121         apic_dump(sc);
 122 #endif
 123 }
 124
 125 int
 126 apic_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
 127 {
 128         struct elroy_softc *sc = pa->pa_pc->_cookie;
 129         pci_chipset_tag_t pc = pa->pa_pc;
 130         pcitag_t tag = pa->pa_tag;
 131         pcireg_t reg;
 132         int line;
 133
 134         reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
 135 #ifdef DEBUG
 136         printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg),
 137             PCI_INTERRUPT_LINE(reg));
 138 #endif
 139         line = PCI_INTERRUPT_LINE(reg);
 140         if (sc->sc_irq[line] == 0)
 141                 sc->sc_irq[line] = hp700_intr_allocate_bit(&int_reg_cpu);
 142         *ihp = (line << APIC_INT_LINE_SHIFT) | sc->sc_irq[line];
 143         return (APIC_INT_IRQ(*ihp) == 0);
 144 }
 145
 146 const char *
 147 apic_intr_string(void *v, pci_intr_handle_t ih)
 148 {
 149         static char buf[32];
 150
 151         snprintf(buf, sizeof(buf), "line %ld irq %ld",
 152             APIC_INT_LINE(ih), APIC_INT_IRQ(ih));
 153
 154         return (buf);
 155 }
 156
 157 void *
 158 apic_intr_establish(void *v, pci_intr_handle_t ih,
 159     int pri, int (*handler)(void *), void *arg)
 160 {
 161         struct elroy_softc *sc = v;
 162         volatile struct elroy_regs *r = sc->sc_regs;
 163         hppa_hpa_t hpa = cpu_gethpa(0);
 164         struct evcnt *cnt;
 165         struct apic_iv *aiv, *biv;
 166         void *iv;
 167         int irq = APIC_INT_IRQ(ih);
 168         int line = APIC_INT_LINE(ih);
 169         uint32_t ent0;
 170
 171         /* no mapping or bogus */
 172         if (irq <= 0 || irq > 31)
 173                 return (NULL);
 174
 175         aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_NOWAIT);
 176         if (aiv == NULL)
 177                 return NULL;
 178
 179         aiv->sc = sc;
 180         aiv->ih = ih;
 181         aiv->handler = handler;
 182         aiv->arg = arg;
 183         aiv->next = NULL;
 184         aiv->cnt = NULL;
 185         if (apic_intr_list[irq]) {
 186                 cnt = malloc(sizeof(struct evcnt), M_DEVBUF, M_NOWAIT);
 187                 if (cnt == NULL) {
 188                         free(aiv, M_DEVBUF);
 189                         return NULL;
 190                 }
 191
 192                 evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL,
 193                     device_xname(sc->sc_dv), "irq" /* XXXNH */);
 194                 biv = apic_intr_list[irq];
 195                 while (biv->next)
 196                         biv = biv->next;
 197                 biv->next = aiv;
 198                 aiv->cnt = cnt;
 199                 return arg;
 200         }
 201
 202         if ((iv = hp700_intr_establish(sc->sc_dv, pri, apic_intr,
 203              aiv, &int_reg_cpu, irq))) {
 204                 ent0 = (31 - irq) & APIC_ENT0_VEC;
 205                 ent0 |= apic_get_int_ent0(sc, line);
 206 #if 0
 207                 if (cold) {
 208                         sc->sc_imr |= (1 << irq);
 209                         ent0 |= APIC_ENT0_MASK;
 210                 }
 211 #endif
 212                 apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
 213                 apic_write(sc->sc_regs, APIC_ENT1(line),
 214                     ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
 215                 apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
 216
 217                 /* Signal EOI. */
 218                 elroy_write32(&r->apic_eoi,
 219                     htole32((31 - irq) & APIC_ENT0_VEC));
 220
 221                 apic_intr_list[irq] = aiv;
 222         }
 223
 224         return (arg);
 225 }
 226
 227 void
 228 apic_intr_disestablish(void *v, void *cookie)
 229 {
 230 }
 231
 232 int
 233 apic_intr(void *v)
 234 {
 235         struct apic_iv *iv = v;
 236         struct elroy_softc *sc = iv->sc;
 237         volatile struct elroy_regs *r = sc->sc_regs;
 238         int claimed = 0;
 239
 240         while (iv) {
 241                 if (iv->handler(iv->arg)) {
 242                         if (iv->cnt)
 243                                 iv->cnt->ev_count++;
 244                         /* Signal EOI. */
 245                         elroy_write32(&r->apic_eoi,
 246                             htole32((31 - APIC_INT_IRQ(iv->ih)) & APIC_ENT0_VEC));
 247                         claimed = 1;
 248                 }
 249                 iv = iv->next;
 250         }
 251
 252         return (claimed);
 253 }
 254
 255 /* Maximum number of supported interrupt routing entries. */
 256 #define MAX_INT_TBL_SZ  16
 257
 258 void
 259 apic_get_int_tbl(struct elroy_softc *sc)
 260 {
 261         static struct pdc_pat_io_num int_tbl_sz PDC_ALIGNMENT;
 262         static struct pdc_pat_pci_rt int_tbl[MAX_INT_TBL_SZ] PDC_ALIGNMENT;
 263         size_t size;
 264
 265         if (pdc_call((iodcio_t)pdc, 0, PDC_PCI_INDEX, PDC_PCI_GET_INT_TBL_SZ,
 266             &int_tbl_sz, 0, 0, 0, 0, 0))
 267                 return;
 268
 269         if (int_tbl_sz.num > MAX_INT_TBL_SZ)
 270                 panic("interrupt routing table too big (%d entries)",
 271                     int_tbl_sz.num);
 272
 273         size = int_tbl_sz.num * sizeof(struct pdc_pat_pci_rt);
 274         sc->sc_int_tbl_sz = int_tbl_sz.num;
 275         sc->sc_int_tbl = malloc(size, M_DEVBUF, M_NOWAIT);
 276         if (sc->sc_int_tbl == NULL)
 277                 return;
 278
 279         if (pdc_call((iodcio_t)pdc, 0, PDC_PCI_INDEX, PDC_PCI_GET_INT_TBL,
 280             &int_tbl_sz, 0, &int_tbl, 0, 0, 0))
 281                 return;
 282
 283         memcpy(sc->sc_int_tbl, int_tbl, size);
 284 }
 285
 286 uint32_t
 287 apic_get_int_ent0(struct elroy_softc *sc, int line)
 288 {
 289         volatile struct elroy_regs *r = sc->sc_regs;
 290         int trigger = MPS_INT(MPS_INTPO_DEF, MPS_INTTR_DEF);
 291         uint32_t ent0 = APIC_ENT0_LOW | APIC_ENT0_LEV;
 292         int bus, mpspo, mpstr;
 293         int i;
 294
 295         bus = le32toh(elroy_read32(&r->busnum)) & 0xff;
 296         for (i = 0; i < sc->sc_int_tbl_sz; i++) {
 297                 if (bus == sc->sc_int_tbl[i].bus &&
 298                     line == sc->sc_int_tbl[i].line)
 299                         trigger = sc->sc_int_tbl[i].trigger;
 300         }
 301
 302         mpspo = (trigger >> MPS_INTPO_SHIFT) & MPS_INTPO_MASK;
 303         mpstr = (trigger >> MPS_INTTR_SHIFT) & MPS_INTTR_MASK;
 304
 305         switch (mpspo) {
 306         case MPS_INTPO_DEF:
 307                 break;
 308         case MPS_INTPO_ACTHI:
 309                 ent0 &= ~APIC_ENT0_LOW;
 310                 break;
 311         case MPS_INTPO_ACTLO:
 312                 ent0 |= APIC_ENT0_LOW;
 313                 break;
 314         default:
 315                 panic("unknown MPS interrupt polarity %d", mpspo);
 316         }
 317
 318         switch(mpstr) {
 319         case MPS_INTTR_DEF:
 320                 break;
 321         case MPS_INTTR_LEVEL:
 322                 ent0 |= APIC_ENT0_LEV;
 323                 break;
 324         case MPS_INTTR_EDGE:
 325                 ent0 &= ~APIC_ENT0_LEV;
 326                 break;
 327         default:
 328                 panic("unknown MPS interrupt trigger %d", mpstr);
 329         }
 330
 331         return ent0;
 332 }
 333
 334 #ifdef DEBUG
 335 void
 336 apic_dump(struct elroy_softc *sc)
 337 {
 338         int i;
 339
 340         for (i = 0; i < sc->sc_nints; i++)
 341                 printf("0x%04x 0x%04x\n", apic_read(sc->sc_regs, APIC_ENT0(i)),
 342                     apic_read(sc->sc_regs, APIC_ENT1(i)));
 343
 344         for (i = 0; i < sc->sc_int_tbl_sz; i++) {
 345                 printf("type=%x ", sc->sc_int_tbl[i].type);
 346                 printf("len=%d ", sc->sc_int_tbl[i].len);
 347                 printf("itype=%d ", sc->sc_int_tbl[i].itype);
 348                 printf("trigger=%x ", sc->sc_int_tbl[i].trigger);
 349                 printf("pin=%x ", sc->sc_int_tbl[i].pin);
 350                 printf("bus=%d ", sc->sc_int_tbl[i].bus);
 351                 printf("line=%d ", sc->sc_int_tbl[i].line);
 352                 printf("addr=%llx\n", sc->sc_int_tbl[i].addr);
 353         }
 354 }
 355 #endif