sys/arch/hpcmips/include/bus_dma_hpcmips.h

   1 /*      $NetBSD: bus_dma_hpcmips.h,v 1.4 2005/12/11 12:17:33 christos Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2001 TAKEMRUA Shin. All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the project nor the names of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  */
  31
  32 #ifndef _BUS_DMA_HPCMIPS_H_
  33 #define _BUS_DMA_HPCMIPS_H_
  34
  35 #define HPCMIPS_DMAMAP_COHERENT 0x100   /* no cache flush necessary on sync */
  36
  37 /*
  38  *      bus_dma_segment
  39  *
  40  *      Describes a single contiguous DMA transaction.  Values
  41  *      are suitable for programming into DMA registers.
  42  */
  43 struct bus_dma_segment_hpcmips {
  44         bus_addr_t      _ds_vaddr;      /* virtual address, 0 if invalid */
  45 };
  46
  47 /*
  48  *      bus_dma_tag
  49  *
  50  *      A machine-dependent opaque type describing the implementation of
  51  *      DMA for a given bus.
  52  */
  53 struct bus_dma_tag_hpcmips {
  54         struct bus_dma_tag      bdt;
  55         void    *_dmamap_chipset_v;
  56 };
  57
  58 /*
  59  *      bus_dmamap
  60  *
  61  *      Describes a DMA mapping.
  62  */
  63 struct bus_dmamap_hpcmips {
  64         struct bus_dmamap bdm;
  65         bus_size_t      _dm_size;       /* largest DMA transfer mappable */
  66         int             _dm_segcnt;     /* number of segs this map can map */
  67         bus_size_t      _dm_maxmaxsegsz;/* fixed largest possible segment */
  68         bus_size_t      _dm_boundary;   /* don't cross this */
  69         int             _dm_flags;      /* misc. flags */
  70         struct bus_dma_segment_hpcmips _dm_segs[1];
  71 };
  72
  73 extern struct bus_dma_tag_hpcmips hpcmips_default_bus_dma_tag;
  74 bus_dma_protos(_hpcmips)
  75
  76 int     _hpcmips_bd_mem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
  77             bus_size_t alignment, bus_size_t boundary,
  78             bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
  79             vaddr_t low, vaddr_t high);
  80
  81 #endif /* _BUS_DMA_HPCMIPS_H_ */