sys/arch/hpcmips/include/intr.h

   1 /*      $NetBSD: intr.h,v 1.21 2007/12/03 15:33:43 ad Exp $     */
   2
   3 /*
   4  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Jonathan Stone for
  17  *      the NetBSD Project.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _HPCMIPS_INTR_H_
  34 #define _HPCMIPS_INTR_H_
  35
  36 #define IPL_NONE        0       /* disable only this interrupt */
  37 #define IPL_SOFTCLOCK   1       /* clock software interrupts (SI 0) */
  38 #define IPL_SOFTBIO     1       /* bio software interrupts (SI 0) */
  39 #define IPL_SOFTNET     2       /* network software interrupts (SI 1) */
  40 #define IPL_SOFTSERIAL  2       /* serial software interrupts (SI 1) */
  41 #define IPL_VM          3
  42 #define IPL_SCHED       4
  43 #define IPL_HIGH        4       /* disable all interrupts */
  44
  45 #define _IPL_N          5
  46
  47 #define _IPL_SI0_FIRST  IPL_SOFTCLOCK
  48 #define _IPL_SI0_LAST   IPL_SOFTBIO
  49
  50 #define _IPL_SI1_FIRST  IPL_SOFTNET
  51 #define _IPL_SI1_LAST   IPL_SOFTSERIAL
  52
  53 /* Interrupt sharing types. */
  54 #define IST_UNUSABLE    -1      /* interrupt cannot be used */
  55 #define IST_NONE        0       /* none */
  56 #define IST_PULSE       1       /* pulsed */
  57 #define IST_EDGE        2       /* edge-triggered */
  58 #define IST_LEVEL       3       /* level-triggered */
  59
  60 #ifdef _KERNEL
  61 #ifndef _LOCORE
  62 #include <mips/cpuregs.h>
  63 #include <mips/locore.h>
  64
  65 extern const u_int32_t *ipl_sr_bits;
  66
  67 void    intr_init(void);
  68
  69 #define spl0()          (void) _spllower(0)
  70 #define splx(s)         (void) _splset(s)
  71
  72 typedef int ipl_t;
  73 typedef struct {
  74         ipl_t _sr;
  75 } ipl_cookie_t;
  76
  77 static inline ipl_cookie_t
  78 makeiplcookie(ipl_t ipl)
  79 {
  80
  81         return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
  82 }
  83
  84 static inline int
  85 splraiseipl(ipl_cookie_t icookie)
  86 {
  87
  88         return _splraise(icookie._sr);
  89 }
  90
  91 #include <sys/spl.h>
  92
  93 #endif /* !_LOCORE */
  94 #endif /* _KERNEL */
  95
  96 #endif /* !_HPCMIPS_INTR_H_ */