sys/arch/m68k/include/cacheops_20.h

   1 /*      $NetBSD: cacheops_20.h,v 1.8 2006/02/16 20:17:13 perry Exp $    */
   2
   3 /*-
   4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Leo Weppelman
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Invalidate entire TLB.
  34  */
  35 static __inline void __attribute__((__unused__))
  36 TBIA_20(void)
  37 {
  38         __asm volatile (" pflusha");
  39 }
  40
  41 /*
  42  * Invalidate any TLB entry for given VA (TB Invalidate Single)
  43  */
  44 static __inline void __attribute__((__unused__))
  45 TBIS_20(vaddr_t va)
  46 {
  47
  48         __asm volatile (" pflushs       #0,#0,%0@" : : "a" (va) );
  49 }
  50
  51 /*
  52  * Invalidate supervisor side of TLB
  53  */
  54 static __inline void __attribute__((__unused__))
  55 TBIAS_20(void)
  56 {
  57         __asm volatile (" pflushs #4,#4");
  58 }
  59
  60 /*
  61  * Invalidate user side of TLB
  62  */
  63 static __inline void __attribute__((__unused__))
  64 TBIAU_20(void)
  65 {
  66         __asm volatile (" pflushs #0,#4;");
  67 }
  68
  69 /*
  70  * Invalidate instruction cache
  71  */
  72 static __inline void __attribute__((__unused__))
  73 ICIA_20(void)
  74 {
  75         __asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
  76 }
  77
  78 static __inline void __attribute__((__unused__))
  79 ICPA_20(void)
  80 {
  81         __asm volatile (" movc %0,%%cacr;" : : "d" (IC_CLEAR));
  82 }
  83
  84 /*
  85  * Invalidate data cache.
  86  * NOTE: we do not flush 68030/20 on-chip cache as there are no aliasing
  87  * problems with DC_WA.  The only cases we have to worry about are context
  88  * switch and TLB changes, both of which are handled "in-line" in resume
  89  * and TBI*.
  90  */
  91 #define DCIA_20()
  92 #define DCIS_20()
  93 #define DCIU_20()
  94 #define DCIAS_20(va)
  95 #define DCFA_20()
  96 #define DCPA_20()
  97
  98 static __inline void __attribute__((__unused__))
  99 PCIA_20(void)
 100 {
 101         __asm volatile (" movc %0,%%cacr;" : : "d" (DC_CLEAR));
 102 }