sys/arch/mac68k/dev/scc_8530.h

   1 /*
   2  * Mach Operating System
   3  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
   4  * All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify and distribute this software and its
   7  * documentation is hereby granted, provided that both the copyright
   8  * notice and this permission notice appear in all copies of the
   9  * software, derivative works or modified versions, and any portions
  10  * thereof, and that both notices appear in supporting documentation.
  11  *
  12  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  13  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  14  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  15  *
  16  * Carnegie Mellon requests users of this software to return to
  17  *
  18  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  19  *  School of Computer Science
  20  *  Carnegie Mellon University
  21  *  Pittsburgh PA 15213-3890
  22  *
  23  * any improvements or extensions that they make and grant Carnegie Mellon
  24  * the rights to redistribute these changes.
  25  */
  26 /*
  27  * HISTORY
  28  * $Log:        scc_8530.h,v $
  29  * Revision 2.4  93/02/05  08:06:56  danner
  30  *      Generalized register access, to accomodate Alpha.
  31  *      [93/02/04  01:27:21  af]
  32  *
  33  * Revision 2.3  92/02/19  16:46:06  elf
  34  *      Revised, based on Intel documentation for the 82530:
  35  *      "Microcommunications Handbook", Vol 1-2, 1990.
  36  *      [92/01/22            af]
  37  *
  38  * Revision 2.2  91/08/24  11:52:49  af
  39  *      Created, from the Zilog specs:
  40  *      "Z8530 SCC Serial Communications Controller, Product Specification"
  41  *      in the "1983/84 Components Data Book" pp 409-429, September 1983
  42  *      Zilog, Campbell, CA 95008
  43  *      [91/06/21            af]
  44  *
  45  */
  46 /*
  47  *      File: scc_8530.h
  48  *      Author: Alessandro Forin, Carnegie Mellon University
  49  *      Date:   6/91
  50  *
  51  *      Definitions for the Zilog Z8530 SCC serial line chip
  52  */
  53 #ident "$Id: scc_8530.h,v 1.1 1993/09/29 06:09:27 briggs Exp $"
  54
  55 #ifndef _SCC_8530_H_
  56 #define _SCC_8530_H_
  57
  58 /*
  59  * Register map, needs definition of the alignment
  60  * used on the specific machine.
  61  * #define the 'scc_register_t' data type before
  62  * including this header file.  For restrictions on
  63  * access modes define the set/get_datum macros.
  64  * We provide defaults ifnot.
  65  */
  66
  67 #ifndef scc_register_t
  68
  69 typedef struct scc_register {
  70     volatile unsigned char      datum;
  71 } scc_register_t;
  72
  73 #endif
  74
  75
  76 #define SCC_CHANNEL_A   1
  77 #define SCC_CHANNEL_B   0
  78
  79 typedef struct {
  80     /* Channel B is first, then A */
  81     struct {
  82         scc_register_t  scc_command;    /* reg select */
  83         scc_register_t  scc_data;       /* Rx/Tx buffer */
  84     } scc_channel[2];
  85 } scc_regmap_t;
  86
  87
  88 #ifndef scc_set_datum(d,v)
  89 #define scc_set_datum(d,v)      (d) = (v)
  90 #define scc_get_datum(d,v)      (v) = (d)
  91 #endif
  92
  93 #define scc_init_reg(scc,chan)          { \
  94                 char tmp; \
  95                 scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,tmp); \
  96                 scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,tmp); \
  97         }
  98
  99 #define scc_read_reg(scc,chan,reg,val)  { \
 100                 scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,reg); \
 101                 scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
 102         }
 103
 104 #define scc_read_reg_zero(scc,chan,val) { \
 105                 scc_get_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
 106         }
 107
 108 #define scc_write_reg(scc,chan,reg,val) { \
 109                 scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,reg); \
 110                 scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
 111         }
 112
 113 #define scc_write_reg_zero(scc,chan,val) { \
 114                 scc_set_datum((scc)->scc_channel[(chan)].scc_command.datum,val); \
 115         }
 116
 117 #define scc_read_data(scc,chan,val)     { \
 118                 scc_get_datum((scc)->scc_channel[(chan)].scc_data.datum,val); \
 119         }
 120
 121 #define scc_write_data(scc,chan,val) { \
 122                 scc_set_datum((scc)->scc_channel[(chan)].scc_data.datum,val); \
 123         }
 124
 125 /*
 126  * Addressable registers
 127  */
 128
 129 #define SCC_RR0         0       /* status register */
 130 #define SCC_RR1         1       /* special receive conditions */
 131 #define SCC_RR2         2       /* (modified) interrupt vector */
 132 #define SCC_RR3         3       /* interrupts pending (cha A only) */
 133 #define SCC_RR8         8       /* recv buffer (alias for data) */
 134 #define SCC_RR10        10      /* sdlc status */
 135 #define SCC_RR12        12      /* BRG constant, low part */
 136 #define SCC_RR13        13      /* BRG constant, high part */
 137 #define SCC_RR15        15      /* interrupts currently enabled */
 138
 139 #define SCC_WR0         0       /* reg select, and commands */
 140 #define SCC_WR1         1       /* interrupt and DMA enables */
 141 #define SCC_WR2         2       /* interrupt vector */
 142 #define SCC_WR3         3       /* receiver params and enables */
 143 #define SCC_WR4         4       /* clock/char/parity params */
 144 #define SCC_WR5         5       /* xmit params and enables */
 145 #define SCC_WR6         6       /* synchr SYNCH/address */
 146 #define SCC_WR7         7       /* synchr SYNCH/flag */
 147 #define SCC_WR8         8       /* xmit buffer (alias for data) */
 148 #define SCC_WR9         9       /* vectoring and resets */
 149 #define SCC_WR10        10      /* synchr params */
 150 #define SCC_WR11        11      /* clocking definitions */
 151 #define SCC_WR12        12      /* BRG constant, low part */
 152 #define SCC_WR13        13      /* BRG constant, high part */
 153 #define SCC_WR14        14      /* BRG enables and commands */
 154 #define SCC_WR15        15      /* interrupt enables */
 155
 156 /*
 157  * Read registers defines
 158  */
 159
 160 #define SCC_RR0_BREAK           0x80    /* break detected (rings twice), or */
 161 #define SCC_RR0_ABORT           0x80    /* abort (synchr) */
 162 #define SCC_RR0_TX_UNDERRUN     0x40    /* xmit buffer empty/end of message */
 163 #define SCC_RR0_CTS             0x20    /* clear-to-send pin active (sampled
 164                                            only on intr and after RESI cmd */
 165 #define SCC_RR0_SYNCH           0x10    /* SYNCH found/still hunting */
 166 #define SCC_RR0_DCD             0x08    /* carrier-detect (same as CTS) */
 167 #define SCC_RR0_TX_EMPTY        0x04    /* xmit buffer empty */
 168 #define SCC_RR0_ZERO_COUNT      0x02    /* ? */
 169 #define SCC_RR0_RX_AVAIL        0x01    /* recv fifo not empty */
 170
 171 #define SCC_RR1_EOF             0x80    /* end-of-frame, SDLC mode */
 172 #define SCC_RR1_CRC_ERR         0x40    /* incorrect CRC or.. */
 173 #define SCC_RR1_FRAME_ERR       0x40    /* ..bad frame */
 174 #define SCC_RR1_RX_OVERRUN      0x20    /* rcv fifo overflow */
 175 #define SCC_RR1_PARITY_ERR      0x10    /* incorrect parity in data */
 176 #define SCC_RR1_RESIDUE0        0x08
 177 #define SCC_RR1_RESIDUE1        0x04
 178 #define SCC_RR1_RESIDUE2        0x02
 179 #define SCC_RR1_ALL_SENT        0x01
 180
 181 /* RR2 contains the interrupt vector unmodified (channel A) or
 182    modified as follows (channel B, if vector-include-status) */
 183
 184 #define SCC_RR2_STATUS(val)     ((val)&0xf)
 185
 186 #define SCC_RR2_B_XMIT_DONE     0x0
 187 #define SCC_RR2_B_EXT_STATUS    0x2
 188 #define SCC_RR2_B_RECV_DONE     0x4
 189 #define SCC_RR2_B_RECV_SPECIAL  0x6
 190 #define SCC_RR2_A_XMIT_DONE     0x8
 191 #define SCC_RR2_A_EXT_STATUS    0xa
 192 #define SCC_RR2_A_RECV_DONE     0xc
 193 #define SCC_RR2_A_RECV_SPECIAL  0xe
 194
 195 /* Interrupts pending, to be read from channel A only (B raz) */
 196 #define SCC_RR3_zero            0xc0
 197 #define SCC_RR3_RX_IP_A         0x20
 198 #define SCC_RR3_TX_IP_A         0x10
 199 #define SCC_RR3_EXT_IP_A        0x08
 200 #define SCC_RR3_RX_IP_B         0x04
 201 #define SCC_RR3_TX_IP_B         0x02
 202 #define SCC_RR3_EXT_IP_B        0x01
 203
 204 /* RR8 is the receive data buffer, a 3 deep FIFO */
 205 #define SCC_RECV_BUFFER         SCC_RR8
 206 #define SCC_RECV_FIFO_DEEP      3
 207
 208 #define SCC_RR10_1CLKS          0x80
 209 #define SCC_RR10_2CLKS          0x40
 210 #define SCC_RR10_zero           0x2d
 211 #define SCC_RR10_LOOP_SND       0x10
 212 #define SCC_RR10_ON_LOOP        0x02
 213
 214 /* RR12/RR13 hold the timing base, upper byte in RR13 */
 215
 216 #define scc_get_timing_base(scc,chan,val)       { \
 217                 register char   tmp;    \
 218                 scc_read_reg(scc,chan,SCC_RR12,val);\
 219                 scc_read_reg(scc,chan,SCC_RR13,tmp);\
 220                 (val) = ((val)<<8)|(tmp&0xff);\
 221         }
 222
 223 #define SCC_RR15_BREAK_IE       0x80
 224 #define SCC_RR15_TX_UNDERRUN_IE 0x40
 225 #define SCC_RR15_CTS_IE         0x20
 226 #define SCC_RR15_SYNCH_IE       0x10
 227 #define SCC_RR15_DCD_IE         0x08
 228 #define SCC_RR15_zero           0x05
 229 #define SCC_RR15_ZERO_COUNT_IE  0x02
 230
 231
 232 /*
 233  * Write registers defines
 234  */
 235
 236 /* WR0 is used for commands too */
 237 #define SCC_RESET_TXURUN_LATCH  0xc0
 238 #define SCC_RESET_TX_CRC        0x80
 239 #define SCC_RESET_RX_CRC        0x40
 240 #define SCC_RESET_HIGHEST_IUS   0x38    /* channel A only */
 241 #define SCC_RESET_ERROR         0x30
 242 #define SCC_RESET_TX_IP         0x28
 243 #define SCC_IE_NEXT_CHAR        0x20
 244 #define SCC_SEND_SDLC_ABORT     0x18
 245 #define SCC_RESET_EXT_IP        0x10
 246
 247 #define SCC_WR1_DMA_ENABLE      0x80    /* dma control */
 248 #define SCC_WR1_DMA_MODE        0x40    /* drive ~req for DMA controller */
 249 #define SCC_WR1_DMA_RECV_DATA   0x20    /* from wire to host memory */
 250                                         /* interrupt enable/conditions */
 251 #define SCC_WR1_RXI_SPECIAL_O   0x18    /* on special only */
 252 #define SCC_WR1_RXI_ALL_CHAR    0x10    /* on each char, or special */
 253 #define SCC_WR1_RXI_FIRST_CHAR  0x08    /* on first char, or special */
 254 #define SCC_WR1_RXI_DISABLE     0x00    /* never on recv */
 255 #define SCC_WR1_PARITY_IE       0x04    /* on parity errors */
 256 #define SCC_WR1_TX_IE           0x02
 257 #define SCC_WR1_EXT_IE          0x01
 258
 259 /* WR2 is common and contains the interrupt vector (high nibble) */
 260
 261 #define SCC_WR3_RX_8_BITS       0xc0
 262 #define SCC_WR3_RX_6_BITS       0x80
 263 #define SCC_WR3_RX_7_BITS       0x40
 264 #define SCC_WR3_RX_5_BITS       0x00
 265 #define SCC_WR3_AUTO_ENABLE     0x20
 266 #define SCC_WR3_HUNT_MODE       0x10
 267 #define SCC_WR3_RX_CRC_ENABLE   0x08
 268 #define SCC_WR3_SDLC_SRCH       0x04
 269 #define SCC_WR3_INHIBIT_SYNCH   0x02
 270 #define SCC_WR3_RX_ENABLE       0x01
 271
 272 /* Should be re-written after reset */
 273 #define SCC_WR4_CLK_x64         0xc0    /* clock divide factor */
 274 #define SCC_WR4_CLK_x32         0x80
 275 #define SCC_WR4_CLK_x16         0x40
 276 #define SCC_WR4_CLK_x1          0x00
 277 #define SCC_WR4_EXT_SYNCH_MODE  0x30    /* synch modes */
 278 #define SCC_WR4_SDLC_MODE       0x20
 279 #define SCC_WR4_16BIT_SYNCH     0x10
 280 #define SCC_WR4_8BIT_SYNCH      0x00
 281 #define SCC_WR4_2_STOP          0x0c    /* asynch modes */
 282 #define SCC_WR4_1_5_STOP        0x08
 283 #define SCC_WR4_1_STOP          0x04
 284 #define SCC_WR4_SYNCH_MODE      0x00
 285 #define SCC_WR4_EVEN_PARITY     0x02
 286 #define SCC_WR4_PARITY_ENABLE   0x01
 287
 288 #define SCC_WR5_DTR             0x80    /* drive DTR pin */
 289 #define SCC_WR5_TX_8_BITS       0x60
 290 #define SCC_WR5_TX_6_BITS       0x40
 291 #define SCC_WR5_TX_7_BITS       0x20
 292 #define SCC_WR5_TX_5_BITS       0x00
 293 #define SCC_WR5_SEND_BREAK      0x10
 294 #define SCC_WR5_TX_ENABLE       0x08
 295 #define SCC_WR5_CRC_16          0x04    /* CRC if non zero, .. */
 296 #define SCC_WR5_SDLC            0x00    /* ..SDLC otherwise  */
 297 #define SCC_WR5_RTS             0x02    /* drive RTS pin */
 298 #define SCC_WR5_TX_CRC_ENABLE   0x01
 299
 300 /* Registers WR6 and WR7 are for synch modes data, with among other things: */
 301
 302 #define SCC_WR6_BISYNCH_12      0x0f
 303 #define SCC_WR6_SDLC_RANGE_MASK 0x0f
 304 #define SCC_WR7_SDLC_FLAG       0x7e
 305
 306 /* WR8 is the transmit data buffer (no FIFO) */
 307 #define SCC_XMT_BUFFER          SCC_WR8
 308
 309 #define SCC_WR9_HW_RESET        0xc0    /* force hardware reset */
 310 #define SCC_WR9_RESET_CHA_A     0x80
 311 #define SCC_WR9_RESET_CHA_B     0x40
 312 #define SCC_WR9_NON_VECTORED    0x20    /* mbz for Zilog chip */
 313 #define SCC_WR9_STATUS_HIGH     0x10
 314 #define SCC_WR9_MASTER_IE       0x08
 315 #define SCC_WR9_DLC             0x04    /* disable-lower-chain */
 316 #define SCC_WR9_NV              0x02    /* no vector */
 317 #define SCC_WR9_VIS             0x01    /* vector-includes-status */
 318
 319 #define SCC_WR10_CRC_PRESET     0x80
 320 #define SCC_WR10_FM0            0x60
 321 #define SCC_WR10_FM1            0x40
 322 #define SCC_WR10_NRZI           0x20
 323 #define SCC_WR10_NRZ            0x00
 324 #define SCC_WR10_ACTIVE_ON_POLL 0x10
 325 #define SCC_WR10_MARK_IDLE      0x08    /* flag if zero */
 326 #define SCC_WR10_ABORT_ON_URUN  0x04    /* flag if zero */
 327 #define SCC_WR10_LOOP_MODE      0x02
 328 #define SCC_WR10_6BIT_SYNCH     0x01
 329 #define SCC_WR10_8BIT_SYNCH     0x00
 330
 331 #define SCC_WR11_RTxC_XTAL      0x80    /* RTxC pin is input (ext oscill) */
 332 #define SCC_WR11_RCLK_DPLL      0x60    /* clock received data on dpll */
 333 #define SCC_WR11_RCLK_BAUDR     0x40    /* .. on BRG */
 334 #define SCC_WR11_RCLK_TRc_PIN   0x20    /* .. on TRxC pin */
 335 #define SCC_WR11_RCLK_RTc_PIN   0x00    /* .. on RTxC pin */
 336 #define SCC_WR11_XTLK_DPLL      0x18
 337 #define SCC_WR11_XTLK_BAUDR     0x10
 338 #define SCC_WR11_XTLK_TRc_PIN   0x08
 339 #define SCC_WR11_XTLK_RTc_PIN   0x00
 340 #define SCC_WR11_TRc_OUT        0x04    /* drive TRxC pin as output from..*/
 341 #define SCC_WR11_TRcOUT_DPLL    0x03    /* .. the dpll */
 342 #define SCC_WR11_TRcOUT_BAUDR   0x02    /* .. the BRG */
 343 #define SCC_WR11_TRcOUT_XMTCLK  0x01    /* .. the xmit clock */
 344 #define SCC_WR11_TRcOUT_XTAL    0x00    /* .. the external oscillator */
 345
 346 /* WR12/WR13 are for timing base preset */
 347 #define scc_set_timing_base(scc,chan,val)       { \
 348                 scc_write_reg(scc,chan,SCC_RR12,val);\
 349                 scc_write_reg(scc,chan,SCC_RR13,(val)>>8);\
 350         }
 351
 352 /* More commands in this register */
 353 #define SCC_WR14_NRZI_MODE      0xe0    /* synch modulations */
 354 #define SCC_WR14_FM_MODE        0xc0
 355 #define SCC_WR14_RTc_SOURCE     0xa0    /* clock is from pin .. */
 356 #define SCC_WR14_BAUDR_SOURCE   0x80    /* .. or internal BRG */
 357 #define SCC_WR14_DISABLE_DPLL   0x60
 358 #define SCC_WR14_RESET_CLKMISS  0x40
 359 #define SCC_WR14_SEARCH_MODE    0x20
 360 /* ..and more bitsy */
 361 #define SCC_WR14_LOCAL_LOOPB    0x10
 362 #define SCC_WR14_AUTO_ECHO      0x08
 363 #define SCC_WR14_DTR_REQUEST    0x04
 364 #define SCC_WR14_BAUDR_SRC      0x02
 365 #define SCC_WR14_BAUDR_ENABLE   0x01
 366
 367 #define SCC_WR15_BREAK_IE       0x80
 368 #define SCC_WR15_TX_UNDERRUN_IE 0x40
 369 #define SCC_WR15_CTS_IE         0x20
 370 #define SCC_WR15_SYNCHUNT_IE    0x10
 371 #define SCC_WR15_DCD_IE         0x08
 372 #define SCC_WR15_zero           0x05
 373 #define SCC_WR15_ZERO_COUNT_IE  0x02
 374
 375
 376 #endif  /*_SCC_8530_H_*/