sys/arch/mac68k/include/scsi_5380.h

   1 /*      $NetBSD: scsi_5380.h,v 1.5 1999/04/12 20:38:19 pk Exp $ */
   2
   3 /*
   4  * Mach Operating System
   5  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
   6  * All Rights Reserved.
   7  *
   8  * Permission to use, copy, modify and distribute this software and its
   9  * documentation is hereby granted, provided that both the copyright
  10  * notice and this permission notice appear in all copies of the
  11  * software, derivative works or modified versions, and any portions
  12  * thereof, and that both notices appear in supporting documentation.
  13  *
  14  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  15  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  17  *
  18  * Carnegie Mellon requests users of this software to return to
  19  *
  20  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  21  *  School of Computer Science
  22  *  Carnegie Mellon University
  23  *  Pittsburgh PA 15213-3890
  24  *
  25  * any improvements or extensions that they make and grant Carnegie the
  26  * rights to redistribute these changes.
  27  */
  28 /*
  29  *      File: scsi_5380.h
  30  *      Author: Alessandro Forin, Carnegie Mellon University
  31  *      Date:   5/91
  32  *
  33  *      Defines for the NCR 5380 (SCSI chip), aka Am5380
  34  */
  35
  36 /*
  37  * Register map
  38  */
  39
  40 typedef struct {
  41         volatile unsigned char sci_data;        /* r:  Current data */
  42 #define sci_odata sci_data                      /* w:  Out data */
  43         PAD(pad0);
  44
  45         volatile unsigned char sci_icmd;        /* rw: Initiator command */
  46         PAD(pad1);
  47
  48         volatile unsigned char sci_mode;        /* rw: Mode */
  49         PAD(pad2);
  50
  51         volatile unsigned char sci_tcmd;        /* rw: Target command */
  52         PAD(pad3);
  53
  54         volatile unsigned char sci_bus_csr;     /* r:  Bus Status */
  55 #define sci_sel_enb sci_bus_csr                 /* w:  Select enable */
  56         PAD(pad4);
  57
  58         volatile unsigned char sci_csr;         /* r:  Status */
  59 #define sci_dma_send sci_csr                    /* w:  Start DMA send data */
  60         PAD(pad5);
  61
  62         volatile unsigned char sci_idata;       /* r:  Input data */
  63 #define sci_trecv sci_idata                     /* w:  Start DMA receive, target */
  64         PAD(pad6);
  65
  66         volatile unsigned char sci_iack;        /* r:  Interrupt Acknowledge  */
  67 #define sci_irecv sci_iack                      /* w:  Start DMA receive, initiator */
  68 } sci_regmap_t;
  69
  70
  71 /*
  72  * Initiator command register
  73  */
  74
  75 #define SCI_ICMD_DATA           0x01            /* rw: Assert data bus   */
  76 #define SCI_ICMD_ATN            0x02            /* rw: Assert ATN signal */
  77 #define SCI_ICMD_SEL            0x04            /* rw: Assert SEL signal */
  78 #define SCI_ICMD_BSY            0x08            /* rw: Assert BSY signal */
  79 #define SCI_ICMD_ACK            0x10            /* rw: Assert ACK signal */
  80 #define SCI_ICMD_LST            0x20            /* r:  Lost arbitration */
  81 #define SCI_ICMD_DIFF   SCI_ICMD_LST            /* w:  Differential cable */
  82 #define SCI_ICMD_AIP            0x40            /* r:  Arbitration in progress */
  83 #define SCI_ICMD_TEST   SCI_ICMD_AIP            /* w:  Test mode */
  84 #define SCI_ICMD_RST            0x80            /* rw: Assert RST signal */
  85
  86
  87 /*
  88  * Mode register
  89  */
  90
  91 #define SCI_MODE_ARB            0x01            /* rw: Start arbitration */
  92 #define SCI_MODE_DMA            0x02            /* rw: Enable DMA xfers */
  93 #define SCI_MODE_MONBSY         0x04            /* rw: Monitor BSY signal */
  94 #define SCI_MODE_DMA_IE         0x08            /* rw: Enable DMA complete interrupt */
  95 #define SCI_MODE_PERR_IE        0x10            /* rw: Interrupt on parity errors */
  96 #define SCI_MODE_PAR_CHK        0x20            /* rw: Check parity */
  97 #define SCI_MODE_TARGET         0x40            /* rw: Target mode (Initiator if 0) */
  98 #define SCI_MODE_BLOCKDMA       0x80            /* rw: Block-mode DMA handshake (MBZ) */
  99
 100
 101 /*
 102  * Target command register
 103  */
 104
 105 #define SCI_TCMD_IO             0x01            /* rw: Assert I/O signal */
 106 #define SCI_TCMD_CD             0x02            /* rw: Assert C/D signal */
 107 #define SCI_TCMD_MSG            0x04            /* rw: Assert MSG signal */
 108 #define SCI_TCMD_PHASE_MASK     0x07            /* r:  Mask for current bus phase */
 109 #define SCI_TCMD_REQ            0x08            /* rw: Assert REQ signal */
 110 #define SCI_TCMD_LAST_SENT      0x80            /* ro: Last byte was xferred
 111                                                  *     (not on 5380/1) */
 112
 113 #define SCI_PHASE(x)            SCSI_PHASE(x)
 114
 115 /*
 116  * Current (SCSI) Bus status
 117  */
 118
 119 #define SCI_BUS_DBP             0x01            /* r:  Data Bus parity */
 120 #define SCI_BUS_SEL             0x02            /* r:  SEL signal */
 121 #define SCI_BUS_IO              0x04            /* r:  I/O signal */
 122 #define SCI_BUS_CD              0x08            /* r:  C/D signal */
 123 #define SCI_BUS_MSG             0x10            /* r:  MSG signal */
 124 #define SCI_BUS_REQ             0x20            /* r:  REQ signal */
 125 #define SCI_BUS_BSY             0x40            /* r:  BSY signal */
 126 #define SCI_BUS_RST             0x80            /* r:  RST signal */
 127
 128 #define SCI_CUR_PHASE(x)        SCSI_PHASE((x)>>2)
 129
 130 /*
 131  * Bus and Status register
 132  */
 133
 134 #define SCI_CSR_ACK             0x01            /* r:  ACK signal */
 135 #define SCI_CSR_ATN             0x02            /* r:  ATN signal */
 136 #define SCI_CSR_DISC            0x04            /* r:  Disconnected (BSY==0) */
 137 #define SCI_CSR_PHASE_MATCH     0x08            /* r:  Bus and SCI_TCMD match */
 138 #define SCI_CSR_INT             0x10            /* r:  Interrupt request */
 139 #define SCI_CSR_PERR            0x20            /* r:  Parity error */
 140 #define SCI_CSR_DREQ            0x40            /* r:  DMA request */
 141 #define SCI_CSR_DONE            0x80            /* r:  DMA count is zero */
 142