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[netbsd-mini2440.git] / sys / arch / mac68k / obio / esp.c
blob7a743f3e4abc893288dc17eaae6d1f8bdc59d0dc
1 /* $NetBSD: esp.c,v 1.51 2008/06/02 12:01:11 hauke Exp $ */
2
3 /*
4 * Copyright (c) 1997 Jason R. Thorpe.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project
18 * by Jason R. Thorpe.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Copyright (c) 1994 Peter Galbavy
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 * 3. All advertising materials mentioning features or use of this software
47 * must display the following acknowledgement:
48 * This product includes software developed by Peter Galbavy
49 * 4. The name of the author may not be used to endorse or promote products
50 * derived from this software without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
54 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
55 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
56 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
58 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
60 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
61 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
62 * POSSIBILITY OF SUCH DAMAGE.
63 */
64
65 /*
66 * Based on aic6360 by Jarle Greipsland
67 *
68 * Acknowledgements: Many of the algorithms used in this driver are
69 * inspired by the work of Julian Elischer (julian@tfs.com) and
70 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
71 */
72
73 /*
74 * Initial m68k mac support from Allen Briggs <briggs@macbsd.com>
75 * (basically consisting of the match, a bit of the attach, and the
76 * "DMA" glue functions).
77 */
78
79 #include <sys/cdefs.h>
80 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.51 2008/06/02 12:01:11 hauke Exp $");
81
82 #include <sys/types.h>
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/kernel.h>
86 #include <sys/errno.h>
87 #include <sys/ioctl.h>
88 #include <sys/device.h>
89 #include <sys/buf.h>
90 #include <sys/proc.h>
91 #include <sys/queue.h>
92
93 #include <dev/scsipi/scsi_all.h>
94 #include <dev/scsipi/scsipi_all.h>
95 #include <dev/scsipi/scsiconf.h>
96 #include <dev/scsipi/scsi_message.h>
97
98 #include <machine/cpu.h>
99 #include <machine/bus.h>
100 #include <machine/param.h>
101
102 #include <dev/ic/ncr53c9xreg.h>
103 #include <dev/ic/ncr53c9xvar.h>
104
105 #include <machine/viareg.h>
106
107 #include <mac68k/obio/espvar.h>
108 #include <mac68k/obio/obiovar.h>
109
110 int espmatch(device_t, cfdata_t, void *);
111 void espattach(device_t, device_t, void *);
112
113 /* Linkup to the rest of the kernel */
114 CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc),
115 espmatch, espattach, NULL, NULL);
116
117 /*
118 * Functions and the switch for the MI code.
119 */
120 uint8_t esp_read_reg(struct ncr53c9x_softc *, int);
121 void esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
122 int esp_dma_isintr(struct ncr53c9x_softc *);
123 void esp_dma_reset(struct ncr53c9x_softc *);
124 int esp_dma_intr(struct ncr53c9x_softc *);
125 int esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, int,
126 size_t *);
127 void esp_dma_go(struct ncr53c9x_softc *);
128 void esp_dma_stop(struct ncr53c9x_softc *);
129 int esp_dma_isactive(struct ncr53c9x_softc *);
130 void esp_quick_write_reg(struct ncr53c9x_softc *, int, u_char);
131 int esp_quick_dma_intr(struct ncr53c9x_softc *);
132 int esp_quick_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, int,
133 size_t *);
134 void esp_quick_dma_go(struct ncr53c9x_softc *);
135
136 void esp_intr(void *);
137 void esp_dualbus_intr(void *);
138 static struct esp_softc *esp0, *esp1;
139
140 static inline int esp_dafb_have_dreq(struct esp_softc *);
141 static inline int esp_iosb_have_dreq(struct esp_softc *);
142 int (*esp_have_dreq)(struct esp_softc *);
143
144 struct ncr53c9x_glue esp_glue = {
145 esp_read_reg,
146 esp_write_reg,
147 esp_dma_isintr,
148 esp_dma_reset,
149 esp_dma_intr,
150 esp_dma_setup,
151 esp_dma_go,
152 esp_dma_stop,
153 esp_dma_isactive,
154 NULL, /* gl_clear_latched_intr */
155 };
156
157 int
158 espmatch(device_t parent, cfdata_t cf, void *aux)
159 {
160 struct obio_attach_args *oa = aux;
161
162 if (oa->oa_addr == 0 && mac68k_machine.scsi96) {
163 return 1;
164 }
165 if (oa->oa_addr == 1 && mac68k_machine.scsi96_2) {
166 return 1;
167 }
168 return 0;
169 }
170
171 /*
172 * Attach this instance, and then all the sub-devices
173 */
174 void
175 espattach(device_t parent, device_t self, void *aux)
176 {
177 struct esp_softc *esc = device_private(self);
178 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
179 struct obio_attach_args *oa = aux;
180 int quick = 0;
181 unsigned long reg_offset;
182 extern vaddr_t SCSIBase;
183
184 sc->sc_dev = self;
185
186 reg_offset = SCSIBase - IOBase;
187 esc->sc_tag = oa->oa_tag;
188
189 /*
190 * For Wombat, Primus and Optimus motherboards, DREQ is
191 * visible on bit 0 of the IOSB's emulated VIA2 vIFR (and
192 * the scsi registers are offset 0x1000 bytes from IOBase).
193 *
194 * For the Q700/900/950 it's at f9800024 for bus 0 and
195 * f9800028 for bus 1 (900/950). For these machines, that is also
196 * a (12-bit) configuration register for DAFB's control of the
197 * pseudo-DMA timing. The default value is 0x1d1.
198 */
199 esp_have_dreq = esp_dafb_have_dreq;
200 if (oa->oa_addr == 0) {
201 if (reg_offset == 0x10000) {
202 quick = 1;
203 esp_have_dreq = esp_iosb_have_dreq;
204 } else if (reg_offset == 0x18000) {
205 quick = 0;
206 } else {
207 if (bus_space_map(esc->sc_tag, 0xf9800024,
208 4, 0, &esc->sc_bsh)) {
209 aprint_error(": failed to map 4"
210 " at 0xf9800024.\n");
211 } else {
212 quick = 1;
213 bus_space_write_4(esc->sc_tag,
214 esc->sc_bsh, 0, 0x1d1);
215 }
216 }
217 } else {
218 if (bus_space_map(esc->sc_tag, 0xf9800028,
219 4, 0, &esc->sc_bsh)) {
220 aprint_error(": failed to map 4 at 0xf9800028.\n");
221 } else {
222 quick = 1;
223 bus_space_write_4(esc->sc_tag, esc->sc_bsh, 0, 0x1d1);
224 }
225 }
226 if (quick) {
227 esp_glue.gl_write_reg = esp_quick_write_reg;
228 esp_glue.gl_dma_intr = esp_quick_dma_intr;
229 esp_glue.gl_dma_setup = esp_quick_dma_setup;
230 esp_glue.gl_dma_go = esp_quick_dma_go;
231 }
232
233 /*
234 * Set up the glue for MI code early; we use some of it here.
235 */
236 sc->sc_glue = &esp_glue;
237
238 /*
239 * Save the regs
240 */
241 if (oa->oa_addr == 0) {
242 esp0 = esc;
243
244 esc->sc_reg = (volatile uint8_t *)SCSIBase;
245 via2_register_irq(VIA2_SCSIIRQ, esp_intr, esc);
246 esc->irq_mask = V2IF_SCSIIRQ;
247 if (reg_offset == 0x10000) {
248 /* From the Q650 developer's note */
249 sc->sc_freq = 16500000;
250 } else {
251 sc->sc_freq = 25000000;
252 }
253
254 if (esp_glue.gl_dma_go == esp_quick_dma_go) {
255 aprint_normal(" (quick)");
256 }
257 } else {
258 esp1 = esc;
259
260 esc->sc_reg = (volatile uint8_t *)SCSIBase + 0x402;
261 via2_register_irq(VIA2_SCSIIRQ, esp_dualbus_intr, NULL);
262 esc->irq_mask = 0;
263 sc->sc_freq = 25000000;
264
265 if (esp_glue.gl_dma_go == esp_quick_dma_go) {
266 printf(" (quick)");
267 }
268 }
269
270 aprint_normal(": address %p", esc->sc_reg);
271
272 sc->sc_id = 7;
273
274 /* gimme MHz */
275 sc->sc_freq /= 1000000;
276
277 /*
278 * It is necessary to try to load the 2nd config register here,
279 * to find out what rev the esp chip is, else the esp_reset
280 * will not set up the defaults correctly.
281 */
282 sc->sc_cfg1 = sc->sc_id; /* | NCRCFG1_PARENB; */
283 sc->sc_cfg2 = NCRCFG2_SCSI2;
284 sc->sc_cfg3 = 0;
285 sc->sc_rev = NCR_VARIANT_NCR53C96;
286
287 /*
288 * This is the value used to start sync negotiations
289 * Note that the NCR register "SYNCTP" is programmed
290 * in "clocks per byte", and has a minimum value of 4.
291 * The SCSI period used in negotiation is one-fourth
292 * of the time (in nanoseconds) needed to transfer one byte.
293 * Since the chip's clock is given in MHz, we have the following
294 * formula: 4 * period = (1000 / freq) * 4
295 */
296 sc->sc_minsync = 1000 / sc->sc_freq;
297
298 /* We need this to fit into the TCR... */
299 sc->sc_maxxfer = 64 * 1024;
300
301 switch (current_mac_model->machineid) {
302 case MACH_MACQ630:
303 /* XXX on LC630 64k xfer causes timeout error */
304 sc->sc_maxxfer = 63 * 1024;
305 break;
306 }
307
308 if (!quick) {
309 sc->sc_minsync = 0; /* No synchronous xfers w/o DMA */
310 sc->sc_maxxfer = 8 * 1024;
311 }
312
313 /*
314 * Configure interrupts.
315 */
316 if (esc->irq_mask) {
317 via2_reg(vPCR) = 0x22;
318 via2_reg(vIFR) = esc->irq_mask;
319 via2_reg(vIER) = 0x80 | esc->irq_mask;
320 }
321
322 /*
323 * Now try to attach all the sub-devices
324 */
325 sc->sc_adapter.adapt_minphys = minphys;
326 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
327 ncr53c9x_attach(sc);
328 }
329
330 /*
331 * Glue functions.
332 */
333
334 uint8_t
335 esp_read_reg(struct ncr53c9x_softc *sc, int reg)
336 {
337 struct esp_softc *esc = (struct esp_softc *)sc;
338
339 return esc->sc_reg[reg * 16];
340 }
341
342 void
343 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
344 {
345 struct esp_softc *esc = (struct esp_softc *)sc;
346 uint8_t v = val;
347
348 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {
349 v = NCRCMD_TRANS;
350 }
351 esc->sc_reg[reg * 16] = v;
352 }
353
354 void
355 esp_dma_stop(struct ncr53c9x_softc *sc)
356 {
357 }
358
359 int
360 esp_dma_isactive(struct ncr53c9x_softc *sc)
361 {
362 struct esp_softc *esc = (struct esp_softc *)sc;
363
364 return esc->sc_active;
365 }
366
367 int
368 esp_dma_isintr(struct ncr53c9x_softc *sc)
369 {
370 struct esp_softc *esc = (struct esp_softc *)sc;
371
372 return esc->sc_reg[NCR_STAT * 16] & 0x80;
373 }
374
375 void
376 esp_dma_reset(struct ncr53c9x_softc *sc)
377 {
378 struct esp_softc *esc = (struct esp_softc *)sc;
379
380 esc->sc_active = 0;
381 esc->sc_tc = 0;
382 }
383
384 int
385 esp_dma_intr(struct ncr53c9x_softc *sc)
386 {
387 struct esp_softc *esc = (struct esp_softc *)sc;
388 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg;
389 uint8_t *p;
390 u_int espphase, espstat, espintr;
391 int cnt, s;
392
393 if (esc->sc_active == 0) {
394 printf("dma_intr--inactive DMA\n");
395 return -1;
396 }
397
398 if ((sc->sc_espintr & NCRINTR_BS) == 0) {
399 esc->sc_active = 0;
400 return 0;
401 }
402
403 cnt = *esc->sc_dmalen;
404 if (*esc->sc_dmalen == 0) {
405 printf("data interrupt, but no count left.");
406 }
407
408 p = *esc->sc_dmaaddr;
409 espphase = sc->sc_phase;
410 espstat = (u_int)sc->sc_espstat;
411 espintr = (u_int)sc->sc_espintr;
412 cmdreg = esc->sc_reg + NCR_CMD * 16;
413 fiforeg = esc->sc_reg + NCR_FIFO * 16;
414 statreg = esc->sc_reg + NCR_STAT * 16;
415 intrreg = esc->sc_reg + NCR_INTR * 16;
416 do {
417 if (esc->sc_datain) {
418 *p++ = *fiforeg;
419 cnt--;
420 if (espphase == DATA_IN_PHASE) {
421 *cmdreg = NCRCMD_TRANS;
422 } else {
423 esc->sc_active = 0;
424 }
425 } else {
426 if ( (espphase == DATA_OUT_PHASE)
427 || (espphase == MESSAGE_OUT_PHASE)) {
428 *fiforeg = *p++;
429 cnt--;
430 *cmdreg = NCRCMD_TRANS;
431 } else {
432 esc->sc_active = 0;
433 }
434 }
435
436 if (esc->sc_active) {
437 while (!(*statreg & 0x80));
438 s = splhigh();
439 espstat = *statreg;
440 espintr = *intrreg;
441 espphase = (espintr & NCRINTR_DIS)
442 ? /* Disconnected */ BUSFREE_PHASE
443 : espstat & PHASE_MASK;
444 splx(s);
445 }
446 } while (esc->sc_active && (espintr & NCRINTR_BS));
447 sc->sc_phase = espphase;
448 sc->sc_espstat = (u_char)espstat;
449 sc->sc_espintr = (u_char)espintr;
450 *esc->sc_dmaaddr = p;
451 *esc->sc_dmalen = cnt;
452
453 if (*esc->sc_dmalen == 0) {
454 esc->sc_tc = NCRSTAT_TC;
455 }
456 sc->sc_espstat |= esc->sc_tc;
457 return 0;
458 }
459
460 int
461 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
462 int datain, size_t *dmasize)
463 {
464 struct esp_softc *esc = (struct esp_softc *)sc;
465
466 esc->sc_dmaaddr = addr;
467 esc->sc_dmalen = len;
468 esc->sc_datain = datain;
469 esc->sc_dmasize = *dmasize;
470 esc->sc_tc = 0;
471
472 return 0;
473 }
474
475 void
476 esp_dma_go(struct ncr53c9x_softc *sc)
477 {
478 struct esp_softc *esc = (struct esp_softc *)sc;
479
480 if (esc->sc_datain == 0) {
481 esc->sc_reg[NCR_FIFO * 16] = **esc->sc_dmaaddr;
482 (*esc->sc_dmalen)--;
483 (*esc->sc_dmaaddr)++;
484 }
485 esc->sc_active = 1;
486 }
487
488 void
489 esp_quick_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
490 {
491 struct esp_softc *esc = (struct esp_softc *)sc;
492
493 esc->sc_reg[reg * 16] = val;
494 }
495
496 #if DEBUG
497 int mac68k_esp_debug=0;
498 #endif
499
500 int
501 esp_quick_dma_intr(struct ncr53c9x_softc *sc)
502 {
503 struct esp_softc *esc = (struct esp_softc *)sc;
504 int trans=0, resid=0;
505
506 if (esc->sc_active == 0)
507 panic("dma_intr--inactive DMA");
508
509 esc->sc_active = 0;
510
511 if (esc->sc_dmasize == 0) {
512 int res;
513
514 res = NCR_READ_REG(sc, NCR_TCL);
515 res += NCR_READ_REG(sc, NCR_TCM) << 8;
516 /* This can happen in the case of a TRPAD operation */
517 /* Pretend that it was complete */
518 sc->sc_espstat |= NCRSTAT_TC;
519 #if DEBUG
520 if (mac68k_esp_debug) {
521 printf("dmaintr: DMA xfer of zero xferred %d\n",
522 65536 - res);
523 }
524 #endif
525 return 0;
526 }
527
528 if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
529 if (esc->sc_datain == 0) {
530 resid = NCR_READ_REG(sc, NCR_FFLAG) & 0x1f;
531 #if DEBUG
532 if (mac68k_esp_debug) {
533 printf("Write FIFO residual %d bytes\n", resid);
534 }
535 #endif
536 }
537 resid += NCR_READ_REG(sc, NCR_TCL);
538 resid += NCR_READ_REG(sc, NCR_TCM) << 8;
539 if (resid == 0)
540 resid = 65536;
541 }
542
543 trans = esc->sc_dmasize - resid;
544 if (trans < 0) {
545 printf("dmaintr: trans < 0????");
546 trans = *esc->sc_dmalen;
547 }
548
549 NCR_DMA(("dmaintr: trans %d, resid %d.\n", trans, resid));
550 #if DEBUG
551 if (mac68k_esp_debug) {
552 printf("eqd_intr: trans %d, resid %d.\n", trans, resid);
553 }
554 #endif
555 *esc->sc_dmaaddr += trans;
556 *esc->sc_dmalen -= trans;
557
558 return 0;
559 }
560
561 int
562 esp_quick_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
563 int datain, size_t *dmasize)
564 {
565 struct esp_softc *esc = (struct esp_softc *)sc;
566
567 esc->sc_dmaaddr = addr;
568 esc->sc_dmalen = len;
569
570 if (*len & 1) {
571 esc->sc_pad = 1;
572 } else {
573 esc->sc_pad = 0;
574 }
575
576 esc->sc_datain = datain;
577 esc->sc_dmasize = *dmasize;
578
579 #if DIAGNOSTIC
580 if (esc->sc_dmasize == 0) {
581 /* This can happen in the case of a TRPAD operation */
582 }
583 #endif
584 #if DEBUG
585 if (mac68k_esp_debug) {
586 printf("eqd_setup: addr %lx, len %lx, in? %d, dmasize %lx\n",
587 (long) *addr, (long) *len, datain, (long) esc->sc_dmasize);
588 }
589 #endif
590
591 return 0;
592 }
593
594 static inline int
595 esp_dafb_have_dreq(struct esp_softc *esc)
596 {
597
598 return *(volatile uint32_t *)(esc->sc_bsh.base) & 0x200;
599 }
600
601 static inline int
602 esp_iosb_have_dreq(struct esp_softc *esc)
603 {
604
605 return via2_reg(vIFR) & V2IF_SCSIDRQ;
606 }
607
608 static volatile int espspl = -1;
609
610 /*
611 * Apple "DMA" is weird.
612 *
613 * Basically, the CPU acts like the DMA controller. The DREQ/ off the
614 * chip goes to a register that we've mapped at attach time (on the
615 * IOSB or DAFB, depending on the machine). Apple also provides some
616 * space for which the memory controller handshakes data to/from the
617 * NCR chip with the DACK/ line. This space appears to be mapped over
618 * and over, every 4 bytes, but only the lower 16 bits are valid (but
619 * reading the upper 16 bits will handshake DACK/ just fine, so if you
620 * read *u_int16_t++ = *u_int16_t++ in a loop, you'll get
621 * <databyte><databyte>0xff0xff<databyte><databyte>0xff0xff...
622 *
623 * When you're attempting to read or write memory to this DACK/ed space,
624 * and the NCR is not ready for some timeout period, the system will
625 * generate a bus error. This might be for one of several reasons:
626 *
627 * 1) (on write) The FIFO is full and is not draining.
628 * 2) (on read) The FIFO is empty and is not filling.
629 * 3) An interrupt condition has occurred.
630 * 4) Anything else?
631 *
632 * So if a bus error occurs, we first turn off the nofault bus error handler,
633 * then we check for an interrupt (which would render the first two
634 * possibilities moot). If there's no interrupt, check for a DREQ/. If we
635 * have that, then attempt to resume stuffing (or unstuffing) the FIFO. If
636 * neither condition holds, pause briefly and check again.
637 *
638 * NOTE!!! In order to make allowances for the hardware structure of
639 * the mac, spl values in here are hardcoded!!!!!!!!!
640 * This is done to allow serial interrupts to get in during
641 * scsi transfers. This is ugly.
642 */
643 void
644 esp_quick_dma_go(struct ncr53c9x_softc *sc)
645 {
646 struct esp_softc *esc = (struct esp_softc *)sc;
647 extern long mac68k_a2_fromfault;
648 extern int *nofault;
649 label_t faultbuf;
650 uint16_t volatile *pdma;
651 uint16_t *addr;
652 int len, res;
653 uint16_t cnt32, cnt2;
654 volatile uint8_t *statreg;
655
656 esc->sc_active = 1;
657
658 espspl = splhigh();
659
660 addr = (uint16_t *)*esc->sc_dmaaddr;
661 len = esc->sc_dmasize;
662
663 restart_dmago:
664 #if DEBUG
665 if (mac68k_esp_debug) {
666 printf("eqdg: a %lx, l %lx, in? %d ... ",
667 (long) addr, (long) len, esc->sc_datain);
668 }
669 #endif
670 nofault = (int *)&faultbuf;
671 if (setjmp((label_t *)nofault)) {
672 int i = 0;
673
674 nofault = NULL;
675 #if DEBUG
676 if (mac68k_esp_debug) {
677 printf("be\n");
678 }
679 #endif
680 /*
681 * Bus error...
682 * So, we first check for an interrupt. If we have
683 * one, go handle it. Next we check for DREQ/. If
684 * we have it, then we restart the transfer. If
685 * neither, then loop until we get one or the other.
686 */
687 statreg = esc->sc_reg + NCR_STAT * 16;
688 for (;;) {
689 spl2(); /* Give serial a chance... */
690 splhigh(); /* That's enough... */
691
692 if (*statreg & 0x80) {
693 goto gotintr;
694 }
695
696 if (esp_have_dreq(esc)) {
697 /*
698 * Get the remaining length from the address
699 * differential.
700 */
701 addr = (uint16_t *)mac68k_a2_fromfault;
702 len = esc->sc_dmasize -
703 ((long)addr - (long)*esc->sc_dmaaddr);
704
705 if (esc->sc_datain == 0) {
706 /*
707 * Let the FIFO drain before we read
708 * the transfer count.
709 * Do we need to do this?
710 * Can we do this?
711 */
712 while (NCR_READ_REG(sc, NCR_FFLAG)
713 & 0x1f);
714 /*
715 * Get the length from the transfer
716 * counters.
717 */
718 res = NCR_READ_REG(sc, NCR_TCL);
719 res += NCR_READ_REG(sc, NCR_TCM) << 8;
720 /*
721 * If they don't agree,
722 * adjust accordingly.
723 */
724 while (res > len) {
725 len+=2; addr--;
726 }
727 if (res != len) {
728 panic("%s: res %d != len %d",
729 __func__, res, len);
730 }
731 }
732 break;
733 }
734
735 DELAY(1);
736 if (i++ > 1000000)
737 panic("%s: Bus error, but no condition! Argh!",
738 __func__);
739 }
740 goto restart_dmago;
741 }
742
743 len &= ~1;
744
745 statreg = esc->sc_reg + NCR_STAT * 16;
746 pdma = (volatile uint16_t *)(esc->sc_reg + 0x100);
747
748 /*
749 * These loops are unrolled into assembly for two reasons:
750 * 1) We can make sure that they are as efficient as possible, and
751 * 2) (more importantly) we need the address that we are reading
752 * from or writing to to be in a2.
753 */
754 cnt32 = len / 32;
755 cnt2 = (len % 32) / 2;
756 if (esc->sc_datain == 0) {
757 /* while (cnt32--) { 16 instances of *pdma = *addr++; } */
758 /* while (cnt2--) { *pdma = *addr++; } */
759 __asm volatile (
760 " movl %1, %%a2 \n"
761 " movl %2, %%a3 \n"
762 " movw %3, %%d2 \n"
763 " cmpw #0, %%d2 \n"
764 " beq 2f \n"
765 " subql #1, %%d2 \n"
766 "1: movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
767 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
768 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
769 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
770 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
771 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
772 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
773 " movw %%a2@+,%%a3@; movw %%a2@+,%%a3@ \n"
774 " movw #8704,%%sr \n"
775 " movw #9728,%%sr \n"
776 " dbra %%d2, 1b \n"
777 "2: movw %4, %%d2 \n"
778 " cmpw #0, %%d2 \n"
779 " beq 4f \n"
780 " subql #1, %%d2 \n"
781 "3: movw %%a2@+,%%a3@ \n"
782 " dbra %%d2, 3b \n"
783 "4: movl %%a2, %0"
784 : "=g" (addr)
785 : "0" (addr), "g" (pdma), "g" (cnt32), "g" (cnt2)
786 : "a2", "a3", "d2");
787 if (esc->sc_pad) {
788 volatile uint8_t *c;
789 c = (volatile uint8_t *) addr;
790 /* Wait for DREQ */
791 while (!esp_have_dreq(esc)) {
792 if (*statreg & 0x80) {
793 nofault = NULL;
794 goto gotintr;
795 }
796 }
797 *(volatile int8_t *)pdma = *c;
798 }
799 } else {
800 /* while (cnt32--) { 16 instances of *addr++ = *pdma; } */
801 /* while (cnt2--) { *addr++ = *pdma; } */
802 __asm volatile (
803 " movl %1, %%a2 \n"
804 " movl %2, %%a3 \n"
805 " movw %3, %%d2 \n"
806 " cmpw #0, %%d2 \n"
807 " beq 6f \n"
808 " subql #1, %%d2 \n"
809 "5: movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
810 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
811 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
812 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
813 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
814 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
815 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
816 " movw %%a3@,%%a2@+; movw %%a3@,%%a2@+ \n"
817 " movw #8704,%%sr \n"
818 " movw #9728,%%sr \n"
819 " dbra %%d2, 5b \n"
820 "6: movw %4, %%d2 \n"
821 " cmpw #0, %%d2 \n"
822 " beq 8f \n"
823 " subql #1, %%d2 \n"
824 "7: movw %%a3@,%%a2@+ \n"
825 " dbra %%d2, 7b \n"
826 "8: movl %%a2, %0"
827 : "=g" (addr)
828 : "0" (addr), "g" (pdma), "g" (cnt32), "g" (cnt2)
829 : "a2", "a3", "d2");
830 if (esc->sc_pad) {
831 volatile uint8_t *c;
832 c = (volatile int8_t *)addr;
833 /* Wait for DREQ */
834 while (!esp_have_dreq(esc)) {
835 if (*statreg & 0x80) {
836 nofault = NULL;
837 goto gotintr;
838 }
839 }
840 *c = *(volatile uint8_t *)pdma;
841 }
842 }
843
844 nofault = NULL;
845
846 /*
847 * If we have not received an interrupt yet, we should shortly,
848 * and we can't prevent it, so return and wait for it.
849 */
850 if ((*statreg & 0x80) == 0) {
851 #if DEBUG
852 if (mac68k_esp_debug) {
853 printf("g.\n");
854 }
855 #endif
856 if (espspl != -1)
857 splx(espspl);
858 espspl = -1;
859 return;
860 }
861
862 gotintr:
863 #if DEBUG
864 if (mac68k_esp_debug) {
865 printf("g!\n");
866 }
867 #endif
868 /*
869 * We have been called from the MI ncr53c9x_intr() handler,
870 * which protects itself against multiple invocation with a
871 * simple_lock. Follow the example of ncr53c9x_poll().
872 */
873 simple_unlock(&sc->sc_lock);
874 ncr53c9x_intr(sc);
875 simple_lock(&sc->sc_lock);
876 if (espspl != -1)
877 splx(espspl);
878 espspl = -1;
879 }
880
881 void
882 esp_intr(void *sc)
883 {
884 struct esp_softc *esc = (struct esp_softc *)sc;
885
886 if (esc->sc_reg[NCR_STAT * 16] & 0x80) {
887 ncr53c9x_intr((struct ncr53c9x_softc *)esp0);
888 }
889 }
890
891 void
892 esp_dualbus_intr(void *sc)
893 {
894 if (esp0 && (esp0->sc_reg[NCR_STAT * 16] & 0x80)) {
895 ncr53c9x_intr((struct ncr53c9x_softc *)esp0);
896 }
897
898 if (esp1 && (esp1->sc_reg[NCR_STAT * 16] & 0x80)) {
899 ncr53c9x_intr((struct ncr53c9x_softc *)esp1);
900 }
901 }
NetBSD on the FriendlyARM MINI2440