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[netbsd-mini2440.git] / sys / arch / macppc / dev / cuda.c
blobe0be7fa08472849ecc4aeaa436ba689f3a742d48
1 /* $NetBSD: cuda.c,v 1.14 2009/03/18 10:22:31 cegger Exp $ */
2
3 /*-
4 * Copyright (c) 2006 Michael Lorenz
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.14 2009/03/18 10:22:31 cegger Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/device.h>
36 #include <sys/proc.h>
37 #include <sys/mutex.h>
38
39 #include <machine/bus.h>
40 #include <machine/autoconf.h>
41 #include <machine/pio.h>
42 #include <dev/clock_subr.h>
43 #include <dev/i2c/i2cvar.h>
44
45 #include <macppc/dev/viareg.h>
46 #include <macppc/dev/cudavar.h>
47
48 #include <dev/ofw/openfirm.h>
49 #include <dev/adb/adbvar.h>
50 #include "opt_cuda.h"
51
52 #ifdef CUDA_DEBUG
53 #define DPRINTF printf
54 #else
55 #define DPRINTF while (0) printf
56 #endif
57
58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */
59 #define CUDA_IDLE 0x2 /* the bus is currently idle */
60 #define CUDA_OUT 0x3 /* sending out a command */
61 #define CUDA_IN 0x4 /* receiving data */
62 #define CUDA_POLLING 0x5 /* polling - II only */
63
64 static void cuda_attach(device_t, device_t, void *);
65 static int cuda_match(device_t, struct cfdata *, void *);
66 static void cuda_autopoll(void *, int);
67
68 static int cuda_intr(void *);
69
70 typedef struct _cuda_handler {
71 int (*handler)(void *, int, uint8_t *);
72 void *cookie;
73 } CudaHandler;
74
75 struct cuda_softc {
76 device_t sc_dev;
77 void *sc_ih;
78 CudaHandler sc_handlers[16];
79 struct todr_chip_handle sc_todr;
80 struct adb_bus_accessops sc_adbops;
81 struct i2c_controller sc_i2c;
82 kmutex_t sc_buslock;
83 bus_space_tag_t sc_memt;
84 bus_space_handle_t sc_memh;
85 int sc_node;
86 int sc_state;
87 int sc_waiting;
88 int sc_polling;
89 int sc_sent;
90 int sc_out_length;
91 int sc_received;
92 int sc_iic_done;
93 int sc_error;
94 /* time */
95 uint32_t sc_tod;
96 uint32_t sc_autopoll;
97 uint32_t sc_todev;
98 /* ADB */
99 void (*sc_adb_handler)(void *, int, uint8_t *);
100 void *sc_adb_cookie;
101 uint32_t sc_i2c_read_len;
102 /* internal buffers */
103 uint8_t sc_in[256];
104 uint8_t sc_out[256];
105 };
106
107 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc),
108 cuda_match, cuda_attach, NULL, NULL);
109
110 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t);
111 static inline uint8_t cuda_read_reg(struct cuda_softc *, int);
112 static void cuda_idle(struct cuda_softc *);
113 static void cuda_tip(struct cuda_softc *);
114 static void cuda_clear_tip(struct cuda_softc *);
115 static void cuda_in(struct cuda_softc *);
116 static void cuda_out(struct cuda_softc *);
117 static void cuda_toggle_ack(struct cuda_softc *);
118 static void cuda_ack_off(struct cuda_softc *);
119 static int cuda_intr_state(struct cuda_softc *);
120
121 static void cuda_init(struct cuda_softc *);
122
123 /*
124 * send a message to Cuda.
125 */
126 /* cookie, flags, length, data */
127 static int cuda_send(void *, int, int, uint8_t *);
128 static void cuda_poll(void *);
129 static void cuda_adb_poll(void *);
130 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *);
131
132 static int cuda_error_handler(void *, int, uint8_t *);
133
134 static int cuda_todr_handler(void *, int, uint8_t *);
135 static int cuda_todr_set(todr_chip_handle_t, struct timeval *);
136 static int cuda_todr_get(todr_chip_handle_t, struct timeval *);
137
138 static int cuda_adb_handler(void *, int, uint8_t *);
139 static void cuda_final(device_t);
140
141 static struct cuda_attach_args *cuda0 = NULL;
142
143 /* ADB bus attachment stuff */
144 static int cuda_adb_send(void *, int, int, int, uint8_t *);
145 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *);
146
147 /* i2c stuff */
148 static int cuda_i2c_acquire_bus(void *, int);
149 static void cuda_i2c_release_bus(void *, int);
150 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t,
151 void *, size_t, int);
152
153 static int
154 cuda_match(device_t parent, struct cfdata *cf, void *aux)
155 {
156 struct confargs *ca = aux;
157
158 if (ca->ca_nreg < 8)
159 return 0;
160
161 if (ca->ca_nintr < 4)
162 return 0;
163
164 if (strcmp(ca->ca_name, "via-cuda") == 0) {
165 return 10; /* beat adb* at obio? */
166 }
167
168 return 0;
169 }
170
171 static void
172 cuda_attach(device_t parent, device_t dev, void *aux)
173 {
174 struct confargs *ca = aux;
175 struct cuda_softc *sc = device_private(dev);
176 struct i2cbus_attach_args iba;
177 static struct cuda_attach_args caa;
178 int irq = ca->ca_intr[0];
179 int node, i, child;
180 char name[32];
181
182 sc->sc_dev = dev;
183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1");
184 if (node)
185 OF_getprop(node, "interrupts", &irq, 4);
186
187 printf(" irq %d", irq);
188
189 sc->sc_node = ca->ca_node;
190 sc->sc_memt = ca->ca_tag;
191
192 sc->sc_sent = 0;
193 sc->sc_received = 0;
194 sc->sc_waiting = 0;
195 sc->sc_polling = 0;
196 sc->sc_state = CUDA_NOTREADY;
197 sc->sc_error = 0;
198 sc->sc_i2c_read_len = 0;
199
200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr,
201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) {
202
203 printf(": unable to map registers\n");
204 return;
205 }
206 sc->sc_ih = intr_establish(irq, IST_EDGE, IPL_TTY, cuda_intr, sc);
207 printf("\n");
208
209 for (i = 0; i < 16; i++) {
210 sc->sc_handlers[i].handler = NULL;
211 sc->sc_handlers[i].cookie = NULL;
212 }
213
214 cuda_init(sc);
215
216 /* now attach children */
217 config_interrupts(dev, cuda_final);
218 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc);
219 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc);
220
221 child = OF_child(ca->ca_node);
222 while (child != 0) {
223
224 if (OF_getprop(child, "name", name, 32) == 0)
225 continue;
226 if (strncmp(name, "adb", 4) == 0) {
227
228 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc);
229 sc->sc_adbops.cookie = sc;
230 sc->sc_adbops.send = cuda_adb_send;
231 sc->sc_adbops.poll = cuda_adb_poll;
232 sc->sc_adbops.autopoll = cuda_autopoll;
233 sc->sc_adbops.set_handler = cuda_adb_set_handler;
234 config_found_ia(dev, "adb_bus", &sc->sc_adbops,
235 nadb_print);
236 } else if (strncmp(name, "rtc", 4) == 0) {
237
238 sc->sc_todr.todr_gettime = cuda_todr_get;
239 sc->sc_todr.todr_settime = cuda_todr_set;
240 sc->sc_todr.cookie = sc;
241 todr_attach(&sc->sc_todr);
242 }
243 child = OF_peer(child);
244 }
245
246 caa.cookie = sc;
247 caa.set_handler = cuda_set_handler;
248 caa.send = cuda_send;
249 caa.poll = cuda_poll;
250 #if notyet
251 config_found(dev, &caa, cuda_print);
252 #endif
253 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
254 iba.iba_tag = &sc->sc_i2c;
255 sc->sc_i2c.ic_cookie = sc;
256 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus;
257 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus;
258 sc->sc_i2c.ic_send_start = NULL;
259 sc->sc_i2c.ic_send_stop = NULL;
260 sc->sc_i2c.ic_initiate_xfer = NULL;
261 sc->sc_i2c.ic_read_byte = NULL;
262 sc->sc_i2c.ic_write_byte = NULL;
263 sc->sc_i2c.ic_exec = cuda_i2c_exec;
264 config_found_ia(sc->sc_dev, "i2cbus", &iba, iicbus_print);
265
266 if (cuda0 == NULL)
267 cuda0 = &caa;
268 }
269
270 static void
271 cuda_init(struct cuda_softc *sc)
272 {
273 volatile int i;
274 uint8_t reg;
275
276 reg = cuda_read_reg(sc, vDirB);
277 reg |= 0x30; /* register B bits 4 and 5: outputs */
278 cuda_write_reg(sc, vDirB, reg);
279
280 reg = cuda_read_reg(sc, vDirB);
281 reg &= 0xf7; /* register B bit 3: input */
282 cuda_write_reg(sc, vDirB, reg);
283
284 reg = cuda_read_reg(sc, vACR);
285 reg &= ~vSR_OUT; /* make sure SR is set to IN */
286 cuda_write_reg(sc, vACR, reg);
287
288 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10);
289
290 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */
291
292 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */
293 cuda_idle(sc); /* set ADB bus state to idle */
294
295 /* sort of a device reset */
296 i = cuda_read_reg(sc, vSR); /* clear interrupt */
297 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */
298 cuda_idle(sc); /* reset state to idle */
299 delay(150);
300 cuda_tip(sc); /* signal start of frame */
301 delay(150);
302 cuda_toggle_ack(sc);
303 delay(150);
304 cuda_clear_tip(sc);
305 delay(150);
306 cuda_idle(sc); /* back to idle state */
307 i = cuda_read_reg(sc, vSR); /* clear interrupt */
308 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */
309 }
310
311 static void
312 cuda_final(device_t dev)
313 {
314 struct cuda_softc *sc = device_private(dev);
315
316 sc->sc_polling = 0;
317 }
318
319 static inline void
320 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value)
321 {
322
323 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value);
324 }
325
326 static inline uint8_t
327 cuda_read_reg(struct cuda_softc *sc, int offset)
328 {
329
330 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset);
331 }
332
333 static int
334 cuda_set_handler(void *cookie, int type,
335 int (*handler)(void *, int, uint8_t *), void *hcookie)
336 {
337 struct cuda_softc *sc = cookie;
338 CudaHandler *me;
339
340 if ((type >= 0) && (type < 16)) {
341 me = &sc->sc_handlers[type];
342 me->handler = handler;
343 me->cookie = hcookie;
344 return 0;
345 }
346 return -1;
347 }
348
349 static int
350 cuda_send(void *cookie, int poll, int length, uint8_t *msg)
351 {
352 struct cuda_softc *sc = cookie;
353 int s;
354
355 DPRINTF("cuda_send %08x\n", (uint32_t)cookie);
356 if (sc->sc_state == CUDA_NOTREADY)
357 return -1;
358
359 s = splhigh();
360
361 if ((sc->sc_state == CUDA_IDLE) /*&&
362 ((cuda_read_reg(sc, vBufB) & vPB3) == vPB3)*/) {
363 /* fine */
364 DPRINTF("chip is idle\n");
365 } else {
366 DPRINTF("cuda state is %d\n", sc->sc_state);
367 if (sc->sc_waiting == 0) {
368 sc->sc_waiting = 1;
369 } else {
370 splx(s);
371 return -1;
372 }
373 }
374
375 sc->sc_error = 0;
376 memcpy(sc->sc_out, msg, length);
377 sc->sc_out_length = length;
378 sc->sc_sent = 0;
379
380 if (sc->sc_waiting != 1) {
381
382 delay(150);
383 sc->sc_state = CUDA_OUT;
384 cuda_out(sc);
385 cuda_write_reg(sc, vSR, sc->sc_out[0]);
386 cuda_ack_off(sc);
387 cuda_tip(sc);
388 }
389 sc->sc_waiting = 1;
390
391 if (sc->sc_polling || poll || cold) {
392 cuda_poll(sc);
393 }
394
395 splx(s);
396
397 return 0;
398 }
399
400 static void
401 cuda_poll(void *cookie)
402 {
403 struct cuda_softc *sc = cookie;
404 int s;
405
406 DPRINTF("polling\n");
407 while ((sc->sc_state != CUDA_IDLE) ||
408 (cuda_intr_state(sc)) ||
409 (sc->sc_waiting == 1)) {
410 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) {
411 s = splhigh();
412 cuda_intr(sc);
413 splx(s);
414 }
415 }
416 }
417
418 static void
419 cuda_adb_poll(void *cookie)
420 {
421 struct cuda_softc *sc = cookie;
422 int s;
423
424 s = splhigh();
425 cuda_intr(sc);
426 splx(s);
427 }
428
429 static void
430 cuda_idle(struct cuda_softc *sc)
431 {
432 uint8_t reg;
433
434 reg = cuda_read_reg(sc, vBufB);
435 reg |= (vPB4 | vPB5);
436 cuda_write_reg(sc, vBufB, reg);
437 }
438
439 static void
440 cuda_tip(struct cuda_softc *sc)
441 {
442 uint8_t reg;
443
444 reg = cuda_read_reg(sc, vBufB);
445 reg &= ~vPB5;
446 cuda_write_reg(sc, vBufB, reg);
447 }
448
449 static void
450 cuda_clear_tip(struct cuda_softc *sc)
451 {
452 uint8_t reg;
453
454 reg = cuda_read_reg(sc, vBufB);
455 reg |= vPB5;
456 cuda_write_reg(sc, vBufB, reg);
457 }
458
459 static void
460 cuda_in(struct cuda_softc *sc)
461 {
462 uint8_t reg;
463
464 reg = cuda_read_reg(sc, vACR);
465 reg &= ~vSR_OUT;
466 cuda_write_reg(sc, vACR, reg);
467 }
468
469 static void
470 cuda_out(struct cuda_softc *sc)
471 {
472 uint8_t reg;
473
474 reg = cuda_read_reg(sc, vACR);
475 reg |= vSR_OUT;
476 cuda_write_reg(sc, vACR, reg);
477 }
478
479 static void
480 cuda_toggle_ack(struct cuda_softc *sc)
481 {
482 uint8_t reg;
483
484 reg = cuda_read_reg(sc, vBufB);
485 reg ^= vPB4;
486 cuda_write_reg(sc, vBufB, reg);
487 }
488
489 static void
490 cuda_ack_off(struct cuda_softc *sc)
491 {
492 uint8_t reg;
493
494 reg = cuda_read_reg(sc, vBufB);
495 reg |= vPB4;
496 cuda_write_reg(sc, vBufB, reg);
497 }
498
499 static int
500 cuda_intr_state(struct cuda_softc *sc)
501 {
502 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0);
503 }
504
505 static int
506 cuda_intr(void *arg)
507 {
508 struct cuda_softc *sc = arg;
509 int i, ending, type;
510 uint8_t reg;
511
512 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */
513 DPRINTF("[");
514 if ((reg & 0x80) == 0) {
515 DPRINTF("irq %02x]", reg);
516 return 0; /* No interrupts to process */
517 }
518 DPRINTF(":");
519
520 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */
521
522 switch_start:
523 switch (sc->sc_state) {
524 case CUDA_IDLE:
525 /*
526 * This is an unexpected packet, so grab the first (dummy)
527 * byte, set up the proper vars, and tell the chip we are
528 * starting to receive the packet by setting the TIP bit.
529 */
530 sc->sc_in[1] = cuda_read_reg(sc, vSR);
531 DPRINTF("start: %02x", sc->sc_in[1]);
532 if (cuda_intr_state(sc) == 0) {
533 /* must have been a fake start */
534 DPRINTF(" ... fake start\n");
535 if (sc->sc_waiting) {
536 /* start over */
537 delay(150);
538 sc->sc_state = CUDA_OUT;
539 sc->sc_sent = 0;
540 cuda_out(sc);
541 cuda_write_reg(sc, vSR, sc->sc_out[1]);
542 cuda_ack_off(sc);
543 cuda_tip(sc);
544 }
545 break;
546 }
547
548 cuda_in(sc);
549 cuda_tip(sc);
550
551 sc->sc_received = 1;
552 sc->sc_state = CUDA_IN;
553 DPRINTF(" CUDA_IN");
554 break;
555
556 case CUDA_IN:
557 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR);
558 DPRINTF(" %02x", sc->sc_in[sc->sc_received]);
559 ending = 0;
560 if (sc->sc_received > 255) {
561 /* bitch only once */
562 if (sc->sc_received == 256) {
563 printf("%s: input overflow\n",
564 device_xname(sc->sc_dev));
565 ending = 1;
566 }
567 } else
568 sc->sc_received++;
569 if (sc->sc_received > 3) {
570 if ((sc->sc_in[3] == CMD_IIC) &&
571 (sc->sc_received > (sc->sc_i2c_read_len + 4))) {
572 ending = 1;
573 }
574 }
575
576 /* intr off means this is the last byte (end of frame) */
577 if (cuda_intr_state(sc) == 0) {
578 ending = 1;
579 DPRINTF(".\n");
580 } else {
581 cuda_toggle_ack(sc);
582 }
583
584 if (ending == 1) { /* end of message? */
585
586 sc->sc_in[0] = sc->sc_received - 1;
587
588 /* reset vars and signal the end of this frame */
589 cuda_idle(sc);
590
591 /* check if we have a handler for this message */
592 type = sc->sc_in[1];
593 if ((type >= 0) && (type < 16)) {
594 CudaHandler *me = &sc->sc_handlers[type];
595
596 if (me->handler != NULL) {
597 me->handler(me->cookie,
598 sc->sc_received - 1, &sc->sc_in[1]);
599 } else {
600 printf("no handler for type %02x\n", type);
601 panic("barf");
602 }
603 }
604
605 DPRINTF("CUDA_IDLE");
606 sc->sc_state = CUDA_IDLE;
607
608 sc->sc_received = 0;
609
610 /*
611 * If there is something waiting to be sent out,
612 * set everything up and send the first byte.
613 */
614 if (sc->sc_waiting == 1) {
615
616 DPRINTF("pending write\n");
617 delay(1500); /* required */
618 sc->sc_sent = 0;
619 sc->sc_state = CUDA_OUT;
620
621 /*
622 * If the interrupt is on, we were too slow
623 * and the chip has already started to send
624 * something to us, so back out of the write
625 * and start a read cycle.
626 */
627 if (cuda_intr_state(sc)) {
628 cuda_in(sc);
629 cuda_idle(sc);
630 sc->sc_sent = 0;
631 sc->sc_state = CUDA_IDLE;
632 sc->sc_received = 0;
633 delay(150);
634 DPRINTF("too slow - incoming message\n");
635 goto switch_start;
636 }
637 /*
638 * If we got here, it's ok to start sending
639 * so load the first byte and tell the chip
640 * we want to send.
641 */
642 DPRINTF("sending ");
643
644 cuda_out(sc);
645 cuda_write_reg(sc, vSR,
646 sc->sc_out[sc->sc_sent]);
647 cuda_ack_off(sc);
648 cuda_tip(sc);
649 }
650 }
651 break;
652
653 case CUDA_OUT:
654 i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */
655
656 sc->sc_sent++;
657 if (cuda_intr_state(sc)) { /* ADB intr low during write */
658
659 DPRINTF("incoming msg during send\n");
660 cuda_in(sc); /* make sure SR is set to IN */
661 cuda_idle(sc);
662 sc->sc_sent = 0; /* must start all over */
663 sc->sc_state = CUDA_IDLE; /* new state */
664 sc->sc_received = 0;
665 sc->sc_waiting = 1; /* must retry when done with
666 * read */
667 delay(150);
668 goto switch_start; /* process next state right
669 * now */
670 break;
671 }
672 if (sc->sc_out_length == sc->sc_sent) { /* check for done */
673
674 sc->sc_waiting = 0; /* done writing */
675 sc->sc_state = CUDA_IDLE; /* signal bus is idle */
676 cuda_in(sc);
677 cuda_idle(sc);
678 DPRINTF("done sending\n");
679 } else {
680 /* send next byte */
681 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]);
682 cuda_toggle_ack(sc); /* signal byte ready to
683 * shift */
684 }
685 break;
686
687 case CUDA_NOTREADY:
688 DPRINTF("adb: not yet initialized\n");
689 break;
690
691 default:
692 DPRINTF("intr: unknown ADB state\n");
693 break;
694 }
695
696 DPRINTF("]");
697 return 1;
698 }
699
700 static int
701 cuda_error_handler(void *cookie, int len, uint8_t *data)
702 {
703 struct cuda_softc *sc = cookie;
704
705 /*
706 * something went wrong
707 * byte 3 seems to be the failed command
708 */
709 sc->sc_error = 1;
710 wakeup(&sc->sc_todev);
711 return 0;
712 }
713
714
715 /* real time clock */
716
717 static int
718 cuda_todr_handler(void *cookie, int len, uint8_t *data)
719 {
720 struct cuda_softc *sc = cookie;
721
722 #ifdef CUDA_DEBUG
723 int i;
724 printf("msg: %02x", data[0]);
725 for (i = 1; i < len; i++) {
726 printf(" %02x", data[i]);
727 }
728 printf("\n");
729 #endif
730
731 switch(data[2]) {
732 case CMD_READ_RTC:
733 memcpy(&sc->sc_tod, &data[3], 4);
734 break;
735 case CMD_WRITE_RTC:
736 sc->sc_tod = 0xffffffff;
737 break;
738 case CMD_AUTOPOLL:
739 sc->sc_autopoll = 1;
740 break;
741 case CMD_IIC:
742 sc->sc_iic_done = len;
743 break;
744 }
745 wakeup(&sc->sc_todev);
746 return 0;
747 }
748
749 #define DIFF19041970 2082844800
750
751 static int
752 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp)
753 {
754 struct cuda_softc *sc = tch->cookie;
755 int cnt = 0;
756 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC};
757
758 sc->sc_tod = 0;
759 cuda_send(sc, 0, 2, cmd);
760
761 while ((sc->sc_tod == 0) && (cnt < 10)) {
762 tsleep(&sc->sc_todev, 0, "todr", 10);
763 cnt++;
764 }
765
766 if (sc->sc_tod == 0)
767 return EIO;
768
769 tvp->tv_sec = sc->sc_tod - DIFF19041970;
770 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec);
771 tvp->tv_usec = 0;
772 return 0;
773 }
774
775 static int
776 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp)
777 {
778 struct cuda_softc *sc = tch->cookie;
779 uint32_t sec;
780 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0};
781
782 sec = tvp->tv_sec + DIFF19041970;
783 memcpy(&cmd[2], &sec, 4);
784 sc->sc_tod = 0;
785 if (cuda_send(sc, 0, 6, cmd) == 0) {
786 while (sc->sc_tod == 0) {
787 tsleep(&sc->sc_todev, 0, "todr", 10);
788 }
789 return 0;
790 }
791 return -1;
792
793 }
794
795 /* poweroff and reboot */
796
797 void
798 cuda_poweroff(void)
799 {
800 struct cuda_softc *sc;
801 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF};
802
803 if (cuda0 == NULL)
804 return;
805 sc = cuda0->cookie;
806 sc->sc_polling = 1;
807 cuda0->poll(sc);
808 if (cuda0->send(sc, 1, 2, cmd) == 0)
809 while (1);
810 }
811
812 void
813 cuda_restart(void)
814 {
815 struct cuda_softc *sc;
816 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET};
817
818 if (cuda0 == NULL)
819 return;
820 sc = cuda0->cookie;
821 sc->sc_polling = 1;
822 cuda0->poll(sc);
823 if (cuda0->send(sc, 1, 2, cmd) == 0)
824 while (1);
825 }
826
827 /* ADB message handling */
828
829 static void
830 cuda_autopoll(void *cookie, int flag)
831 {
832 struct cuda_softc *sc = cookie;
833 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)};
834
835 if (cmd[2] == sc->sc_autopoll)
836 return;
837
838 sc->sc_autopoll = -1;
839 cuda_send(sc, 0, 3, cmd);
840 while(sc->sc_autopoll == -1) {
841 if (sc->sc_polling || cold) {
842 cuda_poll(sc);
843 } else
844 tsleep(&sc->sc_todev, 0, "autopoll", 100);
845 }
846 }
847
848 static int
849 cuda_adb_handler(void *cookie, int len, uint8_t *data)
850 {
851 struct cuda_softc *sc = cookie;
852
853 if (sc->sc_adb_handler != NULL) {
854 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1,
855 &data[1]);
856 return 0;
857 }
858 return -1;
859 }
860
861 static int
862 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data)
863 {
864 struct cuda_softc *sc = cookie;
865 int i, s = 0;
866 uint8_t packet[16];
867
868 /* construct an ADB command packet and send it */
869 packet[0] = CUDA_ADB;
870 packet[1] = command;
871 for (i = 0; i < len; i++)
872 packet[i + 2] = data[i];
873 if (poll || cold) {
874 s = splhigh();
875 cuda_poll(sc);
876 }
877 cuda_send(sc, poll, len + 2, packet);
878 if (poll || cold) {
879 cuda_poll(sc);
880 splx(s);
881 }
882 return 0;
883 }
884
885 static int
886 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *),
887 void *hcookie)
888 {
889 struct cuda_softc *sc = cookie;
890
891 /* register a callback for incoming ADB messages */
892 sc->sc_adb_handler = handler;
893 sc->sc_adb_cookie = hcookie;
894 return 0;
895 }
896
897 /* i2c message handling */
898
899 static int
900 cuda_i2c_acquire_bus(void *cookie, int flags)
901 {
902 struct cuda_softc *sc = cookie;
903
904 mutex_enter(&sc->sc_buslock);
905 return 0;
906 }
907
908 static void
909 cuda_i2c_release_bus(void *cookie, int flags)
910 {
911 struct cuda_softc *sc = cookie;
912
913 mutex_exit(&sc->sc_buslock);
914 }
915
916 static int
917 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send,
918 size_t send_len, void *_recv, size_t recv_len, int flags)
919 {
920 struct cuda_softc *sc = cookie;
921 const uint8_t *send = _send;
922 uint8_t *recv = _recv;
923 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC};
924
925 DPRINTF("cuda_i2c_exec(%02x)\n", addr);
926 command[2] = addr;
927
928 /* Copy command and output data bytes, if any, to buffer */
929 if (send_len > 0)
930 memcpy(&command[3], send, min((int)send_len, 12));
931 else if (I2C_OP_READ_P(op) && (recv_len == 0)) {
932 /*
933 * If no data bytes in either direction, it's a "quick"
934 * i2c operation. We don't know how to do a quick_read
935 * since that requires us to set the low bit of the
936 * address byte after it has been left-shifted.
937 */
938 sc->sc_error = 0;
939 return -1;
940 }
941
942 sc->sc_iic_done = 0;
943 cuda_send(sc, sc->sc_polling, send_len + 3, command);
944
945 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) {
946 if (sc->sc_polling || cold) {
947 cuda_poll(sc);
948 } else
949 tsleep(&sc->sc_todev, 0, "i2c", 1000);
950 }
951
952 if (sc->sc_error) {
953 sc->sc_error = 0;
954 return -1;
955 }
956
957 /* see if we're supposed to do a read */
958 if (recv_len > 0) {
959 sc->sc_iic_done = 0;
960 command[2] |= 1;
961 command[3] = 0;
962
963 /*
964 * XXX we need to do something to limit the size of the answer
965 * - apparently the chip keeps sending until we tell it to stop
966 */
967 sc->sc_i2c_read_len = recv_len;
968 DPRINTF("rcv_len: %d\n", recv_len);
969 cuda_send(sc, sc->sc_polling, 3, command);
970 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) {
971 if (sc->sc_polling || cold) {
972 cuda_poll(sc);
973 } else
974 tsleep(&sc->sc_todev, 0, "i2c", 1000);
975 }
976
977 if (sc->sc_error) {
978 printf("error trying to read\n");
979 sc->sc_error = 0;
980 return -1;
981 }
982 }
983
984 DPRINTF("received: %d\n", sc->sc_iic_done);
985 if ((sc->sc_iic_done > 3) && (recv_len > 0)) {
986 int rlen;
987
988 /* we got an answer */
989 rlen = min(sc->sc_iic_done - 3, recv_len);
990 memcpy(recv, &sc->sc_in[4], rlen);
991 #ifdef CUDA_DEBUG
992 {
993 int i;
994 printf("ret:");
995 for (i = 0; i < rlen; i++)
996 printf(" %02x", recv[i]);
997 printf("\n");
998 }
999 #endif
1000 return rlen;
1001 }
1002 return 0;
1003 }
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