sys/arch/macppc/dev/dbdma.c

   1 /*      $NetBSD: dbdma.c,v 1.8 2007/10/17 19:55:18 garbled Exp $        */
   2
   3 /*
   4  * Copyright 1991-1998 by Open Software Foundation, Inc.
   5  *              All Rights Reserved
   6  *
   7  * Permission to use, copy, modify, and distribute this software and
   8  * its documentation for any purpose and without fee is hereby granted,
   9  * provided that the above copyright notice appears in all copies and
  10  * that both the copyright notice and this permission notice appear in
  11  * supporting documentation.
  12  *
  13  * OSF DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
  14  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  15  * FOR A PARTICULAR PURPOSE.
  16  *
  17  * IN NO EVENT SHALL OSF BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
  18  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  19  * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
  20  * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
  21  * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  22  *
  23  */
  24
  25 #include <sys/cdefs.h>
  26 __KERNEL_RCSID(0, "$NetBSD: dbdma.c,v 1.8 2007/10/17 19:55:18 garbled Exp $");
  27
  28 #include <sys/param.h>
  29 #include <sys/malloc.h>
  30 #include <sys/systm.h>
  31
  32 #include <uvm/uvm_extern.h>
  33
  34 #include <machine/autoconf.h>
  35 #include <machine/pio.h>
  36 #include <macppc/dev/dbdma.h>
  37
  38 dbdma_command_t *dbdma_alloc_commands = NULL;
  39
  40 void
  41 dbdma_start(dbdma_regmap_t *dmap, dbdma_command_t *commands)
  42 {
  43         unsigned long addr = vtophys((vaddr_t)commands);
  44
  45         if (addr & 0xf)
  46                 panic("dbdma_start command structure not 16-byte aligned");
  47
  48         dmap->d_intselect = 0xff;  /* Endian magic - clear out interrupts */
  49         DBDMA_ST4_ENDIAN(&dmap->d_control,
  50                          DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE |
  51                                              DBDMA_CNTRL_DEAD   |
  52                                              DBDMA_CNTRL_WAKE   |
  53                                              DBDMA_CNTRL_FLUSH  |
  54                                              DBDMA_CNTRL_PAUSE  |
  55                                              DBDMA_CNTRL_RUN      )));
  56
  57         while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE)
  58                 ;
  59
  60         dmap->d_cmdptrhi = 0;   /* 64-bit not yet */
  61         DBDMA_ST4_ENDIAN(&dmap->d_cmdptrlo, addr);
  62
  63         DBDMA_ST4_ENDIAN(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN));
  64 }
  65
  66 void
  67 dbdma_stop(dbdma_regmap_t *dmap)
  68 {
  69         out32rb(&dmap->d_control, DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_RUN) |
  70                           DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));
  71
  72         while (in32rb(&dmap->d_status) &
  73                 (DBDMA_CNTRL_ACTIVE|DBDMA_CNTRL_FLUSH));
  74 }
  75
  76 void
  77 dbdma_flush(dbdma_regmap_t *dmap)
  78 {
  79         out32rb(&dmap->d_control, DBDMA_SET_CNTRL(DBDMA_CNTRL_FLUSH));
  80
  81         while (in32rb(&dmap->d_status) & (DBDMA_CNTRL_FLUSH));
  82 }
  83
  84 void
  85 dbdma_reset(dbdma_regmap_t *dmap)
  86 {
  87         out32rb(&dmap->d_control,
  88                          DBDMA_CLEAR_CNTRL( (DBDMA_CNTRL_ACTIVE |
  89                                              DBDMA_CNTRL_DEAD   |
  90                                              DBDMA_CNTRL_WAKE   |
  91                                              DBDMA_CNTRL_FLUSH  |
  92                                              DBDMA_CNTRL_PAUSE  |
  93                                              DBDMA_CNTRL_RUN      )));
  94
  95         while (in32rb(&dmap->d_status) & DBDMA_CNTRL_RUN);
  96 }
  97
  98 void
  99 dbdma_continue(dbdma_regmap_t *dmap)
 100 {
 101         out32rb(&dmap->d_control,
 102                 DBDMA_SET_CNTRL(DBDMA_CNTRL_RUN | DBDMA_CNTRL_WAKE) |
 103                 DBDMA_CLEAR_CNTRL(DBDMA_CNTRL_PAUSE | DBDMA_CNTRL_DEAD));
 104 }
 105
 106 void
 107 dbdma_pause(dbdma_regmap_t *dmap)
 108 {
 109         DBDMA_ST4_ENDIAN(&dmap->d_control,DBDMA_SET_CNTRL(DBDMA_CNTRL_PAUSE));
 110
 111         while (DBDMA_LD4_ENDIAN(&dmap->d_status) & DBDMA_CNTRL_ACTIVE)
 112                 ;
 113 }
 114
 115 dbdma_command_t *
 116 dbdma_alloc(int size)
 117 {
 118         u_int buf;
 119
 120         buf = (u_int)malloc(size + 0x0f, M_DEVBUF, M_WAITOK);
 121         buf = (buf + 0x0f) & ~0x0f;
 122
 123         return (dbdma_command_t *)buf;
 124 }