sys/arch/mips/include/pte.h

   1 /*      $NetBSD: pte.h,v 1.18 2007/10/17 19:55:37 garbled Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   9  * NASA Ames Research Center.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30  * POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 /*
  34  * Copyright 1996 The Board of Trustees of The Leland Stanford
  35  * Junior University. All Rights Reserved.
  36  *
  37  * Permission to use, copy, modify, and distribute this
  38  * software and its documentation for any purpose and without
  39  * fee is hereby granted, provided that the above copyright
  40  * notice appear in all copies.  Stanford University
  41  * makes no representations about the suitability of this
  42  * software for any purpose.  It is provided "as is" without
  43  * express or implied warranty.
  44  */
  45
  46 #ifndef  __MIPS_PTE_H__
  47 #define  __MIPS_PTE_H__
  48
  49 #include <mips/mips1_pte.h>
  50 #include <mips/mips3_pte.h>
  51
  52 #define PG_ASID 0x000000ff      /* Address space ID */
  53
  54 #ifndef _LOCORE
  55 #include <mips/cpu.h>
  56
  57 typedef union pt_entry {
  58         unsigned int     pt_entry;      /* for copying, etc. */
  59         struct mips1_pte pt_mips1_pte;  /* for getting to bits by name */
  60         struct mips3_pte pt_mips3_pte;
  61 } pt_entry_t;
  62
  63 /*
  64  * Macros/inline functions to hide PTE format differences.
  65  */
  66
  67 #define mips_pg_nv_bit()        (MIPS1_PG_NV)   /* same on mips1 and mips3 */
  68
  69
  70 int pmap_is_page_ro(pmap_t, vaddr_t, int);
  71
  72
  73 /* MIPS1-only */
  74 #if defined(MIPS1) && !defined(MIPS3_PLUS)
  75 #define mips_pg_v(entry)        ((entry) & MIPS1_PG_V)
  76 #define mips_pg_wired(entry)    ((entry) & MIPS1_PG_WIRED)
  77
  78 #define mips_pg_m_bit()         (MIPS1_PG_D)
  79 #define mips_pg_rw_bit()        (MIPS1_PG_RW)   /* no RW bits for mips1 */
  80 #define mips_pg_ro_bit()        (MIPS1_PG_RO)
  81 #define mips_pg_ropage_bit()    (MIPS1_PG_RO)   /* XXX not MIPS1_PG_ROPAGE? */
  82 #define mips_pg_rwpage_bit()    (MIPS1_PG_RWPAGE)
  83 #define mips_pg_rwncpage_bit()  (MIPS1_PG_RWNCPAGE)
  84 #define mips_pg_cwpage_bit()    (MIPS1_PG_CWPAGE)
  85 #define mips_pg_cwncpage_bit()  (MIPS1_PG_CWNCPAGE)
  86 #define mips_pg_global_bit()    (MIPS1_PG_G)
  87 #define mips_pg_wired_bit()     (MIPS1_PG_WIRED)
  88
  89 #define PTE_TO_PADDR(pte)       MIPS1_PTE_TO_PADDR((pte))
  90 #define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va))
  91
  92 #define mips_tlbpfn_to_paddr(x)         mips1_tlbpfn_to_paddr((vaddr_t)(x))
  93 #define mips_paddr_to_tlbpfn(x)         mips1_paddr_to_tlbpfn((x))
  94 #endif /* mips1 */
  95
  96
  97 /* MIPS3 (or greater) only */
  98 #if !defined(MIPS1) && defined(MIPS3_PLUS)
  99 #define mips_pg_v(entry)        ((entry) & MIPS3_PG_V)
 100 #define mips_pg_wired(entry)    ((entry) & MIPS3_PG_WIRED)
 101
 102 #define mips_pg_m_bit()         (MIPS3_PG_D)
 103 #define mips_pg_rw_bit()        (MIPS3_PG_D)
 104 #define mips_pg_ro_bit()        (MIPS3_PG_RO)
 105 #define mips_pg_ropage_bit()    (MIPS3_PG_ROPAGE)
 106 #define mips_pg_rwpage_bit()    (MIPS3_PG_RWPAGE)
 107 #define mips_pg_rwncpage_bit()  (MIPS3_PG_RWNCPAGE)
 108 #define mips_pg_cwpage_bit()    (MIPS3_PG_CWPAGE)
 109 #define mips_pg_cwncpage_bit()  (MIPS3_PG_CWNCPAGE)
 110 #define mips_pg_global_bit()    (MIPS3_PG_G)
 111 #define mips_pg_wired_bit()     (MIPS3_PG_WIRED)
 112
 113 #define PTE_TO_PADDR(pte)       MIPS3_PTE_TO_PADDR((pte))
 114 #define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va))
 115
 116 #define mips_tlbpfn_to_paddr(x)         mips3_tlbpfn_to_paddr((vaddr_t)(x))
 117 #define mips_paddr_to_tlbpfn(x)         mips3_paddr_to_tlbpfn((x))
 118 #endif /* mips3 */
 119
 120 /* MIPS1 and MIPS3 (or greater) */
 121 #if defined(MIPS1) && defined(MIPS3_PLUS)
 122
 123 static __inline int
 124     mips_pg_v(unsigned int entry),
 125     mips_pg_wired(unsigned int entry),
 126     PAGE_IS_RDONLY(unsigned int pte, vaddr_t va);
 127
 128 static __inline unsigned int
 129     mips_pg_wired_bit(void), mips_pg_m_bit(void),
 130     mips_pg_ro_bit(void), mips_pg_rw_bit(void),
 131     mips_pg_ropage_bit(void),
 132     mips_pg_cwpage_bit(void),
 133     mips_pg_rwpage_bit(void),
 134     mips_pg_global_bit(void);
 135 static __inline paddr_t PTE_TO_PADDR(unsigned int pte);
 136
 137 static __inline paddr_t mips_tlbpfn_to_paddr(unsigned int pfn);
 138 static __inline unsigned int mips_paddr_to_tlbpfn(paddr_t pa);
 139
 140
 141 static __inline int
 142 mips_pg_v(entry)
 143         unsigned int entry;
 144 {
 145         if (MIPS_HAS_R4K_MMU)
 146                 return (entry & MIPS3_PG_V);
 147         return (entry & MIPS1_PG_V);
 148 }
 149
 150 static __inline int
 151 mips_pg_wired(entry)
 152         unsigned int entry;
 153 {
 154         if (MIPS_HAS_R4K_MMU)
 155                 return (entry & MIPS3_PG_WIRED);
 156         return (entry & MIPS1_PG_WIRED);
 157 }
 158
 159 static __inline unsigned int
 160 mips_pg_m_bit(void)
 161 {
 162         if (MIPS_HAS_R4K_MMU)
 163                 return (MIPS3_PG_D);
 164         return (MIPS1_PG_D);
 165 }
 166
 167 static __inline unsigned int
 168 mips_pg_ro_bit(void)
 169 {
 170         if (MIPS_HAS_R4K_MMU)
 171                 return (MIPS3_PG_RO);
 172         return (MIPS1_PG_RO);
 173 }
 174
 175 static __inline unsigned int
 176 mips_pg_rw_bit(void)
 177 {
 178         if (MIPS_HAS_R4K_MMU)
 179                 return (MIPS3_PG_D);
 180         return (MIPS1_PG_RW);
 181 }
 182
 183 static __inline unsigned int
 184 mips_pg_ropage_bit(void)
 185 {
 186         if (MIPS_HAS_R4K_MMU)
 187                 return (MIPS3_PG_ROPAGE);
 188         return (MIPS1_PG_RO);
 189 }
 190
 191 static __inline unsigned int
 192 mips_pg_rwpage_bit(void)
 193 {
 194         if (MIPS_HAS_R4K_MMU)
 195                 return (MIPS3_PG_RWPAGE);
 196         return (MIPS1_PG_RWPAGE);
 197 }
 198
 199 static __inline unsigned int
 200 mips_pg_cwpage_bit(void)
 201 {
 202         if (MIPS_HAS_R4K_MMU)
 203                 return (MIPS3_PG_CWPAGE);
 204         return (MIPS1_PG_CWPAGE);
 205 }
 206
 207
 208 static __inline unsigned int
 209 mips_pg_global_bit(void)
 210 {
 211         if (MIPS_HAS_R4K_MMU)
 212                 return (MIPS3_PG_G);
 213         return (MIPS1_PG_G);
 214 }
 215
 216 static __inline unsigned int
 217 mips_pg_wired_bit(void)
 218 {
 219         if (MIPS_HAS_R4K_MMU)
 220                 return (MIPS3_PG_WIRED);
 221         return (MIPS1_PG_WIRED);
 222 }
 223
 224 static __inline paddr_t
 225 PTE_TO_PADDR(pte)
 226         unsigned int pte;
 227 {
 228         if (MIPS_HAS_R4K_MMU)
 229                 return (MIPS3_PTE_TO_PADDR(pte));
 230         return (MIPS1_PTE_TO_PADDR(pte));
 231 }
 232
 233 static __inline int
 234 PAGE_IS_RDONLY(pte, va)
 235         unsigned int pte;
 236         vaddr_t va;
 237 {
 238         if (MIPS_HAS_R4K_MMU)
 239                 return (MIPS3_PAGE_IS_RDONLY(pte, va));
 240         return (MIPS1_PAGE_IS_RDONLY(pte, va));
 241 }
 242
 243 static __inline paddr_t
 244 mips_tlbpfn_to_paddr(pfn)
 245         unsigned int pfn;
 246 {
 247         if (MIPS_HAS_R4K_MMU)
 248                 return (mips3_tlbpfn_to_paddr(pfn));
 249         return (mips1_tlbpfn_to_paddr(pfn));
 250 }
 251
 252 static __inline unsigned int
 253 mips_paddr_to_tlbpfn(pa)
 254         paddr_t pa;
 255 {
 256         if (MIPS_HAS_R4K_MMU)
 257                 return (mips3_paddr_to_tlbpfn(pa));
 258         return (mips1_paddr_to_tlbpfn(pa));
 259 }
 260 #endif
 261
 262 #endif /* ! _LOCORE */
 263
 264 #if defined(_KERNEL) && !defined(_LOCORE)
 265 /*
 266  * Kernel virtual address to page table entry and visa versa.
 267  */
 268 #define kvtopte(va) \
 269         (Sysmap + (((vaddr_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT))
 270 #define ptetokv(pte) \
 271         ((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
 272
 273 extern  pt_entry_t *Sysmap;             /* kernel pte table */
 274 extern  u_int Sysmapsize;               /* number of pte's in Sysmap */
 275 #endif  /* defined(_KERNEL) && !defined(_LOCORE) */
 276 #endif /* __MIPS_PTE_H__ */