sys/arch/mips/include/r3900regs.h

   1 /*      $NetBSD: r3900regs.h,v 1.6 2002/03/05 16:02:48 simonb Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  *      [address space]
  34  *      kseg2           0xc0000000 - 0xfeffffff
  35  *      reserved        0xff000000 - 0xfffeffff
  36  *      kseg2           0xffff0000 - 0xffffffff
  37  * -> vmparam.h VM_MAX_KERNEL_ADDRESS
  38  */
  39
  40 /*
  41  *      [cause register]
  42  */
  43 #define R3900_CR_EXC_CODE       MIPS3_CR_EXC_CODE /* five bits */
  44 #undef MIPS1_CR_EXC_CODE
  45 #define MIPS1_CR_EXC_CODE       R3900_CR_EXC_CODE
  46
  47 /*
  48  *      [status register]
  49  *      R3900 don't have PE, CM, PZ, SwC and IsC.
  50  */
  51 #define R3900_SR_NMI            0x00100000 /* r3k PE position */
  52 #if 0
  53 #undef MIPS1_PARITY_ERR
  54 #undef MIPS1_CACHE_MISS
  55 #undef MIPS1_PARITY_ZERO
  56 #undef MIPS1_SWAP_CACHES
  57 #undef MIPS1_ISOL_CACHES
  58 #endif
  59
  60 /*
  61  *      [context register]
  62  * - no changes.
  63  */
  64
  65
  66 /*
  67  *      TX3900 Coprocessor 0 registers
  68  */
  69 #define R3900_COP_0_CONFIG      $3
  70 #define R3900_COP_0_DEBUG       $16
  71 #define R3900_COP_0_DEPC        $17
  72
  73 #define R3920_COP_0_PAGEMASK    $5
  74 #define R3920_COP_0_WIRED       $6
  75 #define R3920_COP_0_CACHE       $7
  76 #define R3920_COP_0_TAG_LO      $20
  77
  78 /*
  79  *      TLB entry
  80  *      3912 ... TLB entry is 64bits wide and R3000A compatible
  81  *      3922 ... TLB entry is 96bits wide
  82  */
  83
  84 /*
  85  *      Config register (R3900 specific)
  86  */
  87 #define R3900_CONFIG_ICS_SHIFT          19
  88 #define R3900_CONFIG_ICS_MASK           0x00380000
  89 #define R3900_CONFIG_ICS_1KB            0x00000000
  90 #define R3900_CONFIG_ICS_2KB            0x00080000
  91 #define R3900_CONFIG_ICS_4KB            0x00100000
  92 #define R3900_CONFIG_ICS_8KB            0x00180000
  93 #define R3900_CONFIG_ICS_16KB           0x00200000
  94
  95 #define R3900_CONFIG_DCS_SHIFT          16
  96 #define R3900_CONFIG_DCS_1KB            0x00000000
  97 #define R3900_CONFIG_DCS_2KB            0x00010000
  98 #define R3900_CONFIG_DCS_4KB            0x00020000
  99 #define R3900_CONFIG_DCS_8KB            0x00030000
 100 #define R3900_CONFIG_DCS_16KB           0x00040000
 101
 102 #define R3900_CONFIG_DCS_MASK           0x00070000
 103 #define R3900_CONFIG_CWFON              0x00004000
 104 #define R3900_CONFIG_WBON               0x00002000
 105 #define R3900_CONFIG_RF_SHIFT           10
 106 #define R3900_CONFIG_RF_MASK            0x00000c00
 107 #define R3900_CONFIG_DOZE               0x00000200
 108 #define R3900_CONFIG_HALT               0x00000100
 109 #define R3900_CONFIG_LOCK               0x00000080
 110 #define R3900_CONFIG_ICE                0x00000020
 111 #define R3900_CONFIG_DCE                0x00000010
 112 #define R3900_CONFIG_IRSIZE_SHIFT       2
 113 #define R3900_CONFIG_IRSIZE_MASK        0x0000000c
 114 #define R3900_CONFIG_DRSIZE_SHIFT       0
 115 #define R3900_CONFIG_DRSIZE_MASK        0x00000003
 116
 117 /*
 118  *      CACHE
 119  */
 120 /* Cache size (limit) */
 121 /* R3900/R3920 */
 122 #define R3900_C_SIZE_MIN                1024
 123 #define R3900_C_SIZE_MAX                8192
 124 /* Cache line size */
 125 /* R3900 */
 126 #define R3900_C_LSIZE_I                 16
 127 #define R3900_C_LSIZE_D                 4
 128 /* R3920 */
 129 #define R3920_C_LSIZE_I                 16
 130 #define R3920_C_LSIZE_D                 16
 131 /* Cache operation */
 132 /* R3900 */
 133 #define R3900_C_IINV_I                  0x00
 134 #define R3900_C_IWBINV_D                0x01
 135 #define R3900_C_ILRUC_I                 0x04
 136 #define R3900_C_ILRUC_D                 0x05
 137 #define R3900_C_ILCKC_D                 0x09 /* R3900 only */
 138 #define R3900_C_HINV_D                  0x11
 139 /* R3920 */
 140 #define R3920_C_IINV_I                  0x00
 141 #define R3920_C_IWBINV_D                0x01
 142 #define R3920_C_ILRUC_I                 0x04
 143 #define R3920_C_ILRUC_D                 0x05
 144 #define R3920_C_ILDTAG_I                0x0c /* R3920 only */
 145 #define R3920_C_ILDTAG_D                0x0d /* R3920 only */
 146 #define R3920_C_HINV_I                  0x10 /* R3920 only */
 147 #define R3920_C_HINV_D                  0x11
 148 #define R3920_C_HWBINV_D                0x14 /* R3920 only */
 149 #define R3920_C_HWB_D                   0x18 /* R3920 only */
 150 #define R3920_C_ISTTAG_I                0x1c /* R3920 only */
 151 #define R3920_C_ISTTAG_D                0x1d /* R3920 only */