sys/arch/mips/sibyte/include/sb1250_dma.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  DMA definitions                          File: sb1250_dma.h
   5     *
   6     *  This module contains constants and macros useful for
   7     *  programming the SB1250's DMA controllers, both the data mover
   8     *  and the Ethernet DMA.
   9     *
  10     *  SB1250 specification level:  User's manual 10/21/02
  11     *  BCM1280 specification level: User's manual 11/24/03
  12     *
  13     *********************************************************************
  14     *
  15     *  Copyright 2000,2001,2002,2003,2004
  16     *  Broadcom Corporation. All rights reserved.
  17     *
  18     *  This software is furnished under license and may be used and
  19     *  copied only in accordance with the following terms and
  20     *  conditions.  Subject to these conditions, you may download,
  21     *  copy, install, use, modify and distribute modified or unmodified
  22     *  copies of this software in source and/or binary form.  No title
  23     *  or ownership is transferred hereby.
  24     *
  25     *  1) Any source code used, modified or distributed must reproduce
  26     *     and retain this copyright notice and list of conditions
  27     *     as they appear in the source file.
  28     *
  29     *  2) No right is granted to use any trade name, trademark, or
  30     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  31     *     name may not be used to endorse or promote products derived
  32     *     from this software without the prior written permission of
  33     *     Broadcom Corporation.
  34     *
  35     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  36     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  37     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  39     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  40     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  41     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  42     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  43     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  44     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  45     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  46     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  47     *     THE POSSIBILITY OF SUCH DAMAGE.
  48     ********************************************************************* */
  49
  50
  51 #ifndef _SB1250_DMA_H
  52 #define _SB1250_DMA_H
  53
  54
  55 #include "sb1250_defs.h"
  56
  57 /*  *********************************************************************
  58     *  DMA Registers
  59     ********************************************************************* */
  60
  61 /*
  62  * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
  63  * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
  64  * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
  65  * Registers: DMA_CONFIG0_SER_x_RX
  66  * Registers: DMA_CONFIG0_SER_x_TX
  67  */
  68
  69
  70 #define M_DMA_DROP                  _SB_MAKEMASK1(0)
  71
  72 #define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
  73 #define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
  74
  75 #define S_DMA_DESC_TYPE             _SB_MAKE64(1)
  76 #define M_DMA_DESC_TYPE             _SB_MAKEMASK(2,S_DMA_DESC_TYPE)
  77 #define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
  78 #define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
  79
  80 #define K_DMA_DESC_TYPE_RING_AL         0
  81 #define K_DMA_DESC_TYPE_CHAIN_AL        1
  82
  83 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
  84 #define K_DMA_DESC_TYPE_RING_UAL_WI     2
  85 #define K_DMA_DESC_TYPE_RING_UAL_RMW    3
  86 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
  87
  88 #define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
  89 #define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
  90 #define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
  91 #define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
  92 #define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
  93
  94 #define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
  95 #define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
  96 #define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
  97 #define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
  98
  99 #define S_DMA_RINGSZ                _SB_MAKE64(16)
 100 #define M_DMA_RINGSZ                _SB_MAKEMASK(16,S_DMA_RINGSZ)
 101 #define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x,S_DMA_RINGSZ)
 102 #define G_DMA_RINGSZ(x)             _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
 103
 104 #define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
 105 #define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
 106 #define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
 107 #define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
 108
 109 #define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
 110 #define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
 111 #define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
 112 #define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
 113
 114 /*
 115  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
 116  * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
 117  * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
 118  * Registers: DMA_CONFIG1_SER_x_RX
 119  * Registers: DMA_CONFIG1_SER_x_TX
 120  */
 121
 122 #define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
 123 #define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
 124 #define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
 125 #define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
 126 #define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
 127 #define M_DMA_L2CA                  _SB_MAKEMASK1(5)
 128
 129 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 130 #define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
 131 #define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
 132 #define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
 133 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 134
 135 #define M_DMA_MBZ1                  _SB_MAKEMASK(6,15)
 136
 137 #define S_DMA_HDR_SIZE              _SB_MAKE64(21)
 138 #define M_DMA_HDR_SIZE              _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
 139 #define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
 140 #define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
 141
 142 #define M_DMA_MBZ2                  _SB_MAKEMASK(5,32)
 143
 144 #define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
 145 #define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
 146 #define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
 147 #define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
 148
 149 #define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
 150 #define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
 151 #define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
 152 #define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
 153
 154 /*
 155  * Ethernet and Serial DMA Descriptor base address (Table 7-6)
 156  */
 157
 158 #define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4,0)
 159
 160
 161 /*
 162  * ASIC Mode Base Address (Table 7-7)
 163  */
 164
 165 #define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20,0)
 166
 167 /*
 168  * DMA Descriptor Count Registers (Table 7-8)
 169  */
 170
 171 /* No bitfields */
 172
 173
 174 /*
 175  * Current Descriptor Address Register (Table 7-11)
 176  */
 177
 178 #define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
 179 #define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
 180 #define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
 181 #define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
 182
 183 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 184 #define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
 185 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 186
 187 /*
 188  * Receive Packet Drop Registers
 189  */
 190 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 191 #define S_DMA_OODLOST_RX           _SB_MAKE64(0)
 192 #define M_DMA_OODLOST_RX           _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
 193 #define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
 194
 195 #define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
 196 #define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
 197 #define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
 198 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 199
 200 /*  *********************************************************************
 201     *  DMA Descriptors
 202     ********************************************************************* */
 203
 204 /*
 205  * Descriptor doubleword "A"  (Table 7-12)
 206  */
 207
 208 #define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
 209 #define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
 210 #define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET)
 211 #define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET)
 212
 213 /* Note: Don't shift the address over, just mask it with the mask below */
 214 #define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
 215 #define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
 216
 217 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
 218
 219 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 220 #define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
 221 #define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
 222 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 223
 224 #define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
 225 #define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
 226 #define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
 227 #define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
 228
 229 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 230 #define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
 231 #define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
 232 #define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
 233 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 234
 235 #define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
 236 #define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
 237
 238 #define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
 239 #define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
 240 #define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
 241 #define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
 242
 243 /*
 244  * Descriptor doubleword "B"  (Table 7-13)
 245  */
 246
 247
 248 #define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
 249 #define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
 250 #define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
 251 #define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
 252
 253 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 254 #define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
 255 #define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
 256 #define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
 257 #define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
 258 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 259
 260 #define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
 261
 262 /* Note: Don't shift the address over, just mask it with the mask below */
 263 #define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
 264 #define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
 265
 266 #define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
 267 #define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
 268 #define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
 269 #define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
 270
 271 #define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
 272
 273 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 274 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
 275 #define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
 276 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
 277 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
 278 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 279
 280 #define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
 281 #define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
 282 #define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
 283 #define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
 284
 285 /*
 286  * from pass2 some bits in dscr_b are also used for rx status
 287  */
 288 #define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
 289 #define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS)
 290 #define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
 291 #define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
 292
 293 /*
 294  * Ethernet Descriptor Status Bits (Table 7-15)
 295  */
 296
 297 #define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
 298 #define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
 299
 300 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 301 /* Note: This bit is in the DSCR_B options field */
 302 #define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
 303 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 304
 305 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 306 /* Note: These bits are in the DSCR_B options field */
 307 #define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
 308 #define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
 309 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 310
 311 #define S_DMA_ETHRX_RXCH            53
 312 #define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
 313 #define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
 314 #define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
 315
 316 #define S_DMA_ETHRX_PKTTYPE         55
 317 #define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
 318 #define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
 319 #define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
 320
 321 #define K_DMA_ETHRX_PKTTYPE_IPV4    0
 322 #define K_DMA_ETHRX_PKTTYPE_ARPV4   1
 323 #define K_DMA_ETHRX_PKTTYPE_802     2
 324 #define K_DMA_ETHRX_PKTTYPE_OTHER   3
 325 #define K_DMA_ETHRX_PKTTYPE_USER0   4
 326 #define K_DMA_ETHRX_PKTTYPE_USER1   5
 327 #define K_DMA_ETHRX_PKTTYPE_USER2   6
 328 #define K_DMA_ETHRX_PKTTYPE_USER3   7
 329
 330 #define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
 331 #define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
 332 #define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
 333 #define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
 334 #define M_DMA_ETHRX_BAD             _SB_MAKEMASK1(62)
 335 #define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
 336
 337 /*
 338  * Ethernet Transmit Status Bits (Table 7-16)
 339  */
 340
 341 #define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
 342
 343 /*
 344  * Ethernet Transmit Options (Table 7-17)
 345  */
 346
 347 #define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
 348 #define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
 349 #define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
 350 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
 351 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
 352 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
 353 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
 354 #define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
 355 #define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
 356 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
 357 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
 358 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
 359 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
 360 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
 361 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
 362 #define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
 363
 364 /*
 365  * Serial Receive Options (Table 7-18)
 366  */
 367 #define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
 368 #define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
 369 #define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
 370 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
 371 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
 372 #define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
 373 #define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
 374 #define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
 375
 376 /*
 377  * Serial Transmit Status Bits (Table 7-20)
 378  */
 379
 380 #define M_DMA_SERTX_FLAG            _SB_MAKEMASK1(63)
 381
 382 /*
 383  * Serial Transmit Options (Table 7-21)
 384  */
 385
 386 #define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
 387 #define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
 388 #define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
 389 #define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
 390
 391
 392 /*  *********************************************************************
 393     *  Data Mover Registers
 394     ********************************************************************* */
 395
 396 /*
 397  * Data Mover Descriptor Base Address Register (Table 7-22)
 398  * Register: DM_DSCR_BASE_0
 399  * Register: DM_DSCR_BASE_1
 400  * Register: DM_DSCR_BASE_2
 401  * Register: DM_DSCR_BASE_3
 402  */
 403
 404 #define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4,0)
 405
 406 /*  Note: Just mask the base address and then OR it in. */
 407 #define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
 408 #define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
 409
 410 #define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
 411 #define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
 412 #define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
 413 #define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
 414
 415 #define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
 416 #define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
 417 #define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
 418 #define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
 419
 420 #define K_DM_DSCR_BASE_PRIORITY_1   0
 421 #define K_DM_DSCR_BASE_PRIORITY_2   1
 422 #define K_DM_DSCR_BASE_PRIORITY_4   2
 423 #define K_DM_DSCR_BASE_PRIORITY_8   3
 424 #define K_DM_DSCR_BASE_PRIORITY_16  4
 425
 426 #define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
 427 #define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
 428 #define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)   /* write register */
 429 #define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)   /* read register */
 430 #define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
 431 #define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
 432
 433 /*
 434  * Data Mover Descriptor Count Register (Table 7-25)
 435  */
 436
 437 /* no bitfields */
 438
 439 /*
 440  * Data Mover Current Descriptor Address (Table 7-24)
 441  * Register: DM_CUR_DSCR_ADDR_0
 442  * Register: DM_CUR_DSCR_ADDR_1
 443  * Register: DM_CUR_DSCR_ADDR_2
 444  * Register: DM_CUR_DSCR_ADDR_3
 445  */
 446
 447 #define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
 448 #define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
 449
 450 #define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
 451 #define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
 452 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
 453 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
 454                                      M_DM_CUR_DSCR_DSCR_COUNT)
 455
 456
 457 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 458 /*
 459  * Data Mover Channel Partial Result Registers
 460  * Register: DM_PARTIAL_0
 461  * Register: DM_PARTIAL_1
 462  * Register: DM_PARTIAL_2
 463  * Register: DM_PARTIAL_3
 464  */
 465 #define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
 466 #define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL)
 467 #define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL)
 468 #define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\
 469                                        M_DM_PARTIAL_CRC_PARTIAL)
 470
 471 #define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
 472 #define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL)
 473 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL)
 474 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\
 475                                        M_DM_PARTIAL_TCPCS_PARTIAL)
 476
 477 #define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
 478 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 479
 480
 481 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 482 /*
 483  * Data Mover CRC Definition Registers
 484  * Register: CRC_DEF_0
 485  * Register: CRC_DEF_1
 486  */
 487 #define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
 488 #define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT)
 489 #define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT)
 490 #define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\
 491                                        M_CRC_DEF_CRC_INIT)
 492
 493 #define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
 494 #define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY)
 495 #define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
 496 #define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
 497                                        M_CRC_DEF_CRC_POLY)
 498 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 499
 500
 501 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 502 /*
 503  * Data Mover CRC/Checksum Definition Registers
 504  * Register: CTCP_DEF_0
 505  * Register: CTCP_DEF_1
 506  */
 507 #define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
 508 #define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR)
 509 #define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR)
 510 #define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\
 511                                        M_CTCP_DEF_CRC_TXOR)
 512
 513 #define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
 514 #define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT)
 515 #define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT)
 516 #define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\
 517                                        M_CTCP_DEF_TCPCS_INIT)
 518
 519 #define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
 520 #define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH)
 521 #define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH)
 522 #define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\
 523                                        M_CTCP_DEF_CRC_WIDTH)
 524
 525 #define K_CTCP_DEF_CRC_WIDTH_4        0
 526 #define K_CTCP_DEF_CRC_WIDTH_2        1
 527 #define K_CTCP_DEF_CRC_WIDTH_1        2
 528
 529 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
 530 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 531
 532
 533 /*
 534  * Data Mover Descriptor Doubleword "A"  (Table 7-26)
 535  */
 536
 537 #define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
 538 #define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
 539
 540 #define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
 541 #define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
 542 #define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
 543 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
 544 #define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
 545 #endif /* up to 1250 PASS1 */
 546
 547 #define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
 548 #define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
 549 #define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
 550 #define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
 551
 552 #define K_DM_DSCRA_DIR_DEST_INCR    0
 553 #define K_DM_DSCRA_DIR_DEST_DECR    1
 554 #define K_DM_DSCRA_DIR_DEST_CONST   2
 555
 556 #define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
 557 #define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
 558 #define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
 559
 560 #define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
 561 #define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
 562 #define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
 563 #define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
 564
 565 #define K_DM_DSCRA_DIR_SRC_INCR     0
 566 #define K_DM_DSCRA_DIR_SRC_DECR     1
 567 #define K_DM_DSCRA_DIR_SRC_CONST    2
 568
 569 #define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
 570 #define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
 571 #define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
 572
 573
 574 #define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
 575 #define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
 576 #define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
 577 #define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
 578
 579 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 580 #define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
 581 #define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
 582 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 583
 584 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 585 #define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
 586 #define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
 587 #define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
 588 #define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
 589 #define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
 590 #define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
 591 #define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
 592 #define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
 593 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 594
 595 #define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3,61)
 596
 597 /*
 598  * Data Mover Descriptor Doubleword "B"  (Table 7-25)
 599  */
 600
 601 #define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
 602 #define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
 603
 604 #define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
 605 #define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
 606 #define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
 607 #define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)
 608
 609
 610 #endif