1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * LDT constants File: sb1250_ldt.h
6 * This module contains constants and macros to describe
7 * the LDT interface on the SB1250.
9 * SB1250 specification level: User's manual 1/02/02
11 *********************************************************************
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
16 * This software is furnished under license and may be used and
17 * copied only in accordance with the following terms and
18 * conditions. Subject to these conditions, you may download,
19 * copy, install, use, modify and distribute modified or unmodified
20 * copies of this software in source and/or binary form. No title
21 * or ownership is transferred hereby.
23 * 1) Any source code used, modified or distributed must reproduce
24 * and retain this copyright notice and list of conditions
25 * as they appear in the source file.
27 * 2) No right is granted to use any trade name, trademark, or
28 * logo of Broadcom Corporation. The "Broadcom Corporation"
29 * name may not be used to endorse or promote products derived
30 * from this software without the prior written permission of
31 * Broadcom Corporation.
33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
45 * THE POSSIBILITY OF SUCH DAMAGE.
46 ********************************************************************* */
52 #include "sb1250_defs.h"
54 #define K_LDT_VENDOR_SIBYTE 0x166D
55 #define K_LDT_DEVICE_SB1250 0x0002
58 * LDT Interface Type 1 (bridge) configuration header
61 #define R_LDT_TYPE1_DEVICEID 0x0000
62 #define R_LDT_TYPE1_CMDSTATUS 0x0004
63 #define R_LDT_TYPE1_CLASSREV 0x0008
64 #define R_LDT_TYPE1_DEVHDR 0x000C
65 #define R_LDT_TYPE1_BAR0 0x0010 /* not used */
66 #define R_LDT_TYPE1_BAR1 0x0014 /* not used */
68 #define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
69 #define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
70 #define R_LDT_TYPE1_MEMLIMIT 0x0020
71 #define R_LDT_TYPE1_PREFETCH 0x0024
72 #define R_LDT_TYPE1_PREF_BASE 0x0028
73 #define R_LDT_TYPE1_PREF_LIMIT 0x002C
74 #define R_LDT_TYPE1_IOLIMIT 0x0030
75 #define R_LDT_TYPE1_CAPPTR 0x0034
76 #define R_LDT_TYPE1_ROMADDR 0x0038
77 #define R_LDT_TYPE1_BRCTL 0x003C
78 #define R_LDT_TYPE1_CMD 0x0040
79 #define R_LDT_TYPE1_LINKCTRL 0x0044
80 #define R_LDT_TYPE1_LINKFREQ 0x0048
81 #define R_LDT_TYPE1_RESERVED1 0x004C
82 #define R_LDT_TYPE1_SRICMD 0x0050
83 #define R_LDT_TYPE1_SRITXNUM 0x0054
84 #define R_LDT_TYPE1_SRIRXNUM 0x0058
85 #define R_LDT_TYPE1_ERRSTATUS 0x0068
86 #define R_LDT_TYPE1_SRICTRL 0x006C
87 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
88 #define R_LDT_TYPE1_ADDSTATUS 0x0070
89 #endif /* 1250 PASS2 || 112x PASS1 */
90 #define R_LDT_TYPE1_TXBUFCNT 0x00C8
91 #define R_LDT_TYPE1_EXPCRC 0x00DC
92 #define R_LDT_TYPE1_RXCRC 0x00F0
96 * LDT Device ID register
99 #define S_LDT_DEVICEID_VENDOR 0
100 #define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
101 #define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
102 #define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)
104 #define S_LDT_DEVICEID_DEVICEID 16
105 #define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
106 #define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
107 #define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)
111 * LDT Command Register (Table 8-13)
114 #define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
115 #define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
116 #define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
117 #define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
118 #define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
119 #define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
120 #define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
121 #define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
122 #define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
123 #define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
126 * LDT class and revision registers
129 #define S_LDT_CLASSREV_REV 0
130 #define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
131 #define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
132 #define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)
134 #define S_LDT_CLASSREV_CLASS 8
135 #define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
136 #define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
137 #define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)
139 #define K_LDT_REV 0x01
140 #define K_LDT_CLASS 0x060000
143 * Device Header (offset 0x0C)
146 #define S_LDT_DEVHDR_CLINESZ 0
147 #define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
148 #define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
149 #define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)
151 #define S_LDT_DEVHDR_LATTMR 8
152 #define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
153 #define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
154 #define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)
156 #define S_LDT_DEVHDR_HDRTYPE 16
157 #define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
158 #define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
159 #define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)
161 #define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
163 #define S_LDT_DEVHDR_BIST 24
164 #define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
165 #define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
166 #define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)
171 * LDT Status Register (Table 8-14). Note that these constants
172 * assume you've read the command and status register
173 * together (32-bit read at offset 0x04)
175 * These bits also apply to the secondary status
176 * register (Table 8-15), offset 0x1C
179 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
180 #define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3)
181 #endif /* 1250 PASS2 || 112x PASS1 */
182 #define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
183 #define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
184 #define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
185 #define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
186 #define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
188 #define S_LDT_STATUS_DEVSELTIMING 25
189 #define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
190 #define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
191 #define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)
193 #define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
194 #define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
195 #define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
196 #define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
197 #define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
200 * Bridge Control Register (Table 8-16). Note that these
201 * constants assume you've read the register as a 32-bit
205 #define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
206 #define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
207 #define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
208 #define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
209 #define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
210 #define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
211 #define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
212 #define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
213 #define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
214 #define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
215 #define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
218 * LDT Command Register (Table 8-17). Note that these constants
219 * assume you've read the command and status register together
220 * 32-bit read at offset 0x40
223 #define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
224 #define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
226 #define S_LDT_CMD_CAPTYPE 29
227 #define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)
228 #define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE)
229 #define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE)
232 * LDT link control register (Table 8-18), and (Table 8-19)
235 #define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
236 #define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
237 #define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
238 #define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
239 #define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
240 #define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
241 #define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
243 #define S_LDT_LINKCTRL_CRCERR 8
244 #define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR)
245 #define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR)
246 #define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR)
248 #define S_LDT_LINKCTRL_MAXIN 16
249 #define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN)
250 #define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN)
251 #define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN)
253 #define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
255 #define S_LDT_LINKCTRL_MAXOUT 20
256 #define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT)
257 #define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT)
258 #define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT)
260 #define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
262 #define S_LDT_LINKCTRL_WIDTHIN 24
263 #define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN)
264 #define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN)
265 #define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN)
267 #define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
269 #define S_LDT_LINKCTRL_WIDTHOUT 28
270 #define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT)
271 #define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT)
272 #define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT)
274 #define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
277 * LDT Link frequency register (Table 8-20) offset 0x48
280 #define S_LDT_LINKFREQ_FREQ 8
281 #define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ)
282 #define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ)
283 #define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ)
285 #define K_LDT_LINKFREQ_200MHZ 0
286 #define K_LDT_LINKFREQ_300MHZ 1
287 #define K_LDT_LINKFREQ_400MHZ 2
288 #define K_LDT_LINKFREQ_500MHZ 3
289 #define K_LDT_LINKFREQ_600MHZ 4
290 #define K_LDT_LINKFREQ_800MHZ 5
291 #define K_LDT_LINKFREQ_1000MHZ 6
294 * LDT SRI Command Register (Table 8-21). Note that these constants
295 * assume you've read the command and status register together
296 * 32-bit read at offset 0x50
299 #define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
300 #define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
301 #define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
302 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
303 #define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */
304 #endif /* up to 1250 PASS1 */
305 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
306 #define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19)
307 #define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26)
308 #endif /* 1250 PASS2 || 112x PASS1 */
311 #define S_LDT_SRICMD_RXMARGIN 20
312 #define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN)
313 #define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN)
314 #define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN)
316 #define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
318 #define S_LDT_SRICMD_TXINITIALOFFSET 28
319 #define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET)
320 #define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET)
321 #define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET)
323 #define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
326 * LDT Error control and status register (Table 8-22) (Table 8-23)
329 #define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
330 #define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
331 #define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
332 #define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
333 #define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
334 #define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
335 #define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
336 #define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
337 #define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
338 #define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
339 #define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
340 #define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
341 #define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
342 #define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
343 #define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
344 #define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
345 #define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
346 #define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
348 #define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24)
349 #define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25)
350 #define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26)
351 #define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27)
352 #define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28)
355 * SRI Control register (Table 8-24, 8-25) Offset 0x6C
358 #define S_LDT_SRICTRL_NEEDRESP 0
359 #define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP)
360 #define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP)
361 #define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP)
363 #define S_LDT_SRICTRL_NEEDNPREQ 2
364 #define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ)
365 #define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ)
366 #define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ)
368 #define S_LDT_SRICTRL_NEEDPREQ 4
369 #define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ)
370 #define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ)
371 #define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ)
373 #define S_LDT_SRICTRL_WANTRESP 8
374 #define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP)
375 #define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP)
376 #define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP)
378 #define S_LDT_SRICTRL_WANTNPREQ 10
379 #define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ)
380 #define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ)
381 #define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ)
383 #define S_LDT_SRICTRL_WANTPREQ 12
384 #define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ)
385 #define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ)
386 #define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ)
388 #define S_LDT_SRICTRL_BUFRELSPACE 16
389 #define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE)
390 #define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE)
391 #define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE)
394 * LDT SRI Transmit Buffer Count register (Table 8-26)
397 #define S_LDT_TXBUFCNT_PCMD 0
398 #define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD)
399 #define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD)
400 #define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD)
402 #define S_LDT_TXBUFCNT_PDATA 4
403 #define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA)
404 #define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA)
405 #define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA)
407 #define S_LDT_TXBUFCNT_NPCMD 8
408 #define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD)
409 #define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD)
410 #define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD)
412 #define S_LDT_TXBUFCNT_NPDATA 12
413 #define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA)
414 #define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA)
415 #define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA)
417 #define S_LDT_TXBUFCNT_RCMD 16
418 #define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD)
419 #define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD)
420 #define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD)
422 #define S_LDT_TXBUFCNT_RDATA 20
423 #define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA)
424 #define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA)
425 #define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA)
427 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
429 * Additional Status Register
432 #define S_LDT_ADDSTATUS_TGTDONE 0
433 #define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE)
434 #define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE)
435 #define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE)
436 #endif /* 1250 PASS2 || 112x PASS1 */