sys/arch/newsmips/include/adrsmap.h

   1 /*      $NetBSD: adrsmap.h,v 1.6.24.3 2004/09/21 13:19:33 skrll Exp $   */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * Sony Corp. and Kazumasa Utashiro of Software Research Associates, Inc.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. Neither the name of the University nor the names of its contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * from: $Hdr: adrsmap.h,v 4.300 91/06/09 06:34:29 root Rel41 $ SONY
  35  *
  36  *      @(#)adrsmap.h   8.1 (Berkeley) 6/11/93
  37  */
  38
  39 /*
  40  * adrsmap.h
  41  *
  42  * Define all hardware address map.
  43  */
  44
  45 #ifndef __MACHINE_ADRSMAP__
  46 #define __MACHINE_ADRSMAP__
  47
  48 /*----------------------------------------------------------------------
  49  *      news3400
  50  *----------------------------------------------------------------------*/
  51 /*
  52  * timer
  53  */
  54 #define RTC_PORT        0xbff407f8
  55 #define DATA_PORT       0xbff407f9
  56
  57 #ifdef notdef
  58 #define EN_ITIMER       0xb8000004      /*XXX:???*/
  59 #endif
  60
  61 #define INTEN0  0xbfc80000
  62 #define         INTEN0_PERR     0x80
  63 #define         INTEN0_ABORT    0x40
  64 #define         INTEN0_BERR     0x20
  65 #define         INTEN0_TIMINT   0x10
  66 #define         INTEN0_KBDINT   0x08
  67 #define         INTEN0_MSINT    0x04
  68 #define         INTEN0_CFLT     0x02
  69 #define         INTEN0_CBSY     0x01
  70
  71 #define INTEN1  0xbfc80001
  72 #define         INTEN1_BEEP     0x80
  73 #define         INTEN1_SCC      0x40
  74 #define         INTEN1_LANCE    0x20
  75 #define         INTEN1_DMA      0x10
  76 #define         INTEN1_SLOT1    0x08
  77 #define         INTEN1_SLOT3    0x04
  78 #define         INTEN1_EXT1     0x02
  79 #define         INTEN1_EXT3     0x01
  80
  81 #define INTST0  0xbfc80002
  82 #define         INTST0_PERR     0x80
  83 #define         INTST0_ABORT    0x40
  84 #define         INTST0_BERR     0x00    /* N/A */
  85 #define         INTST0_TIMINT   0x10
  86 #define         INTST0_KBDINT   0x08
  87 #define         INTST0_MSINT    0x04
  88 #define         INTST0_CFLT     0x02
  89 #define         INTST0_CBSY     0x01
  90 #define                 INTST0_PERR_BIT         7
  91 #define                 INTST0_ABORT_BIT        6
  92 #define                 INTST0_BERR_BIT         5       /* N/A */
  93 #define                 INTST0_TIMINT_BIT       4
  94 #define                 INTST0_KBDINT_BIT       3
  95 #define                 INTST0_MSINT_BIT        2
  96 #define                 INTST0_CFLT_BIT         1
  97 #define                 INTST0_CBSY_BIT         0
  98
  99 #define INTST1  0xbfc80003
 100 #define         INTST1_BEEP     0x80
 101 #define         INTST1_SCC      0x40
 102 #define         INTST1_LANCE    0x20
 103 #define         INTST1_DMA      0x10
 104 #define         INTST1_SLOT1    0x08
 105 #define         INTST1_SLOT3    0x04
 106 #define         INTST1_EXT1     0x02
 107 #define         INTST1_EXT3     0x01
 108 #define                 INTST1_BEEP_BIT         7
 109 #define                 INTST1_SCC_BIT          6
 110 #define                 INTST1_LANCE_BIT        5
 111 #define                 INTST1_DMA_BIT          4
 112 #define                 INTST1_SLOT1_BIT        3
 113 #define                 INTST1_SLOT3_BIT        2
 114 #define                 INTST1_EXT1_BIT         1
 115 #define                 INTST1_EXT3_BIT         0
 116
 117 #define INTCLR0 0xbfc80004
 118 #define         INTCLR0_PERR    0x80
 119 #define         INTCLR0_ABORT   0x40
 120 #define         INTCLR0_BERR    0x20
 121 #define         INTCLR0_TIMINT  0x10
 122 #define         INTCLR0_KBDINT  0x00    /* N/A */
 123 #define         INTCLR0_MSINT   0x00    /* N/A */
 124 #define         INTCLR0_CFLT    0x02
 125 #define         INTCLR0_CBSY    0x01
 126
 127 #define INTCLR1 0xbfc80005
 128 #define         INTCLR1_BEEP    0x80
 129 #define         INTCLR1_SCC     0x00    /* N/A */
 130 #define         INTCLR1_LANCE   0x00    /* N/A */
 131 #define         INTCLR1_DMA     0x00    /* N/A */
 132 #define         INTCLR1_SLOT1   0x00    /* N/A */
 133 #define         INTCLR1_SLOT3   0x00    /* N/A */
 134 #define         INTCLR1_EXT1    0x00    /* N/A */
 135 #define         INTCLR1_EXT3    0x00    /* N/A */
 136
 137 #define ITIMER          0xbfc80006
 138 #define IOCLOCK         4915200
 139
 140 #define DIP_SWITCH      0xbfe40000
 141 #define IDROM           0xbfe80000
 142
 143 #define DEBUG_PORT      0xbfcc0003
 144 #define         DP_READ         0x00
 145 #define         DP_WRITE        0xf0
 146 #define         DP_LED0         0x01
 147 #define         DP_LED1         0x02
 148 #define         DP_LED2         0x04
 149 #define         DP_LED3         0x08
 150
 151
 152 #define LANCE_PORT      0xbff80000
 153 #define LANCE_MEMORY    0xbffc0000
 154 #define ETHER_ID        IDROM_PORT
 155
 156 #define LANCE_PORT1     0xb8c30000      /* expansion lance #1 */
 157 #define LANCE_MEMORY1   0xb8c20000
 158 #define ETHER_ID1       0xb8c38000
 159
 160 #define LANCE_PORT2     0xb8c70000      /* expansion lance #2 */
 161 #define LANCE_MEMORY2   0xb8c60000
 162 #define ETHER_ID2       0xb8c78000
 163
 164 #define IDROM_PORT      0xbfe80000
 165
 166 #define SCCPORT0B       0xbfec0000
 167 #define SCCPORT0A       0xbfec0002
 168 #define SCCPORT1B       0xb8c40100
 169 #define SCCPORT1A       0xb8c40102
 170 #define SCCPORT2B       0xb8c40104
 171 #define SCCPORT2A       0xb8c40106
 172 #define SCCPORT3B       0xb8c40110
 173 #define SCCPORT3A       0xb8c40112
 174 #define SCCPORT4B       0xb8c40114
 175 #define SCCPORT4A       0xb8c40116
 176
 177 #define SCC_STATUS0     0xbfcc0002
 178 #define SCC_STATUS1     0xb8c40108
 179 #define SCC_STATUS2     0xb8c40118
 180
 181 #define SCCVECT         (0x1fcc0007 | MIPS_KSEG1_START)
 182 #define SCC_RECV        2
 183 #define SCC_XMIT        0
 184 #define SCC_CTRL        3
 185 #define SCC_STAT        1
 186 #define SCC_INT_MASK    0x6
 187
 188 /*XXX: SHOULD BE FIX*/
 189 #define KEYB_DATA       0xbfd00000      /* keyboard data port */
 190 #define KEYB_STAT       0xbfd00001      /* keyboard status port */
 191 #define KEYB_INTE       INTEN0          /* keyboard interrupt enable */
 192 #define KEYB_RESET      0xbfd00002      /* keyboard reset port*/
 193 #define KEYB_INIT1      0xbfd00003      /* keyboard speed */
 194 #define KEYB_INIT2      KEYB_INIT1      /* keyboard clock */
 195 #define KEYB_BUZZ       0xbfd40001      /* keyboard buzzer (length) */
 196 #define KEYB_BUZZF      0xbfd40000      /* keyboard buzzer frequency */
 197 #define MOUSE_DATA      0xbfd00004      /* mouse data port */
 198 #define MOUSE_STAT      0xbfd00005      /* mouse status port */
 199 #define MOUSE_INTE      INTEN0          /* mouse interrupt enable */
 200 #define MOUSE_RESET     0xbfd00006      /* mouse reset port */
 201 #define MOUSE_INIT1     0xbfd00007      /* mouse speed */
 202 #define MOUSE_INIT2     MOUSE_INIT1     /* mouse clock */
 203
 204 #define RX_MSINTE       0x04            /* Mouse Interrupt Enable */
 205 #define RX_KBINTE       0x08            /* Keyboard Intr. Enable */
 206 #define RX_MSINT        0x04            /* Mouse Interrupted */
 207 #define RX_KBINT        0x08            /* Keyboard Interrupted */
 208 #define RX_MSBUF        0x01            /* Mouse data buffer Full */
 209 #define RX_KBBUF        0x01            /* Keyboard data Full */
 210 #define RX_MSRDY        0x02            /* Mouse data ready */
 211 #define RX_KBRDY        0x02            /* Keyboard data ready */
 212 /*XXX: SHOULD BE FIX*/
 213
 214 #define ABEINT_BADDR    0xbfdc0038
 215
 216 #define NEWS5000_DIP_SWITCH     0xbf3d0000
 217 #define NEWS5000_IDROM          0xbf3c0000
 218
 219 #define NEWS5000_TIMER0         0xbf800000
 220 #define NEWS5000_FREERUN        0xbf840000
 221 #define NEWS5000_NVRAM          0xbf880000
 222 #define NEWS5000_NVRAM_SIZE     0x07f8
 223 #define NEWS5000_RTC_PORT       0xbf881fe0
 224
 225 #define NEWS5000_INTCLR0        0xbf4e0000
 226 #define NEWS5000_INTCLR1        0xbf4e0004
 227 #define NEWS5000_INTCLR2        0xbf4e0008
 228 #define NEWS5000_INTCLR3        0xbf4e000c
 229 #define NEWS5000_INTCLR4        0xbf4e0010
 230 #define NEWS5000_INTCLR5        0xbf4e0014
 231
 232 #define NEWS5000_INTEN0         0xbfa00000
 233 #define NEWS5000_INTEN1         0xbfa00004
 234 #define NEWS5000_INTEN2         0xbfa00008
 235 #define NEWS5000_INTEN3         0xbfa0000c
 236 #define NEWS5000_INTEN4         0xbfa00010
 237 #define NEWS5000_INTEN5         0xbfa00014
 238
 239 #define NEWS5000_INTST0         0xbfa00020
 240 #define NEWS5000_INTST1         0xbfa00024
 241 #define NEWS5000_INTST2         0xbfa00028
 242 #define NEWS5000_INTST3         0xbfa0002c
 243 #define NEWS5000_INTST4         0xbfa00030
 244 #define NEWS5000_INTST5         0xbfa00034
 245
 246 /*
 247  * level0 intr (INTMASK0/INTSTAT0)
 248  */
 249 #define NEWS5000_INT0_DMAC      0x01
 250 #define NEWS5000_INT0_SONIC     0x02
 251 #define NEWS5000_INT0_FDC       0x10
 252
 253 /*
 254  * level1 intr (INTMASK1/INTSTAT1)
 255  */
 256 #define NEWS5000_INT1_KBD       0x01
 257 #define NEWS5000_INT1_SCC       0x02
 258 #define NEWS5000_INT1_AUDIO0    0x04
 259 #define NEWS5000_INT1_AUDIO1    0x08
 260 #define NEWS5000_INT1_PARALLEL  0x20
 261 #define NEWS5000_INT1_FB        0x80
 262
 263 /*
 264  * level2 intr (INTMASK2/INTSTAT2)
 265  */
 266 #define NEWS5000_INT2_TIMER0    0x01
 267 #define NEWS5000_INT2_TIMER1    0x02
 268
 269 /*
 270  * level4 intr (INTMASK4/INTSTAT4)
 271  */
 272 #define NEWS5000_INT4_APBUS     0x01
 273
 274 #define NEWS5000_WBFLUSH        0xbf520004
 275
 276 #define NEWS5000_LED_POWER      0xbf3f0000
 277 #define NEWS5000_LED_DISK       0xbf3f0004
 278 #define NEWS5000_LED_FLOPPY     0xbf3f0008
 279 #define NEWS5000_LED_SEC        0xbf3f000c
 280 #define NEWS5000_LED_NET        0xbf3f0010
 281 #define NEWS5000_LED_CD         0xbf3f0014
 282
 283 #define NEWS5000_APBUS_INTMSK   0xb4c0000c      /* interrupt mask */
 284 #define         NEWS5000_APBUS_INT_DMAADDR      0x0100
 285 #define         NEWS5000_APBUS_INT_RDTIMEO      0x0004
 286 #define         NEWS5000_APBUS_INT_WRTIMEO      0x0001
 287 #define NEWS5000_APBUS_INTST    0xb4c00014      /* interrupt status */
 288 #define NEWS5000_APBUS_BER_A    0xb4c0001c      /* Bus error address */
 289 #define NEWS5000_APBUS_CTRL     0xb4c00034      /* configuration control */
 290 #define NEWS5000_APBUS_DER_A    0xb400005c      /* DMA error address */
 291 #define NEWS5000_APBUS_DER_S    0xb4c0006c      /* DMA error slot */
 292 #define NEWS5000_APBUS_DMA      0xb4c00084      /* unmapped DMA coherency */
 293
 294 #define NEWS5000_APBUS_DMAMAP   0xb4c20000      /* DMA mapping RAM */
 295 #define         NEWS5000_APBUS_MAPSIZE  0x20000 /* size of mapping RAM */
 296 #define         NEWS5000_APBUS_MAPENT   0x8     /* size of mapping entry */
 297 #define         NEWS5000_APBUS_MAP_VALID        0x80000000
 298 #define         NEWS5000_APBUS_MAP_COHERENT     0x40000000
 299
 300 #define NEWS5000_SCCPORT0A      0xbe950000
 301
 302 #endif /* !__MACHINE_ADRSMAP__ */