sys/arch/next68k/include/cpu.h

   1 /*      $NetBSD: cpu.h,v 1.40 2007/10/17 19:56:04 garbled Exp $ */
   2
   3 /*
   4  * Copyright (c) 1982, 1990, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * the Systems Programming Group of the University of Utah Computer
   9  * Science Department.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. Neither the name of the University nor the names of its contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
  36  *
  37  *      @(#)cpu.h       8.4 (Berkeley) 1/5/94
  38  */
  39 /*
  40  * Copyright (c) 1988 University of Utah.
  41  *
  42  * This code is derived from software contributed to Berkeley by
  43  * the Systems Programming Group of the University of Utah Computer
  44  * Science Department.
  45  *
  46  * Redistribution and use in source and binary forms, with or without
  47  * modification, are permitted provided that the following conditions
  48  * are met:
  49  * 1. Redistributions of source code must retain the above copyright
  50  *    notice, this list of conditions and the following disclaimer.
  51  * 2. Redistributions in binary form must reproduce the above copyright
  52  *    notice, this list of conditions and the following disclaimer in the
  53  *    documentation and/or other materials provided with the distribution.
  54  * 3. All advertising materials mentioning features or use of this software
  55  *    must display the following acknowledgement:
  56  *      This product includes software developed by the University of
  57  *      California, Berkeley and its contributors.
  58  * 4. Neither the name of the University nor the names of its contributors
  59  *    may be used to endorse or promote products derived from this software
  60  *    without specific prior written permission.
  61  *
  62  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  63  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  64  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  65  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  66  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  67  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  68  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  69  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  70  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  71  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  72  * SUCH DAMAGE.
  73  *
  74  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
  75  *
  76  *      @(#)cpu.h       8.4 (Berkeley) 1/5/94
  77  */
  78
  79
  80 #ifndef _MACHINE_CPU_H_
  81 #define _MACHINE_CPU_H_
  82
  83 #if defined(_KERNEL)
  84
  85 #if defined(_KERNEL_OPT)
  86 #include "opt_lockdebug.h"
  87 #endif
  88
  89 /*
  90  * Exported definitions unique to next68k/68k cpu support.
  91  */
  92
  93 /*
  94  * Get common m68k definitions.
  95  */
  96 #include <m68k/cpu.h>
  97
  98 #define M68K_MMU_MOTOROLA
  99
 100 /*
 101  * Get interrupt glue.
 102  */
 103 #include <machine/intr.h>
 104
 105 #include <sys/cpu_data.h>
 106 struct cpu_info {
 107         struct cpu_data ci_data;        /* MI per-cpu data */
 108         cpuid_t ci_cpuid;
 109         int     ci_mtx_count;
 110         int     ci_mtx_oldspl;
 111         int     ci_want_resched;
 112 };
 113
 114 extern struct cpu_info cpu_info_store;
 115
 116 #define curcpu()                        (&cpu_info_store)
 117
 118 /*
 119  * definitions of cpu-dependent requirements
 120  * referenced in generic code
 121  */
 122 #define cpu_number()                    0
 123
 124 void    cpu_proc_fork(struct proc *, struct proc *);
 125
 126
 127 /*
 128  * Arguments to hardclock and gatherstats encapsulate the previous
 129  * machine state in an opaque clockframe.  One the hp300, we use
 130  * what the hardware pushes on an interrupt (frame format 0).
 131  */
 132 struct clockframe {
 133         u_short sr;             /* sr at time of interrupt */
 134         u_long  pc;             /* pc at time of interrupt */
 135         u_short fmt:4,
 136                 vec:12;         /* vector offset (4-word frame) */
 137 } __attribute__((packed));
 138
 139 #define CLKF_USERMODE(framep)   (((framep)->sr & PSL_S) == 0)
 140 #define CLKF_PC(framep)         ((framep)->pc)
 141
 142 /*
 143  * The clock interrupt handler can determine if it's a nested
 144  * interrupt by checking for interrupt_depth > 1.
 145  * (Remember, the clock interrupt handler itself will cause the
 146  * depth counter to be incremented).
 147  */
 148 extern volatile unsigned int interrupt_depth;
 149 #define CLKF_INTR(framep)       (interrupt_depth > 1)
 150
 151 /*
 152  * Preempt the current process if in interrupt from user mode,
 153  * or after the current trap/syscall if in system mode.
 154  */
 155 #define cpu_need_resched(ci, flags)     \
 156         do { ci->ci_want_resched = 1; aston(); } while (/* CONSTCOND */0)
 157
 158 /*
 159  * Give a profiling tick to the current process when the user profiling
 160  * buffer pages are invalid.  On the sun3, request an ast to send us
 161  * through trap, marking the proc as needing a profiling tick.
 162  */
 163 #define cpu_need_proftick(l)    ((l)->l_pflag |= LP_OWEUPC, aston())
 164
 165 /*
 166  * Notify the current process (p) that it has a signal pending,
 167  * process as soon as possible.
 168  */
 169 #define cpu_signotify(l)        aston()
 170
 171 #define aston() (astpending++)
 172
 173 extern  int     astpending;     /* need to trap before returning to user mode */
 174
 175 extern  void (*vectab[])(void);
 176
 177 struct fpframe;
 178
 179 /* locore.s functions */
 180 void    m68881_save(struct fpframe *);
 181 void    m68881_restore(struct fpframe *);
 182
 183 int     suline(void *, void *);
 184 void    loadustp(int);
 185
 186 void    doboot(void) __attribute__((__noreturn__));
 187 int     nmihand(void *);
 188
 189 /* clock.c functions */
 190 void    next68k_calibrate_delay(void);
 191
 192 #endif /* _KERNEL */
 193
 194 #define NEXT_RAMBASE  (0x4000000) /* really depends on slot, but... */
 195 #define NEXT_BANKSIZE (0x1000000) /* Size of a memory bank in physical address */
 196
 197 #if 0
 198 /* @@@ this needs to be fixed to work on 030's */
 199 #define NEXT_SLOT_ID            0x0
 200 #ifdef  M68030
 201 #define NEXT_SLOT_ID_BMAP       0x0
 202 #endif  /* M68030 */
 203 #endif
 204 #ifdef  M68040
 205 #ifdef DISABLE_NEXT_BMAP_CHIP           /* @@@ For turbo testing */
 206 #define NEXT_SLOT_ID_BMAP       0x0
 207 #else
 208 #define NEXT_SLOT_ID_BMAP       0x00100000
 209 #endif
 210 #define NEXT_SLOT_ID            0x0
 211 #endif  /* M68040 */
 212
 213 /****************************************************************/
 214
 215 /* Eventually, I'd like to move these defines off into
 216  * configure somewhere
 217  * Darrin B Jewell <jewell@mit.edu>  Thu Feb  5 03:50:58 1998
 218  */
 219 /* ROM */
 220 #define NEXT_P_EPROM            (NEXT_SLOT_ID+0x00000000)
 221 #define NEXT_P_EPROM_BMAP       (NEXT_SLOT_ID+0x01000000)
 222 #define NEXT_P_EPROM_SIZE       (128 * 1024)
 223
 224 /* device space */
 225 #define NEXT_P_DEV_SPACE        (NEXT_SLOT_ID+0x02000000)
 226 #define NEXT_P_DEV_BMAP         (NEXT_SLOT_ID+0x02100000)
 227 #define NEXT_DEV_SPACE_SIZE     0x0001c000
 228
 229 /* DMA control/status (writes MUST be 32-bit) */
 230 #define NEXT_P_SCSI_CSR         (NEXT_SLOT_ID+0x02000010)
 231 #define NEXT_P_SOUNDOUT_CSR     (NEXT_SLOT_ID+0x02000040)
 232 #define NEXT_P_DISK_CSR         (NEXT_SLOT_ID+0x02000050)
 233 #define NEXT_P_SOUNDIN_CSR      (NEXT_SLOT_ID+0x02000080)
 234 #define NEXT_P_PRINTER_CSR      (NEXT_SLOT_ID+0x02000090)
 235 #define NEXT_P_SCC_CSR          (NEXT_SLOT_ID+0x020000c0)
 236 #define NEXT_P_DSP_CSR          (NEXT_SLOT_ID+0x020000d0)
 237 #define NEXT_P_ENETX_CSR        (NEXT_SLOT_ID+0x02000110)
 238 #define NEXT_P_ENETR_CSR        (NEXT_SLOT_ID+0x02000150)
 239 #define NEXT_P_VIDEO_CSR        (NEXT_SLOT_ID+0x02000180)
 240 #define NEXT_P_M2R_CSR          (NEXT_SLOT_ID+0x020001d0)
 241 #define NEXT_P_R2M_CSR          (NEXT_SLOT_ID+0x020001c0)
 242
 243 /* DMA scratch pad (writes MUST be 32-bit) */
 244 #define NEXT_P_VIDEO_SPAD       (NEXT_SLOT_ID+0x02004180)
 245 #define NEXT_P_EVENT_SPAD       (NEXT_SLOT_ID+0x0200418c)
 246 #define NEXT_P_M2M_SPAD         (NEXT_SLOT_ID+0x020041e0)
 247
 248 /* device registers */
 249 #define NEXT_P_ENET             (NEXT_SLOT_ID_BMAP+0x02006000)
 250 #define NEXT_P_DSP              (NEXT_SLOT_ID_BMAP+0x02008000)
 251 #define NEXT_P_MON              (NEXT_SLOT_ID+0x0200e000)
 252 #define NEXT_P_PRINTER          (NEXT_SLOT_ID+0x0200f000)
 253 #define NEXT_P_DISK             (NEXT_SLOT_ID_BMAP+0x02012000)
 254 #define NEXT_P_SCSI             (NEXT_SLOT_ID_BMAP+0x02014000)
 255 #define NEXT_P_FLOPPY           (NEXT_SLOT_ID_BMAP+0x02014100)
 256 #define NEXT_P_TIMER            (NEXT_SLOT_ID_BMAP+0x02016000)
 257 #define NEXT_P_TIMER_CSR        (NEXT_SLOT_ID_BMAP+0x02016004)
 258 #define NEXT_P_SCC              (NEXT_SLOT_ID_BMAP+0x02018000)
 259 #define NEXT_P_SCC_CLK          (NEXT_SLOT_ID_BMAP+0x02018004)
 260 #define NEXT_P_EVENTC           (NEXT_SLOT_ID_BMAP+0x0201a000)
 261 #define NEXT_P_BMAP             (NEXT_SLOT_ID+0x020c0000)
 262 /* All COLOR_FB registers are 1 byte wide */
 263 #define NEXT_P_C16_DAC_0        (NEXT_SLOT_ID_BMAP+0x02018100)  /* COLOR_FB - RAMDAC */
 264 #define NEXT_P_C16_DAC_1        (NEXT_SLOT_ID_BMAP+0x02018101)
 265 #define NEXT_P_C16_DAC_2        (NEXT_SLOT_ID_BMAP+0x02018102)
 266 #define NEXT_P_C16_DAC_3        (NEXT_SLOT_ID_BMAP+0x02018103)
 267 #define NEXT_P_C16_CMD_REG      (NEXT_SLOT_ID_BMAP+0x02018180)  /* COLOR_FB - CSR */
 268
 269 /* system control registers */
 270 #define NEXT_P_MEMTIMING        (NEXT_SLOT_ID_BMAP+0x02006010)
 271 #define NEXT_P_INTRSTAT         (NEXT_SLOT_ID+0x02007000)
 272 #define NEXT_P_INTRSTAT_CON     0x02007000
 273 /* #define NEXT_P_INTRSTAT_0    (NEXT_SLOT_ID+0x02008000) */
 274 #define NEXT_P_INTRMASK         (NEXT_SLOT_ID+0x02007800)
 275 #define NEXT_P_INTRMASK_CON     0x02007800
 276 /* #define NEXT_P_INTRMASK_0    (NEXT_SLOT_ID+0x0200a000) */
 277 #define NEXT_P_SCR1             (NEXT_SLOT_ID+0x0200c000)
 278 #define NEXT_P_SCR1_CON 0x0200c000
 279 #define NEXT_P_SID              0x0200c800              /* NOT slot-relative */
 280 #define NEXT_P_SCR2             (NEXT_SLOT_ID+0x0200d000)
 281 #define NEXT_P_SCR2_CON 0x0200d000
 282 #define NEXT_P_RMTINT           (NEXT_SLOT_ID+0x0200d800)
 283 #define NEXT_P_BRIGHTNESS       (NEXT_SLOT_ID_BMAP+0x02010000)
 284 #define NEXT_P_DRAM_TIMING      (NEXT_SLOT_ID_BMAP+0x02018190) /* Warp 9C memory ctlr */
 285 #define NEXT_P_VRAM_TIMING      (NEXT_SLOT_ID_BMAP+0x02018198) /* Warp 9C memory ctlr */
 286
 287 /* memory */
 288 #define NEXT_P_MAINMEM          (NEXT_SLOT_ID+0x04000000)
 289 #define NEXT_P_MEMSIZE          0x04000000
 290 #define NEXT_P_VIDEOMEM         (NEXT_SLOT_ID+0x0b000000)
 291 #define NEXT_P_VIDEOSIZE        0x0003a800
 292 #if 0
 293 #define NEXT_P_C16_VIDEOMEM     (NEXT_SLOT_ID+0x06000000)       /* COLOR_FB */
 294 #endif
 295 #define NEXT_P_C16_VIDEOMEM     (0x2c000000)
 296 #define NEXT_P_C16_VIDEOSIZE    0x001D4000              /* COLOR_FB */
 297 #define NEXT_P_WF4VIDEO         (NEXT_SLOT_ID+0x0c000000)       /* w A+B-AB function */
 298 #define NEXT_P_WF3VIDEO         (NEXT_SLOT_ID+0x0d000000)       /* w (1-A)B function */
 299 #define NEXT_P_WF2VIDEO         (NEXT_SLOT_ID+0x0e000000)       /* w ceil(A+B) function */
 300 #define NEXT_P_WF1VIDEO         (NEXT_SLOT_ID+0x0f000000)       /* w AB function */
 301 #define NEXT_P_WF4MEM           (NEXT_SLOT_ID+0x10000000)       /* w A+B-AB function */
 302 #define NEXT_P_WF3MEM           (NEXT_SLOT_ID+0x14000000)       /* w (1-A)B function */
 303 #define NEXT_P_WF2MEM           (NEXT_SLOT_ID+0x18000000)       /* w ceil(A+B) function */
 304 #define NEXT_P_WF1MEM           (NEXT_SLOT_ID+0x1c000000)       /* w AB function */
 305 #define NEXT_NMWF               4                       /* # of memory write funcs */
 306
 307 /*
 308  * Interrupt structure.
 309  * BASE and BITS define the origin and length of the bit field in the
 310  * interrupt status/mask register for the particular interrupt level.
 311  * The first component of the interrupt device name indicates the bit
 312  * position in the interrupt status and mask registers; the second is the
 313  * interrupt level; the third is the bit index relative to the start of the
 314  * bit field.
 315  */
 316 #define NEXT_I(l,i,b)   (((b) << 8) | ((l) << 4) | (i))
 317 #define NEXT_I_INDEX(i) ((i) & 0xf)
 318 #define NEXT_I_IPL(i)   (((i) >> 4) & 7)
 319 #define NEXT_I_BIT(i)   ( 1 << (((i) >> 8) & 0x1f))
 320
 321 #define NEXT_I_IPL7_BASE        0
 322 #define NEXT_I_IPL7_BITS        2
 323 #define NEXT_I_NMI              NEXT_I(7,0,31)
 324 #define NEXT_I_PFAIL            NEXT_I(7,1,30)
 325
 326 #define NEXT_I_IPL6_BASE        2
 327 #define NEXT_I_IPL6_BITS        12
 328 #define NEXT_I_TIMER            NEXT_I(6,0,29)
 329 #define NEXT_I_ENETX_DMA        NEXT_I(6,1,28)
 330 #define NEXT_I_ENETR_DMA        NEXT_I(6,2,27)
 331 #define NEXT_I_SCSI_DMA         NEXT_I(6,3,26)
 332 #define NEXT_I_DISK_DMA         NEXT_I(6,4,25)
 333 #define NEXT_I_PRINTER_DMA      NEXT_I(6,5,24)
 334 #define NEXT_I_SOUND_OUT_DMA    NEXT_I(6,6,23)
 335 #define NEXT_I_SOUND_IN_DMA     NEXT_I(6,7,22)
 336 #define NEXT_I_SCC_DMA          NEXT_I(6,8,21)
 337 #define NEXT_I_DSP_DMA          NEXT_I(6,9,20)
 338 #define NEXT_I_M2R_DMA          NEXT_I(6,10,19)
 339 #define NEXT_I_R2M_DMA          NEXT_I(6,11,18)
 340
 341 #define NEXT_I_IPL5_BASE        14
 342 #define NEXT_I_IPL5_BITS        3
 343 #define NEXT_I_SCC              NEXT_I(5,0,17)
 344 #define NEXT_I_REMOTE           NEXT_I(5,1,16)
 345 #define NEXT_I_BUS              NEXT_I(5,2,15)
 346
 347 #define NEXT_I_IPL4_BASE        17
 348 #define NEXT_I_IPL4_BITS        1
 349 #define NEXT_I_DSP_4            NEXT_I(4,0,14)
 350
 351 #define NEXT_I_IPL3_BASE        18
 352 #define NEXT_I_IPL3_BITS        12
 353 #define NEXT_I_DISK             NEXT_I(3,0,13)
 354 #define NEXT_I_C16_VIDEO        NEXT_I(3,0,13)  /* COLOR_FB - Steals old ESDI interrupt */
 355 #define NEXT_I_SCSI             NEXT_I(3,1,12)
 356 #define NEXT_I_PRINTER          NEXT_I(3,2,11)
 357 #define NEXT_I_ENETX            NEXT_I(3,3,10)
 358 #define NEXT_I_ENETR            NEXT_I(3,4,9)
 359 #define NEXT_I_SOUND_OVRUN      NEXT_I(3,5,8)
 360 #define NEXT_I_PHONE            NEXT_I(3,6,7)
 361 #define NEXT_I_DSP_3            NEXT_I(3,7,6)
 362 #define NEXT_I_VIDEO            NEXT_I(3,8,5)
 363 #define NEXT_I_MONITOR          NEXT_I(3,9,4)
 364 #define NEXT_I_KYBD_MOUSE       NEXT_I(3,10,3)
 365 #define NEXT_I_POWER            NEXT_I(3,11,2)
 366
 367 #define NEXT_I_IPL2_BASE        30
 368 #define NEXT_I_IPL2_BITS        1
 369 #define NEXT_I_SOFTINT1         NEXT_I(2,0,1)
 370
 371 #define NEXT_I_IPL1_BASE        31
 372 #define NEXT_I_IPL1_BITS        1
 373 #define NEXT_I_SOFTINT0         NEXT_I(1,0,0)
 374
 375 /****************************************************************/
 376
 377 /* physical memory sections */
 378 #if 0
 379 #define ROMBASE         (0x00000000)
 380 #endif
 381
 382 #define INTIOBASE       (0x02000000)
 383 #define INTIOTOP        (0x02120000)
 384 #define MONOBASE        (0x0b000000)
 385 #define MONOTOP         (0x0b03a800)
 386 #define COLORBASE       (0x2c000000)
 387 #define COLORTOP        (0x2c1D4000)
 388
 389 #define NEXT_INTR_BITS \
 390 "\20\40NMI\37PFAIL\36TIMER\35ENETX_DMA\34ENETR_DMA\33SCSI_DMA\32DISK_DMA\31PRINTER_DMA\30SOUND_OUT_DMA\27SOUND_IN_DMA\26SCC_DMA\25DSP_DMA\24M2R_DMA\23R2M_DMA\22SCC\21REMOTE\20BUS\17DSP_4\16DISK|C16_VIDEO\15SCSI\14PRINTER\13ENETX\12ENETR\11SOUND_OVRUN\10PHONE\07DSP_3\06VIDEO\05MONITOR\04KYBD_MOUSE\03POWER\02SOFTINT1\01SOFTINT0"
 391
 392 /*
 393  * Internal IO space:
 394  *
 395  * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE).
 396  *
 397  * Internal IO space is mapped in the kernel from ``intiobase'' to
 398  * ``intiolimit'' (defined in locore.s).  Since it is always mapped,
 399  * conversion between physical and kernel virtual addresses is easy.
 400  */
 401 #define IIOV(pa)        ((int)(pa)-INTIOBASE+intiobase)
 402 #define IIOP(va)        ((int)(va)-intiobase+INTIOBASE)
 403 #define IIOMAPSIZE      btoc(INTIOTOP-INTIOBASE)        /* 2mb */
 404
 405 /* mono fb space */
 406 #define MONOMAPSIZE     btoc(MONOTOP-MONOBASE)  /* who cares */
 407
 408 /* color fb space */
 409 #define COLORMAPSIZE    btoc(COLORTOP-COLORBASE)        /* who cares */
 410
 411 #endif  /* _MACHINE_CPU_H_ */