sys/arch/powerpc/fpu/fpu_arith.h

   1 /*      $NetBSD: fpu_arith.h,v 1.3 2005/12/11 12:18:42 christos Exp $ */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)fpu_arith.h 8.1 (Berkeley) 6/11/93
  41  */
  42
  43 /*
  44  * Extended-precision arithmetic.
  45  *
  46  * We hold the notion of a `carry register', which may or may not be a
  47  * machine carry bit or register.  On the SPARC, it is just the machine's
  48  * carry bit.
  49  *
  50  * In the worst case, you can compute the carry from x+y as
  51  *      (unsigned)(x + y) < (unsigned)x
  52  * and from x+y+c as
  53  *      ((unsigned)(x + y + c) <= (unsigned)x && (y|c) != 0)
  54  * for example.
  55  */
  56
  57
  58 #ifndef FPE_USE_ASM
  59
  60 /* set up for extended-precision arithemtic */
  61 #define FPU_DECL_CARRY quad_t fpu_carry, fpu_tmp;
  62
  63 /*
  64  * We have three kinds of add:
  65  *      add with carry:                                   r = x + y + c
  66  *      add (ignoring current carry) and set carry:     c'r = x + y + 0
  67  *      add with carry and set carry:                   c'r = x + y + c
  68  * The macros use `C' for `use carry' and `S' for `set carry'.
  69  * Note that the state of the carry is undefined after ADDC and SUBC,
  70  * so if all you have for these is `add with carry and set carry',
  71  * that is OK.
  72  *
  73  * The same goes for subtract, except that we compute x - y - c.
  74  *
  75  * Finally, we have a way to get the carry into a `regular' variable,
  76  * or set it from a value.  SET_CARRY turns 0 into no-carry, nonzero
  77  * into carry; GET_CARRY sets its argument to 0 or 1.
  78  */
  79 #define FPU_ADDC(r, x, y) \
  80         (r) = (x) + (y) + (!!fpu_carry)
  81 #define FPU_ADDS(r, x, y) \
  82         { \
  83                 fpu_tmp = (quad_t)(x) + (quad_t)(y); \
  84                 (r) = (u_int)fpu_tmp; \
  85                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
  86         }
  87 #define FPU_ADDCS(r, x, y) \
  88         { \
  89                 fpu_tmp = (quad_t)(x) + (quad_t)(y) + (!!fpu_carry); \
  90                 (r) = (u_int)fpu_tmp; \
  91                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
  92         }
  93 #define FPU_SUBC(r, x, y) \
  94         (r) = (x) - (y) - (!!fpu_carry)
  95 #define FPU_SUBS(r, x, y) \
  96         { \
  97                 fpu_tmp = (quad_t)(x) - (quad_t)(y); \
  98                 (r) = (u_int)fpu_tmp; \
  99                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
 100         }
 101 #define FPU_SUBCS(r, x, y) \
 102         { \
 103                 fpu_tmp = (quad_t)(x) - (quad_t)(y) - (!!fpu_carry); \
 104                 (r) = (u_int)fpu_tmp; \
 105                 fpu_carry = ((fpu_tmp & 0xffffffff00000000LL) != 0); \
 106         }
 107
 108 #define FPU_GET_CARRY(r) (r) = (!!fpu_carry)
 109 #define FPU_SET_CARRY(v) fpu_carry = ((v) != 0)
 110
 111 #else
 112 /* set up for extended-precision arithemtic */
 113 #define FPU_DECL_CARRY
 114
 115 /*
 116  * We have three kinds of add:
 117  *      add with carry:                                   r = x + y + c
 118  *      add (ignoring current carry) and set carry:     c'r = x + y + 0
 119  *      add with carry and set carry:                   c'r = x + y + c
 120  * The macros use `C' for `use carry' and `S' for `set carry'.
 121  * Note that the state of the carry is undefined after ADDC and SUBC,
 122  * so if all you have for these is `add with carry and set carry',
 123  * that is OK.
 124  *
 125  * The same goes for subtract, except that we compute x - y - c.
 126  *
 127  * Finally, we have a way to get the carry into a `regular' variable,
 128  * or set it from a value.  SET_CARRY turns 0 into no-carry, nonzero
 129  * into carry; GET_CARRY sets its argument to 0 or 1.
 130  */
 131 #define FPU_ADDC(r, x, y) \
 132         __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
 133 #define FPU_ADDS(r, x, y) \
 134         __asm volatile("addc %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
 135 #define FPU_ADDCS(r, x, y) \
 136         __asm volatile("adde %0,%1,%2" : "=r"(r) : "r"(x), "r"(y))
 137 #define FPU_SUBC(r, x, y) \
 138         __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
 139 #define FPU_SUBS(r, x, y) \
 140         __asm volatile("subfc %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
 141 #define FPU_SUBCS(r, x, y) \
 142         __asm volatile("subfe %0,%2,%1" : "=r"(r) : "r"(x), "r"(y))
 143
 144 #define FPU_GET_CARRY(r) __asm volatile("li %0,0; addie %0,%0,0" : "=r"(r))
 145 /* This one needs to destroy a temp register. */
 146 #define FPU_SET_CARRY(v) do { int __tmp;                                \
 147                 __asm volatile("addic %0,%0,-1" : "r"(__tmp) : "r"(v)); \
 148         } while (0)
 149
 150 #define FPU_SHL1_BY_ADD /* shift left 1 faster by ADDC than (a<<1)|(b>>31) */
 151 #endif