sys/arch/powerpc/ibm4xx/dev/pcicreg.h

   1 /*      $NetBSD: ibm405gp.h,v 1.6 2002/08/11 13:32:20 simonb Exp $      */
   2
   3 /*
   4  * Copyright 2001 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _IBM4XX_PCICREG_H_
  39 #define _IBM4XX_PCICREG_H_
  40
  41 /* PCI Configuaration Registers */
  42 #define PCIC_CFGADDR            0x00
  43 #define PCIC_CFGDATA            0x04
  44
  45 #define PCIC_VENDID             0x00
  46 #define PCIC_DEVID              0x02
  47 #define PCIC_CMD                0x04
  48 #define PCIC_STATUS             0x06
  49 #define PCIC_REVID              0x08
  50 #define PCIC_CLS                0x09
  51 #define PCIC_CACHELS            0x0c
  52 #define PCIC_LATTIM             0x0d
  53 #define PCIC_HDTYPE             0x0e
  54 #define PCIC_BIST               0x0f
  55 #define PCIC_BAR0               0x10
  56 #define PCIC_BAR1               0x14            /* PCI name */
  57 #define PCIC_PTM1BAR            PCIC_BAR1       /* 405GP name */
  58 #define PCIC_BAR2               0x18            /* PCI name */
  59 #define PCIC_PTM2BAR            PCIC_BAR2       /* 405GP name */
  60 #define PCIC_BAR3               0x1C
  61 #define PCIC_BAR4               0x20
  62 #define PCIC_BAR5               0x24
  63 #define PCIC_SBSYSVID           0x2c
  64 #define PCIC_SBSYSID            0x2e
  65 #define PCIC_CAP                0x34
  66 #define PCIC_INTLN              0x3c
  67 #define PCIC_INTPN              0x3d
  68 #define PCIC_MINGNT             0x3e
  69 #define PCIC_MAXLTNCY           0x3f
  70
  71 #define PCIC_ICS                0x44    /* 405GP specific parameters */
  72 #define PCIC_ERREN              0x48
  73 #define PCIC_ERRSTS             0x49
  74 #define PCIC_BRDGOPT1           0x4a
  75 #define PCIC_PLBBESR0           0x4c
  76 #define PCIC_PLBBESR1           0x50
  77 #define PCIC_PLBBEAR            0x54
  78 #define PCIC_CAPID              0x58
  79 #define PCIC_NEXTIPTR           0x59
  80 #define PCIC_PMC                0x5a
  81 #define PCIC_PMCSR              0x5c
  82 #define PCIC_PMCSRBSE           0x5e
  83 #define PCIC_DATA               0x5f
  84 #define PCIC_BRDGOPT2           0x60
  85 #define PCIC_PMSCRR             0x64
  86
  87
  88 /* PCI Bridge Local Configuation Registers (0xef400000 0xef40003f - 64 bytes) */
  89 #define PCIL_PMM0LA             0x00    /* PCI Master Map 0: Local Address */
  90 #define PCIL_PMM0MA             0x04    /*                   Mask/Attribute */
  91 #define PCIL_PMM0PCILA          0x08    /*                   PCI Low Address */
  92 #define PCIL_PMM0PCIHA          0x0c    /*                   PCI High Address */
  93 #define PCIL_PMM1LA             0x10
  94 #define PCIL_PMM1MA             0x14
  95 #define PCIL_PMM1PCILA          0x18
  96 #define PCIL_PMM1PCIHA          0x1c
  97 #define PCIL_PMM2LA             0x20
  98 #define PCIL_PMM2MA             0x24
  99 #define PCIL_PMM2PCILA          0x28
 100 #define PCIL_PMM2PCIHA          0x2c
 101 #define PCIL_PTM1MS             0x30
 102 #define PCIL_PTM1LA             0x34
 103 #define PCIL_PTM2MS             0x38
 104 #define PCIL_PTM2LA             0x3c
 105 #endif  /* _IBM4XX_PCICREG_H_ */