1 /* $NetBSD: kse.c,v 1.2 2009/01/12 09:41:59 tsutsui Exp $ */
4 * Copyright (c) 2008 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/param.h>
34 #include <netinet/in.h>
35 #include <netinet/in_systm.h>
37 #include <lib/libsa/stand.h>
38 #include <lib/libsa/net.h>
43 * - reverse endian access every CSR.
44 * - no VTOPHYS() translation, vaddr_t == paddr_t.
45 * - PIPT writeback cache aware.
47 #define CSR_READ_4(l, r) in32rb((l)->csr+(r))
48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
49 #define CSR_READ_2(l, r) in16rb((l)->csr+(r))
50 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
51 #define VTOPHYS(va) (uint32_t)(va)
52 #define DEVTOV(pa) (uint32_t)(pa)
53 #define wbinv(adr, siz) _wbinv(VTOPHYS(adr), (uint32_t)(siz))
54 #define inv(adr, siz) _inv(VTOPHYS(adr), (uint32_t)(siz))
55 #define DELAY(n) delay(n)
56 #define ALLOC(T,A) (T *)((unsigned)alloc(sizeof(T) + (A)) &~ ((A) - 1))
59 uint32_t xd0
, xd1
, xd2
, xd3
;
61 #define T0_OWN (1U<<31) /* desc is ready to Tx */
62 #define T1_IC (1U<<31) /* post interrupt on complete */
63 #define T1_FS (1U<<30) /* first segment of frame */
64 #define T1_LS (1U<<29) /* last segment of frame */
65 #define T1_TER (1U<<25) /* end of ring */
66 #define T1_SPN 0x00300000 /* 21:20 switch port 1/2 */
67 #define T1_TBS_MASK 0x7ff /* segment size 10:0 */
69 #define R0_OWN (1U<<31) /* desc is empty */
70 #define R0_FS (1U<<30) /* first segment of frame */
71 #define R0_LS (1U<<29) /* last segment of frame */
72 #define R0_IPE (1U<<28) /* IP checksum error */
73 #define R0_TCPE (1U<<27) /* TCP checksum error */
74 #define R0_UDPE (1U<<26) /* UDP checksum error */
75 #define R0_ES (1U<<25) /* error summary */
76 #define R0_MF (1U<<24) /* multicast frame */
77 #define R0_SPN 0x00300000 /* 21:20 switch port 1/2 */
78 #define R0_RE (1U<<19) /* MII reported error */
79 #define R0_TL (1U<<18) /* frame too long, beyond 1518 */
80 #define R0_RF (1U<<17) /* damaged runt frame */
81 #define R0_CE (1U<<16) /* CRC error */
82 #define R0_FT (1U<<15) /* frame type */
83 #define R0_FL_MASK 0x7ff /* frame length 10:0 */
84 #define R1_RER (1U<<25) /* end of ring */
85 #define R1_RBS_MASK 0x7fc /* segment size 10:0 */
87 #define MDTXC 0x000 /* DMA transmit control */
88 #define MDRXC 0x004 /* DMA receive control */
89 #define MDTSC 0x008 /* DMA transmit start */
90 #define MDRSC 0x00c /* DMA receive start */
91 #define TDLB 0x010 /* transmit descriptor list base */
92 #define RDLB 0x014 /* receive descriptor list base */
93 #define MARL 0x200 /* MAC address low */
94 #define MARM 0x202 /* MAC address middle */
95 #define MARH 0x204 /* MAC address high */
96 #define CIDR 0x400 /* chip ID and enable */
97 #define P1CR4 0x512 /* port 1 control 4 */
98 #define P1SR 0x514 /* port 1 status */
100 #define FRAMESIZE 1536
105 uint8_t rxstore
[2][FRAMESIZE
];
109 static void mii_dealan(struct local
*, unsigned);
112 kse_match(unsigned tag
, void *data
)
116 v
= pcicfgread(tag
, PCI_ID_REG
);
118 case PCI_DEVICE(0x16c6, 0x8841):
119 case PCI_DEVICE(0x16c6, 0x8842):
126 kse_init(unsigned tag
, void *data
)
129 struct desc
*txd
, *rxd
;
130 unsigned i
, val
, fdx
;
133 l
= ALLOC(struct local
, sizeof(struct desc
)); /* desc alignment */
134 memset(l
, 0, sizeof(struct local
));
135 l
->csr
= DEVTOV(pcicfgread(tag
, 0x10));
138 i
= CSR_READ_2(l
, MARL
);
141 i
= CSR_READ_2(l
, MARM
);
144 i
= CSR_READ_2(l
, MARH
);
148 printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
149 en
[0], en
[1], en
[2], en
[3], en
[4], en
[5]);
151 CSR_WRITE_2(l
, CIDR
, 1);
155 val
= pcicfgread(tag
, PCI_ID_REG
);
156 if (PCI_PRODUCT(val
) == 0x8841) {
157 val
= CSR_READ_2(l
, P1SR
);
158 fdx
= !!(val
& (1U << 9));
159 printf("%s", (val
& (1U << 8)) ? "100Mbps" : "10Mbps");
167 rxd
[0].xd0
= htole32(R0_OWN
);
168 rxd
[0].xd1
= htole32(FRAMESIZE
);
169 rxd
[0].xd2
= htole32(VTOPHYS(l
->rxstore
[0]));
170 rxd
[0].xd3
= htole32(VTOPHYS(&rxd
[1]));
171 rxd
[1].xd0
= htole32(R0_OWN
);
172 rxd
[1].xd1
= htole32(R1_RER
| FRAMESIZE
);
173 rxd
[1].xd2
= htole32(VTOPHYS(l
->rxstore
[1]));
174 rxd
[1].xd3
= htole32(VTOPHYS(&rxd
[0]));
177 CSR_WRITE_4(l
, TDLB
, VTOPHYS(txd
));
178 CSR_WRITE_4(l
, RDLB
, VTOPHYS(rxd
));
179 CSR_WRITE_4(l
, MDTXC
, 07); /* stretch short, add CRC, Tx enable */
180 CSR_WRITE_4(l
, MDRXC
, 01); /* Rx enable */
181 CSR_WRITE_4(l
, MDRSC
, 01); /* start receiving */
187 kse_send(void *dev
, char *buf
, unsigned len
)
189 struct local
*l
= dev
;
190 volatile struct desc
*txd
;
191 unsigned txstat
, loop
;
195 txd
->xd2
= htole32(VTOPHYS(buf
));
196 txd
->xd1
= htole32(T1_FS
| T1_LS
| (len
& T1_TBS_MASK
));
197 txd
->xd0
= htole32(T0_OWN
);
198 wbinv(txd
, sizeof(struct desc
));
199 CSR_WRITE_4(l
, MDTSC
, 01); /* start transmission */
202 txstat
= le32toh(txd
->xd0
);
203 if ((txstat
& T0_OWN
) == 0)
206 inv(txd
, sizeof(struct desc
));
207 } while (--loop
!= 0);
208 printf("xmit failed\n");
215 kse_recv(void *dev
, char *buf
, unsigned maxlen
, unsigned timo
)
217 struct local
*l
= dev
;
218 volatile struct desc
*rxd
;
219 unsigned bound
, rxstat
, len
;
223 printf("recving with %u sec. timeout\n", timo
);
225 rxd
= &l
->rxd
[l
->rx
];
227 inv(rxd
, sizeof(struct desc
));
228 rxstat
= le32toh(rxd
->xd0
);
229 if ((rxstat
& R0_OWN
) == 0)
231 DELAY(1000); /* 1 milli second */
232 } while (--bound
> 0);
236 if (rxstat
& R0_ES
) {
237 rxd
->xd0
= htole32(R0_OWN
);
238 wbinv(rxd
, sizeof(struct desc
));
240 CSR_WRITE_4(l
, MDRSC
, 01); /* restart receiving */
244 len
= (rxstat
& R0_FL_MASK
) - 4 /* HASFCS */;
247 ptr
= l
->rxstore
[l
->rx
];
249 memcpy(buf
, ptr
, len
);
250 rxd
->xd0
= htole32(R0_OWN
);
251 wbinv(rxd
, sizeof(struct desc
));
253 CSR_WRITE_4(l
, MDRSC
, 01); /* necessary? */
258 mii_dealan(struct local
*l
, unsigned timo
)
262 val
= (1U << 13) | (1U << 7) | 0x1f /* advertise all caps */;
263 CSR_WRITE_2(l
, P1CR4
, val
);
264 bound
= getsecs() + timo
;
266 val
= CSR_READ_2(l
, P1SR
);
267 if (val
& (1U << 5)) /* link is found up */
270 } while (getsecs() < bound
);