sys/arch/sgimips/hpc/pi1ppcvar.h

   1 /* $NetBSD: pi1ppcvar.h,v 1.2 2007/03/04 06:00:40 christos Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2001 Alcove - Nicolas Souchu
   5  * Copyright (c) 2005 Joe Britt <britt@danger.com> - SGI PI1 version
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp
  30  *
  31  */
  32
  33 #ifndef __PI1PPCVAR_H
  34 #define __PI1PPCVAR_H
  35
  36 #include <machine/bus.h>
  37 #include <machine/types.h>
  38 #include <sys/device.h>
  39 #include <sys/callout.h>
  40
  41 #include <dev/ppbus/ppbus_conf.h>
  42
  43
  44 /* Maximum time to wait for device response */
  45 #define MAXBUSYWAIT     (5 * (hz))
  46
  47 /* Poll interval when wating for device to become ready */
  48 #define PI1PPC_POLL     ((hz)/10)
  49
  50 /* Interrupt priority level for pi1ppc device */
  51 #define IPL_PI1PPC      IPL_TTY
  52 #define splpi1ppc       spltty
  53
  54
  55 /* Diagnostic and verbose printing macros */
  56
  57 #ifdef PI1PPC_DEBUG
  58 extern int pi1ppc_debug;
  59 #define PI1PPC_DPRINTF(arg) if(pi1ppc_debug) printf arg
  60 #else
  61 #define PI1PPC_DPRINTF(arg)
  62 #endif
  63
  64 #ifdef PI1PPC_VERBOSE
  65 extern int pi1ppc_verbose;
  66 #define PI1PPC_VPRINTF(arg) if(pi1ppc_verbose) printf arg
  67 #else
  68 #define PI1PPC_VPRINTF(arg)
  69 #endif
  70
  71
  72 /* Flag used in DMA transfer */
  73 #define PI1PPC_DMA_MODE_READ 0x0
  74 #define PI1PPC_DMA_MODE_WRITE 0x1
  75
  76
  77 /* Flags passed via config */
  78 #define PI1PPC_FLAG_DISABLE_INTR        0x01
  79 #define PI1PPC_FLAG_DISABLE_DMA 0x02
  80
  81
  82 /* Locking for pi1ppc device */
  83 #if defined(MULTIPROCESSOR) || defined (LOCKDEBUG)
  84 #include <sys/lock.h>
  85 #define PI1PPC_SC_LOCK(sc) (&((sc)->sc_lock))
  86 #define PI1PPC_LOCK_INIT(sc) simple_lock_init(PI1PPC_SC_LOCK((sc)))
  87 #define PI1PPC_LOCK(sc) simple_lock(PI1PPC_SC_LOCK((sc)))
  88 #define PI1PPC_UNLOCK(sc) simple_unlock(PI1PPC_SC_LOCK((sc)))
  89 #else /* !(MULTIPROCESSOR) && !(LOCKDEBUG) */
  90 #define PI1PPC_LOCK_INIT(sc)
  91 #define PI1PPC_LOCK(sc)
  92 #define PI1PPC_UNLOCK(sc)
  93 #define PI1PPC_SC_LOCK(sc) NULL
  94 #endif /* MULTIPROCESSOR || LOCKDEBUG */
  95
  96 /* Single softintr callback entry */
  97 struct pi1ppc_handler_node {
  98         void (*func)(void *);
  99         void *arg;
 100         SLIST_ENTRY(pi1ppc_handler_node) entries;
 101 };
 102
 103 /* Generic structure to hold parallel port chipset info. */
 104 struct pi1ppc_softc {
 105         /* Generic device attributes */
 106         device_t sc_dev;
 107
 108 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
 109         /* Simple lock */
 110         struct simplelock sc_lock;
 111 #endif
 112
 113         /* Machine independent bus infrastructure */
 114         bus_space_tag_t sc_iot;
 115         bus_space_handle_t sc_ioh;
 116         bus_dma_tag_t sc_dmat;
 117         bus_dmamap_t sc_dmapt;
 118         bus_size_t sc_dma_maxsize;
 119
 120         /* Child device */
 121         device_t child;
 122
 123         /* Opaque handle used for interrupt handler establishment */
 124         void *sc_ieh;
 125
 126         /* List of soft interrupts to call */
 127         SLIST_HEAD(handler_list, pi1ppc_handler_node) sc_handler_listhead;
 128
 129          /* Input buffer: working pointers, and size in bytes. */
 130         char * sc_inb;
 131         char * sc_inbstart;
 132         u_int32_t sc_inb_nbytes;
 133         int sc_inerr;
 134
 135         /* Output buffer pointer, working pointer, and size in bytes. */
 136         char * sc_outb;
 137         char * sc_outbstart;
 138         u_int32_t sc_outb_nbytes;
 139         int sc_outerr;
 140
 141         /* DMA functions: setup by bus specific attach code */
 142         int (*sc_dma_start)(struct pi1ppc_softc *, void *, u_int, u_int8_t);
 143         int (*sc_dma_finish)(struct pi1ppc_softc *);
 144         int (*sc_dma_abort)(struct pi1ppc_softc *);
 145         int (*sc_dma_malloc)(device_t, void **, bus_addr_t *,
 146                 bus_size_t);
 147         void (*sc_dma_free)(device_t, void **, bus_addr_t *,
 148                 bus_size_t);
 149
 150         /* Microsequence related members */
 151         char * sc_ptr;          /* microseq current pointer */
 152         int sc_accum;           /* microseq accumulator */
 153
 154         /* Device attachment state */
 155 #define PI1PPC_ATTACHED 1
 156 #define PI1PPC_NOATTACH 0
 157         u_int8_t sc_dev_ok;
 158
 159         /*
 160          * Hardware capabilities flags: standard mode and nibble mode are
 161          * assumed to always be available since if they aren't you don't
 162          * HAVE a parallel port.
 163          */
 164 #define PI1PPC_HAS_INTR 0x01    /* Interrupt available */
 165 #define PI1PPC_HAS_DMA  0x02    /* DMA available */
 166 #define PI1PPC_HAS_FIFO 0x04    /* FIFO available */
 167 #define PI1PPC_HAS_PS2  0x08    /* PS2 mode capable */
 168         u_int8_t sc_has;        /* Chipset detected capabilities */
 169
 170         /* Flags specifying mode of chipset operation . */
 171 #define PI1PPC_MODE_STD 0x01    /* Use centronics-compatible mode */
 172 #define PI1PPC_MODE_PS2 0x02    /* Use PS2 mode */
 173 #define PI1PPC_MODE_NIBBLE 0x10 /* Use nibble mode */
 174         u_int8_t sc_mode;       /* Current operational mode */
 175
 176         /* Flags which further define chipset operation */
 177 #define PI1PPC_USE_INTR 0x01    /* Use interrupts */
 178 #define PI1PPC_USE_DMA  0x02    /* Use DMA */
 179         u_int8_t sc_use;        /* Capabilities to use */
 180
 181         /* Parallel Port Chipset model. */
 182 #define GENERIC         6
 183         u_int8_t sc_model;      /* chipset model */
 184
 185         /* EPP mode - UNUSED */
 186         u_int8_t sc_epp;
 187
 188         /* Parallel Port Chipset Type.  Only Indy-style needed? */
 189 #define PI1PPC_TYPE_INDY 0
 190         u_int8_t sc_type;
 191
 192         /* Stored register values after an interrupt occurs */
 193         u_int8_t sc_ecr_intr;
 194         u_int8_t sc_ctr_intr;
 195         u_int8_t sc_str_intr;
 196
 197 #define PI1PPC_IRQ_NONE 0x0
 198 #define PI1PPC_IRQ_nACK 0x1
 199 #define PI1PPC_IRQ_DMA  0x2
 200 #define PI1PPC_IRQ_FIFO 0x4
 201 #define PI1PPC_IRQ_nFAULT       0x8
 202         u_int8_t sc_irqstat;    /* Record irq settings */
 203
 204 #define PI1PPC_DMA_INIT         0x01
 205 #define PI1PPC_DMA_STARTED      0x02
 206 #define PI1PPC_DMA_COMPLETE     0x03
 207 #define PI1PPC_DMA_INTERRUPTED  0x04
 208 #define PI1PPC_DMA_ERROR                0x05
 209         u_int8_t sc_dmastat;    /* Record dma state */
 210
 211 #define PI1PPC_PWORD_MASK       0x30
 212 #define PI1PPC_PWORD_16 0x00
 213 #define PI1PPC_PWORD_8  0x10
 214 #define PI1PPC_PWORD_32 0x20
 215         u_int8_t sc_pword;      /* PWord size: used for FIFO DMA transfers */
 216         u_int8_t sc_fifo;       /* FIFO size */
 217
 218         /* Indicates number of PWords in FIFO queues that generate interrupt */
 219         u_int8_t sc_wthr;       /* writeIntrThresold */
 220         u_int8_t sc_rthr;       /* readIntrThresold */
 221 };
 222
 223
 224
 225 #ifdef _KERNEL
 226
 227 /* Function prototypes */
 228
 229 /* Soft config attach/detach routines */
 230 void pi1ppc_sc_attach(struct pi1ppc_softc *);
 231 int pi1ppc_sc_detach(struct pi1ppc_softc *, int);
 232
 233 /* Detection routines */
 234 int pi1ppc_detect_port(bus_space_tag_t, bus_space_handle_t);
 235
 236 /* Interrupt handler for pi1ppc device */
 237 int pi1ppcintr(void *);
 238
 239 #endif /* _KERNEL */
 240
 241 #endif /* __PI1PPCVAR_H */