sys/arch/sh3/include/cache.h

   1 /*      $NetBSD: cache.h,v 1.8 2006/09/24 00:43:44 tsutsui Exp $        */
   2
   3 /*-
   4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by UCHIYAMA Yasushi.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Cache configurations.
  34  *
  35  * SH3 I/D unified virtual-index physical-tag cache.
  36  * SH4 I/D separated virtual-index physical-tag cache.
  37  *
  38  *
  39  *         size       line-size entry way type
  40  * SH7708  4/8K       16B       128   2/4 P0,P2,U0 [1]
  41  *                                        P1 [2]
  42  * SH7709  4/8K       16B       128   2/4 [1]
  43  * SH7709A 16K        16B       256   4   [1]
  44  *
  45  * SH7750  I$  D$     line-size entry way
  46  *         8K  8/16K  32B       256   1   [1]
  47  * SH7750
  48  * SH7750S
  49  * SH7751  I$  D$     line-size entry way
  50  *         8K  8/16K  32B       256   1   [1]
  51  *
  52  * SH7750R
  53  * SH7751R I$  D$     line-size entry way
  54  *         16K 16/32K 32B       512   2   [1]
  55  *
  56  * [1]  write-through/back selectable
  57  * [2]  write-through only
  58  *
  59  * Cache operations.
  60  *
  61  * There are some rules that must be followed:
  62  *
  63  *      I-cache Synch (all or range):
  64  *              The goal is to synchronize the instruction stream,
  65  *              so you may need to write-back dirty data cache
  66  *              blocks first.  If a range is requested, and you
  67  *              can't synchronize just a range, you have to hit
  68  *              the whole thing.
  69  *
  70  *      D-cache Write-back Invalidate range:
  71  *              If you can't WB-Inv a range, you must WB-Inv the
  72  *              entire D-cache.
  73  *
  74  *      D-cache Invalidate:
  75  *              If you can't Inv the D-cache without doing a
  76  *              Write-back, YOU MUST PANIC.  This is to catch
  77  *              errors in calling code.  Callers must be aware
  78  *              of this scenario, and must handle it appropriately
  79  *              (consider the bus_dma(9) operations).
  80  *
  81  *      D-cache Write-back:
  82  *              If you can't Write-back without doing an invalidate,
  83  *              that's fine.  Then treat this as a WB-Inv.  Skipping
  84  *              the invalidate is merely an optimization.
  85  *
  86  *      All operations:
  87  *              Valid virtual addresses must be passed to the
  88  *              cache operation.
  89  *
  90  *
  91  *      sh_icache_sync_all      Synchronize I-cache
  92  *
  93  *      sh_icache_sync_range    Synchronize I-cache range
  94  *
  95  *      sh_icache_sync_range_index (index ops)
  96  *
  97  *      sh_dcache_wbinv_all     Write-back Invalidate D-cache
  98  *
  99  *      sh_dcache_wbinv_range   Write-back Invalidate D-cache range
 100  *
 101  *      sh_dcache_wbinv_range_index (index ops)
 102  *
 103  *      sh_dcache_inv_range     Invalidate D-cache range
 104  *
 105  *      sh_dcache_wb_range      Write-back D-cache range
 106  *
 107  *      If I/D unified cache (SH3), I-cache ops are writeback invalidate
 108  *      operation.
 109  *      If write-through mode, sh_dcache_wb_range is no-operation.
 110  *
 111  */
 112
 113 #ifndef _SH3_CACHE_H_
 114 #define _SH3_CACHE_H_
 115
 116 #ifdef _KERNEL
 117 struct sh_cache_ops {
 118         void (*_icache_sync_all)(void);
 119         void (*_icache_sync_range)(vaddr_t, vsize_t);
 120         void (*_icache_sync_range_index)(vaddr_t, vsize_t);
 121
 122         void (*_dcache_wbinv_all)(void);
 123         void (*_dcache_wbinv_range)(vaddr_t, vsize_t);
 124         void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t);
 125         void (*_dcache_inv_range)(vaddr_t, vsize_t);
 126         void (*_dcache_wb_range)(vaddr_t, vsize_t);
 127 };
 128
 129 /* Cache configurations */
 130 #define sh_cache_enable_unified         sh_cache_enable_icache
 131 extern int sh_cache_enable_icache;
 132 extern int sh_cache_enable_dcache;
 133 extern int sh_cache_write_through;
 134 extern int sh_cache_write_through_p0_u0_p3;
 135 extern int sh_cache_write_through_p1;
 136 extern int sh_cache_ways;
 137 extern int sh_cache_unified;
 138 #define sh_cache_size_unified           sh_cache_size_icache
 139 extern int sh_cache_size_icache;
 140 extern int sh_cache_size_dcache;
 141 extern int sh_cache_line_size;
 142 /* for n-way set associative cache */
 143 extern int sh_cache_way_size;
 144 extern int sh_cache_way_shift;
 145 extern int sh_cache_entry_mask;
 146
 147 /* Special mode */
 148 extern int sh_cache_ram_mode;
 149 extern int sh_cache_index_mode_icache;
 150 extern int sh_cache_index_mode_dcache;
 151
 152 extern int sh_cache_alias_mask;
 153 #define sh_cache_indexof(x)     (sh_cache_alias_mask & (x))
 154 extern int sh_cache_prefer_mask;
 155
 156 extern struct sh_cache_ops sh_cache_ops;
 157
 158 #define sh_icache_sync_all()                                            \
 159         (*sh_cache_ops._icache_sync_all)()
 160
 161 #define sh_icache_sync_range(v, s)                                      \
 162         (*sh_cache_ops._icache_sync_range)((v), (s))
 163
 164 #define sh_icache_sync_range_index(v, s)                                \
 165         (*sh_cache_ops._icache_sync_range_index)((v), (s))
 166
 167 #define sh_dcache_wbinv_all()                                           \
 168         (*sh_cache_ops._dcache_wbinv_all)()
 169
 170 #define sh_dcache_wbinv_range(v, s)                                     \
 171         (*sh_cache_ops._dcache_wbinv_range)((v), (s))
 172
 173 #define sh_dcache_wbinv_range_index(v, s)                               \
 174         (*sh_cache_ops._dcache_wbinv_range_index)((v), (s))
 175
 176 #define sh_dcache_inv_range(v, s)                                       \
 177         (*sh_cache_ops._dcache_inv_range)((v), (s))
 178
 179 #define sh_dcache_wb_range(v, s)                                        \
 180         (*sh_cache_ops._dcache_wb_range)((v), (s))
 181
 182 void sh_cache_init(void);
 183 void sh_cache_information(void);
 184
 185 #define SH_HAS_UNIFIED_CACHE    CPU_IS_SH3
 186 #define SH_HAS_VIRTUAL_ALIAS    CPU_IS_SH4
 187 #define SH_HAS_WRITEBACK_CACHE  (!sh_cache_write_through)
 188
 189 #endif /* _KERNEL */
 190 #endif /* _SH3_CACHE_H_ */