sys/arch/sh3/include/cpgreg.h

   1 /*      $NetBSD: cpgreg.h,v 1.4 2002/03/17 17:55:24 uch Exp $   */
   2
   3 /*-
   4  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef _SH3_CPGREG_H_
  30 #define _SH3_CPGREG_H_
  31
  32 /*
  33  * Clock Pulse Generator
  34  */
  35 #define SH3_FRQCR               0xffffff80      /* 16bit */
  36 #define SH4_FRQCR               0xffc00000      /* 16bit */
  37
  38 /*
  39  * Standby Control
  40  */
  41 #define SH3_STBCR               0xffffff82      /* 8bit */
  42 #define SH7709_STBCR2           0xffffff88      /* 8bit */
  43
  44 #define SH4_STBCR               0xffc00004      /* 8bit */
  45 #define SH4_STBCR2              0xffc00010      /* 8bit */
  46
  47 #endif /* !_SH3_CPGREG_H_ */