sys/arch/sh3/include/dacreg.h

   1 /*      $NetBSD: dacreg.h,v 1.1.4.3 2004/09/21 13:21:25 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 2003 Valeriy E. Ushakov
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 #ifndef _SH3_DACREG_H_
  31 #define _SH3_DACREG_H_
  32
  33 /* D/A data registers for channels 0 and 1 */
  34 #define SH7709_DADR0    0xa40000a0
  35 #define SH7709_DADR1    0xa40000a2
  36
  37 /* D/A control register */
  38 #define SH7709_DACR     0xa40000a4
  39
  40 #define SH7709_DACR_DAOE1       0x80 /* output enable for channel 1 */
  41 #define SH7709_DACR_DAOE0       0x40 /* output enable for channel 0 */
  42 #define SH7709_DACR_DAE         0x20 /* D/A enable */
  43
  44 #define SH7709_DACR_BITS        \
  45         "\177\020" "b\07DAOE1\0" "b\06DAOE0\0" "b\05DAE\0"
  46
  47 #endif /* _SH3_DACREG_H_ */