sys/arch/sh3/include/intcreg.h

   1 /*      $NetBSD: intcreg.h,v 1.6.12.4 2005/11/10 13:58:38 skrll Exp $   */
   2
   3 /*-
   4  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef _SH3_INTCREG_H_
  30 #define _SH3_INTCREG_H_
  31 #include <sh3/devreg.h>
  32
  33 /*
  34  * INTC
  35  */
  36 /* SH3 SH7708*, SH7709* common */
  37 #define SH3_ICR0                0xfffffee0      /* 16bit */
  38 #define SH3_IPRA                0xfffffee2      /* 16bit */
  39 #define SH3_IPRB                0xfffffee4      /* 16bit */
  40
  41 /* SH7709, SH7709A only */
  42 #define SH7709_ICR1             0xa4000010      /* 16bit */
  43 #define SH7709_ICR2             0xa4000012      /* 16bit */
  44 #define SH7709_PINTER           0xa4000014      /* 16bit */
  45 #define SH7709_IPRC             0xa4000016      /* 16bit */
  46 #define SH7709_IPRD             0xa4000018      /* 16bit */
  47 #define SH7709_IPRE             0xa400001a      /* 16bit */
  48 #define SH7709_IRR0             0xa4000004      /* 8bit */
  49 #define SH7709_IRR1             0xa4000006      /* 8bit */
  50 #define SH7709_IRR2             0xa4000008      /* 8bit */
  51
  52 #define IPRC_IRQ3_MASK          0xf000
  53 #define IPRC_IRQ2_MASK          0x0f00
  54 #define IPRC_IRQ1_MASK          0x00f0
  55 #define IPRC_IRQ0_MASK          0x000f
  56
  57 #define IPRD_PINT07_MASK        0xf000
  58 #define IPRD_PINT8F_MASK        0x0f00
  59 #define IPRD_IRQ5_MASK          0x00f0
  60 #define IPRD_IRQ4_MASK          0x000f
  61
  62 #define IPRE_DMAC_MASK          0xf000
  63 #define IPRE_IRDA_MASK          0x0f00
  64 #define IPRE_SCIF_MASK          0x00f0
  65 #define IPRE_ADC_MASK           0x000f
  66
  67 #define IRR0_PINT8F             0x80
  68 #define IRR0_PINT07             0x40
  69 #define IRR0_IRQ5               0x20
  70 #define IRR0_IRQ4               0x10
  71 #define IRR0_IRQ3               0x08
  72 #define IRR0_IRQ2               0x04
  73 #define IRR0_IRQ1               0x02
  74 #define IRR0_IRQ0               0x01
  75
  76
  77 /* SH4 */
  78 #define SH4_ICR                 0xffd00000      /* 16bit */
  79 #define SH4_IPRA                0xffd00004      /* 16bit */
  80 #define SH4_IPRB                0xffd00008      /* 16bit */
  81 #define SH4_IPRC                0xffd0000c      /* 16bit */
  82 #define SH4_IPRD                0xffd00010      /* 16bit */
  83 #define SH4_INTPRI00            0xfe080000      /* 32bit */
  84 #define SH4_INTREQ00            0xfe080020      /* 32bit */
  85 #define SH4_INTMSK00            0xfe080040      /* 32bit */
  86 #define SH4_INTMSKCLR00         0xfe080060      /* 32bit */
  87
  88 #define IPRC_GPIO_MASK          0xf000
  89 #define IPRC_DMAC_MASK          0x0f00
  90 #define IPRC_SCIF_MASK          0x00f0
  91 #define IPRC_HUDI_MASK          0x000f
  92
  93 #define IPRD_IRL0_MASK          0xf000
  94 #define IPRD_IRL1_MASK          0x0f00
  95 #define IPRD_IRL2_MASK          0x00f0
  96 #define IPRD_IRL3_MASK          0x000f
  97
  98 #define IPRA_TMU0_MASK          0xf000
  99 #define IPRA_TMU1_MASK          0x0f00
 100 #define IPRA_TMU2_MASK          0x00f0
 101 #define IPRA_RTC_MASK           0x000f
 102
 103 #define IPRB_WDT_MASK           0xf000
 104 #define IPRB_REF_MASK           0x0f00
 105 #define IPRB_SCI_MASK           0x00f0
 106
 107 #define INTPRI00_PCI0_MASK      0x0000000f
 108 #define INTPRI00_PCI1_MASK      0x000000f0
 109 #define INTPRI00_TMU3_MASK      0x00000f00
 110 #define INTPRI00_TMU4_MASK      0x0000f000
 111
 112 /* INTREQ/INTMSK/INTMSKCLR */
 113 #define INTREQ00_PCISERR        0x00000001
 114 #define INTREQ00_PCIDMA3        0x00000002
 115 #define INTREQ00_PCIDMA2        0x00000004
 116 #define INTREQ00_PCIDMA1        0x00000008
 117 #define INTREQ00_PCIDMA0        0x00000010
 118 #define INTREQ00_PCIPWON        0x00000020
 119 #define INTREQ00_PCIPWDWN       0x00000040
 120 #define INTREQ00_PCIERR         0x00000080
 121 #define INTREQ00_TUNI3          0x00000100
 122 #define INTREQ00_TUNI4          0x00000200
 123
 124 #define INTMSK00_MASK_ALL       0x000003ff
 125
 126 #endif /* !_SH3_INTCREG_H_ */