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[netbsd-mini2440.git] / sys / arch / sh3 / include / locore.h
blobcac4f73020c2b15c629eada2d3bd0b1fa62d3a0a
1 /* $NetBSD: locore.h,v 1.18 2008/05/31 22:45:32 uwe Exp $ */
2
3 /*-
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifdef _LOCORE
30
31 #if defined(SH3) && defined(SH4)
32 #define MOV(x, r) mov.l .L_/**/x, r; mov.l @r, r
33 #define REG_SYMBOL(x) .L_/**/x: .long _C_LABEL(__sh_/**/x)
34 #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(__sh_/**/x)
35 #elif defined(SH3)
36 #define MOV(x, r) mov.l .L_/**/x, r
37 #define REG_SYMBOL(x) .L_/**/x: .long SH3_/**/x
38 #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(sh3_/**/x)
39 #elif defined(SH4)
40 #define MOV(x, r) mov.l .L_/**/x, r
41 #define REG_SYMBOL(x) .L_/**/x: .long SH4_/**/x
42 #define FUNC_SYMBOL(x) .L_/**/x: .long _C_LABEL(sh4_/**/x)
43 #endif /* SH3 && SH4 */
44
45 /*
46 * BANK1 r6 contains current trapframe pointer.
47 * BANK1 r7 contains bottom address of lwp's kernel stack.
48 */
49 /*
50 * __EXCEPTION_ENTRY:
51 * + setup stack pointer
52 * + save all registers to trapframe.
53 * + setup kernel stack.
54 * + change bank from 1 to 0
55 * + set BANK0 (r4, r5, r6) = (ssr, spc, ssp)
56 */
57 #define __EXCEPTION_ENTRY ;\
58 /* Check kernel/user mode. */ ;\
59 mov #0x40, r3 ;\
60 swap.b r3, r3 ;\
61 stc ssr, r2 ;\
62 swap.w r3, r3 /* r3 = 0x40000000 */ ;\
63 mov r2, r0 /* r2 = r0 = SSR */ ;\
64 and r3, r0 ;\
65 tst r0, r0 /* if (SSR.MD == 0) T = 1 */ ;\
66 mov r14, r1 ;\
67 mov r6, r14 /* frame pointer */ ;\
68 bf/s 1f /* T==0 ...Exception from kernel mode */;\
69 mov r15, r0 ;\
70 /* Exception from user mode */ ;\
71 mov r7, r15 /* change to kernel stack */ ;\
72 1: ;\
73 /* Save registers */ ;\
74 mov.l r1, @-r14 /* tf_r14 */ ;\
75 mov.l r0, @-r14 /* tf_r15 */ ;\
76 stc.l r0_bank,@-r14 /* tf_r0 */ ;\
77 stc.l r1_bank,@-r14 /* tf_r1 */ ;\
78 stc.l r2_bank,@-r14 /* tf_r2 */ ;\
79 stc.l r3_bank,@-r14 /* tf_r3 */ ;\
80 stc.l r4_bank,@-r14 /* tf_r4 */ ;\
81 stc.l r5_bank,@-r14 /* tf_r5 */ ;\
82 stc.l r6_bank,@-r14 /* tf_r6 */ ;\
83 stc.l r7_bank,@-r14 /* tf_r7 */ ;\
84 mov.l r8, @-r14 /* tf_r8 */ ;\
85 mov.l r9, @-r14 /* tf_r9 */ ;\
86 mov.l r10, @-r14 /* tf_r10 */ ;\
87 mov.l r11, @-r14 /* tf_r11 */ ;\
88 mov.l r12, @-r14 /* tf_r12 */ ;\
89 mov.l r13, @-r14 /* tf_r13 */ ;\
90 sts.l pr, @-r14 /* tf_pr */ ;\
91 sts.l mach, @-r14 /* tf_mach*/ ;\
92 sts.l macl, @-r14 /* tf_macl*/ ;\
93 stc.l gbr, @-r14 /* tf_gbr */ ;\
94 mov.l r2, @-r14 /* tf_ssr */ ;\
95 stc.l spc, @-r14 /* tf_spc */ ;\
96 add #-8, r14 /* skip tf_ubc, tf_expevt */ ;\
97 mov r14, r6 /* store frame pointer */ ;\
98 /* Change register bank to 0 */ ;\
99 shlr r3 /* r3 = 0x20000000 */ ;\
100 stc sr, r1 /* r1 = SR */ ;\
101 not r3, r3 ;\
102 and r1, r3 ;\
103 ldc r3, sr /* SR.RB = 0 */ ;\
104 /* Set up arguments. r4 = ssr, r5 = spc */ ;\
105 stc r2_bank,r4 ;\
106 stc spc, r5
107
108 /*
109 * __EXCEPTION_RETURN:
110 * + block exceptions
111 * + restore all registers from stack.
112 * + rte.
113 */
114 #define __EXCEPTION_RETURN ;\
115 mov #0x10, r0 ;\
116 swap.b r0, r0 ;\
117 swap.w r0, r0 /* r0 = 0x10000000 */ ;\
118 stc sr, r1 ;\
119 or r0, r1 ;\
120 ldc r1, sr /* SR.BL = 1 */ ;\
121 stc r6_bank,r0 ;\
122 mov r0, r14 ;\
123 add #TF_SIZE, r0 ;\
124 ldc r0, r6_bank /* roll up frame pointer */ ;\
125 add #8, r14 /* skip tf_expevt, tf_ubc */ ;\
126 ldc.l @r14+, spc /* tf_spc */ ;\
127 ldc.l @r14+, ssr /* tf_ssr */ ;\
128 ldc.l @r14+, gbr /* tf_gbr */ ;\
129 lds.l @r14+, macl /* tf_macl*/ ;\
130 lds.l @r14+, mach /* tf_mach*/ ;\
131 lds.l @r14+, pr /* tf_pr */ ;\
132 mov.l @r14+, r13 /* tf_r13 */ ;\
133 mov.l @r14+, r12 /* tf_r12 */ ;\
134 mov.l @r14+, r11 /* tf_r11 */ ;\
135 mov.l @r14+, r10 /* tf_r10 */ ;\
136 mov.l @r14+, r9 /* tf_r9 */ ;\
137 mov.l @r14+, r8 /* tf_r8 */ ;\
138 mov.l @r14+, r7 /* tf_r7 */ ;\
139 mov.l @r14+, r6 /* tf_r6 */ ;\
140 mov.l @r14+, r5 /* tf_r5 */ ;\
141 mov.l @r14+, r4 /* tf_r4 */ ;\
142 mov.l @r14+, r3 /* tf_r3 */ ;\
143 mov.l @r14+, r2 /* tf_r2 */ ;\
144 mov.l @r14+, r1 /* tf_r1 */ ;\
145 mov.l @r14+, r0 /* tf_r0 */ ;\
146 mov.l @r14+ r15 /* tf_r15 */ ;\
147 mov.l @r14+, r14 /* tf_r14 */ ;\
148 rte ;\
149 nop
150
151
152 /*
153 * Macros to disable and enable exceptions (including interrupts).
154 * This modifies SR.BL
155 */
156
157 #define __EXCEPTION_BLOCK(Rn, Rm) ;\
158 mov #0x10, Rn ;\
159 swap.b Rn, Rn ;\
160 swap.w Rn, Rn /* Rn = 0x10000000 */ ;\
161 stc sr, Rm ;\
162 or Rm, Rn ;\
163 ldc Rn, sr /* block exceptions */
164
165 #define __EXCEPTION_UNBLOCK(Rn, Rm) ;\
166 mov #0xef, Rn /* ~0x10 */ ;\
167 swap.b Rn, Rn ;\
168 swap.w Rn, Rn /* Rn = ~0x10000000 */ ;\
169 stc sr, Rm ;\
170 and Rn, Rm ;\
171 ldc Rm, sr /* unblock exceptions */
172
173 /*
174 * Macros to disable and enable interrupts.
175 * This modifies SR.I[0-3]
176 */
177 #define __INTR_MASK(Rn, Rm) ;\
178 mov #0x78, Rn ;\
179 shll Rn /* Rn = 0x000000f0 */ ;\
180 stc sr, Rm ;\
181 or Rn, Rm ;\
182 ldc Rm, sr /* mask all interrupts */
183
184 #define __INTR_UNMASK(Rn, Rm) ;\
185 mov #0x78, Rn ;\
186 shll Rn /* Rn = 0x000000f0 */ ;\
187 not Rn, Rn ;\
188 stc sr, Rm ;\
189 and Rn, Rm ;\
190 ldc Rm, sr /* unmask all interrupts */
191
192 #else /* !_LOCORE */
193
194 void sh3_switch_setup(struct lwp *);
195 void sh4_switch_setup(struct lwp *);
196 void sh3_switch_resume(struct lwp *);
197 void sh4_switch_resume(struct lwp *);
198 extern void (*__sh_switch_resume)(struct lwp *);
199
200 #endif /* !_LOCORE */
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