sys/arch/sh3/include/pcicreg.h

   1 /*      $NetBSD: pcicreg.h,v 1.1.6.1 2005/11/10 13:58:38 skrll Exp $    */
   2
   3 /*-
   4  * Copyright (c) 2005 NONAKA Kimihiro
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _SH3_PCICREG_H__
  30 #define _SH3_PCICREG_H__
  31
  32 #include <sh3/devreg.h>
  33
  34 /*
  35  * PCI Controller
  36  */
  37
  38 #define SH4_PCIC                0xfe200000
  39
  40 #define SH4_PCIC_IO             0xfe240000
  41 #define SH4_PCIC_IO_SIZE        0x00040000
  42 #define SH4_PCIC_IO_MASK        (SH4_PCIC_IO_SIZE-1)
  43 #define SH4_PCIC_MEM            0xfd000000
  44 #define SH4_PCIC_MEM_SIZE       0x01000000
  45 #define SH4_PCIC_MEM_MASK       (SH4_PCIC_MEM_SIZE-1)
  46
  47 #define SH4_PCICONF     (SH4_PCIC+0x000)        /* 32bit */
  48 #define SH4_PCICONF0    (SH4_PCICONF+0x00)      /* 32bit */
  49 #define SH4_PCICONF1    (SH4_PCICONF+0x04)      /* 32bit */
  50 #define SH4_PCICONF2    (SH4_PCICONF+0x08)      /* 32bit */
  51 #define SH4_PCICONF3    (SH4_PCICONF+0x0c)      /* 32bit */
  52 #define SH4_PCICONF4    (SH4_PCICONF+0x10)      /* 32bit */
  53 #define SH4_PCICONF5    (SH4_PCICONF+0x14)      /* 32bit */
  54 #define SH4_PCICONF6    (SH4_PCICONF+0x18)      /* 32bit */
  55 #define SH4_PCICONF7    (SH4_PCICONF+0x1c)      /* 32bit */
  56 #define SH4_PCICONF8    (SH4_PCICONF+0x20)      /* 32bit */
  57 #define SH4_PCICONF9    (SH4_PCICONF+0x24)      /* 32bit */
  58 #define SH4_PCICONF10   (SH4_PCICONF+0x28)      /* 32bit */
  59 #define SH4_PCICONF11   (SH4_PCICONF+0x2c)      /* 32bit */
  60 #define SH4_PCICONF12   (SH4_PCICONF+0x30)      /* 32bit */
  61 #define SH4_PCICONF13   (SH4_PCICONF+0x34)      /* 32bit */
  62 #define SH4_PCICONF14   (SH4_PCICONF+0x38)      /* 32bit */
  63 #define SH4_PCICONF15   (SH4_PCICONF+0x3c)      /* 32bit */
  64 #define SH4_PCICONF16   (SH4_PCICONF+0x40)      /* 32bit */
  65 #define SH4_PCICONF17   (SH4_PCICONF+0x44)      /* 32bit */
  66 #define SH4_PCICR       (SH4_PCIC+0x100)        /* 32bit */
  67 #define SH4_PCILSR0     (SH4_PCIC+0x104)        /* 32bit */
  68 #define SH4_PCILSR1     (SH4_PCIC+0x108)        /* 32bit */
  69 #define SH4_PCILAR0     (SH4_PCIC+0x10c)        /* 32bit */
  70 #define SH4_PCILAR1     (SH4_PCIC+0x110)        /* 32bit */
  71 #define SH4_PCIINT      (SH4_PCIC+0x114)        /* 32bit */
  72 #define SH4_PCIINTM     (SH4_PCIC+0x118)        /* 32bit */
  73 #define SH4_PCIALR      (SH4_PCIC+0x11c)        /* 32bit */
  74 #define SH4_PCICLR      (SH4_PCIC+0x120)        /* 32bit */
  75 #define SH4_PCIAINT     (SH4_PCIC+0x130)        /* 32bit */
  76 #define SH4_PCIAINTM    (SH4_PCIC+0x134)        /* 32bit */
  77 #define SH4_PCIDMABT    (SH4_PCIC+0x140)        /* 32bit */
  78 #define SH4_PCIDPA0     (SH4_PCIC+0x180)        /* 32bit */
  79 #define SH4_PCIDLA0     (SH4_PCIC+0x184)        /* 32bit */
  80 #define SH4_PCIDTC0     (SH4_PCIC+0x188)        /* 32bit */
  81 #define SH4_PCIDCR0     (SH4_PCIC+0x18c)        /* 32bit */
  82 #define SH4_PCIDPA1     (SH4_PCIC+0x190)        /* 32bit */
  83 #define SH4_PCIDLA1     (SH4_PCIC+0x194)        /* 32bit */
  84 #define SH4_PCIDTC1     (SH4_PCIC+0x198)        /* 32bit */
  85 #define SH4_PCIDCR1     (SH4_PCIC+0x19c)        /* 32bit */
  86 #define SH4_PCIDPA2     (SH4_PCIC+0x1a0)        /* 32bit */
  87 #define SH4_PCIDLA2     (SH4_PCIC+0x1a4)        /* 32bit */
  88 #define SH4_PCIDTC2     (SH4_PCIC+0x1a8)        /* 32bit */
  89 #define SH4_PCIDCR2     (SH4_PCIC+0x1ac)        /* 32bit */
  90 #define SH4_PCIDPA3     (SH4_PCIC+0x1b0)        /* 32bit */
  91 #define SH4_PCIDLA3     (SH4_PCIC+0x1b4)        /* 32bit */
  92 #define SH4_PCIDTC3     (SH4_PCIC+0x1b8)        /* 32bit */
  93 #define SH4_PCIDCR3     (SH4_PCIC+0x1bc)        /* 32bit */
  94 #define SH4_PCIPAR      (SH4_PCIC+0x1c0)        /* 32bit */
  95 #define SH4_PCIMBR      (SH4_PCIC+0x1c4)        /* 32bit */
  96 #define SH4_PCIIOBR     (SH4_PCIC+0x1c8)        /* 32bit */
  97 #define SH4_PCIPINT     (SH4_PCIC+0x1cc)        /* 32bit */
  98 #define SH4_PCIPINTM    (SH4_PCIC+0x1d0)        /* 32bit */
  99 #define SH4_PCICLKR     (SH4_PCIC+0x1d4)        /* 32bit */
 100 #define SH4_PCIBCR1     (SH4_PCIC+0x1e0)        /* 32bit */
 101 #define SH4_PCIBCR2     (SH4_PCIC+0x1e4)        /* 32bit */
 102 #define SH4_PCIWCR1     (SH4_PCIC+0x1e8)        /* 32bit */
 103 #define SH4_PCIWCR2     (SH4_PCIC+0x1ec)        /* 32bit */
 104 #define SH4_PCIWCR3     (SH4_PCIC+0x1f0)        /* 32bit */
 105 #define SH4_PCIMCR      (SH4_PCIC+0x1f4)        /* 32bit */
 106 #define SH4_PCIBCR3     (SH4_PCIC+0x1f8)        /* 32bit: SH7751R */
 107 #define SH4_PCIPCTR     (SH4_PCIC+0x200)        /* 32bit */
 108 #define SH4_PCIPDTR     (SH4_PCIC+0x204)        /* 32bit */
 109 #define SH4_PCIPDR      (SH4_PCIC+0x220)        /* 32bit */
 110
 111 #define PCICR_BASE              0xa5000000
 112 #define PCICR_TRDSGL            0x00000200
 113 #define PCICR_BYTESWAP          0x00000100
 114 #define PCICR_PCIPUP            0x00000080
 115 #define PCICR_BMABT             0x00000040
 116 #define PCICR_MD10              0x00000020
 117 #define PCICR_MD9               0x00000010
 118 #define PCICR_SERR              0x00000008
 119 #define PCICR_INTA              0x00000004
 120 #define PCICR_RSTCTL            0x00000002
 121 #define PCICR_CFINIT            0x00000001
 122
 123 #define PCIINT_M_LOCKON         0x00008000
 124 #define PCIINT_T_TGT_ABORT      0x00004000
 125 #define PCIINT_TGT_RETRY        0x00000200
 126 #define PCIINT_MST_DIS          0x00000100
 127 #define PCIINT_ADRPERR          0x00000080
 128 #define PCIINT_SERR_DET         0x00000040
 129 #define PCIINT_T_DPERR_WT       0x00000020
 130 #define PCIINT_T_PERR_DET       0x00000010
 131 #define PCIINT_M_TGT_ABORT      0x00000008
 132 #define PCIINT_M_MST_ABORT      0x00000004
 133 #define PCIINT_M_DPERR_WT       0x00000002
 134 #define PCIINT_M_DPERR_RD       0x00000001
 135 #define PCIINT_ALL              0x0000c3ff
 136 #define PCIINT_CLEAR_ALL        PCIINT_ALL
 137
 138 #define PCIINTM_MASK_ALL        0x00000000
 139 #define PCIINTM_UNMASK_ALL      PCIINT_ALL
 140
 141 #define PCIMBR_MASK             0xff000000
 142
 143 #define PCIIOBR_MASK            0xffc00000
 144
 145 #endif  /* _SH3_PCICREG_H__ */