1 /* $NetBSD: intr.h,v 1.10 2007/12/03 15:34:21 ad Exp $ */
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * Device class interrupt levels
34 * Note: sun4 and sun4c hardware only has software interrupt available
35 * on level 1, 4 or 6. This limits the choice of the various
36 * IPL_SOFT* symbols to one of those three values.
38 #define IPL_NONE 0 /* nothing */
39 #define IPL_SOFTCLOCK 1 /* timeouts */
40 #define IPL_SOFTNET 1 /* protocol stack */
41 #define IPL_SOFTBIO 1 /* block I/O */
42 #define IPL_SOFTAUDIO 4 /* second-level audio */
43 #define IPL_SOFTFDC 4 /* second-level floppy */
44 #define IPL_SOFTSERIAL 6 /* serial */
45 #define IPL_VM 7 /* memory allocation */
46 #define IPL_SCHED 11 /* scheduler */
47 #define IPL_HIGH 15 /* everything */
50 * fd hardware, ts102, and tadpole microcontoller interrupts are at level 11
53 #define IPL_FD IPL_SCHED
54 #define IPL_TS102 IPL_SCHED
57 * zs hardware interrupts are at level 12
58 * su (com) hardware interrupts are at level 13
59 * IPL_SERIAL must protect them all.
62 #define IPL_ZS IPL_HIGH
64 #if defined(_KERNEL) && !defined(_LOCORE)
66 sparc_softintr_establish(int level
, void (*fun
)(void *), void *arg
);
69 sparc_softintr_disestablish(void *cookie
);
72 * NB that sparc_softintr_schedule() casts the cookie to an int *.
73 * This is to get the sic_pilreq member of the softintr_cookie
74 * structure, which is otherwise internal to intr.c.
76 #if defined(SUN4M) || defined(SUN4D)
77 extern void raise(int, int);
78 #if !(defined(SUN4) || defined(SUN4C))
79 #define sparc_softintr_schedule(cookie) raise(0, *((int *) (cookie)))
80 #else /* both defined */
81 #define sparc_softintr_schedule(cookie) do { \
82 if (CPU_ISSUN4M || CPU_ISSUN4D) \
83 raise(0, *((int *)(cookie))); \
85 ienab_bis(*((int *)(cookie))); \
87 #endif /* SUN4 || SUN4C */
88 #else /* SUN4M || SUN4D */
89 #define sparc_softintr_schedule(cookie) ienab_bis(*((int *) (cookie)))
90 #endif /* SUN4M || SUN4D */
93 void sparc_softintr_schedule(void *cookie
);
95 #endif /* KERNEL && !_LOCORE */