sys/arch/sparc/include/pte.h

   1 /*      $NetBSD: pte.h,v 1.30 2005/12/24 20:07:32 perry Exp $ */
   2
   3 /*
   4  * Copyright (c) 1996
   5  *      The President and Fellows of Harvard College. All rights reserved.
   6  * Copyright (c) 1992, 1993
   7  *      The Regents of the University of California.  All rights reserved.
   8  *
   9  * This software was developed by the Computer Systems Engineering group
  10  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  11  * contributed to Berkeley.
  12  *
  13  * All advertising materials mentioning features or use of this software
  14  * must display the following acknowledgements:
  15  *      This product includes software developed by Harvard University.
  16  *      This product includes software developed by the University of
  17  *      California, Lawrence Berkeley Laboratory.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions
  21  * are met:
  22  * 1. Redistributions of source code must retain the above copyright
  23  *    notice, this list of conditions and the following disclaimer.
  24  * 2. Redistributions in binary form must reproduce the above copyright
  25  *    notice, this list of conditions and the following disclaimer in the
  26  *    documentation and/or other materials provided with the distribution.
  27  * 3. All advertising materials mentioning features or use of this software
  28  *    must display the following acknowledgements:
  29  *      This product includes software developed by Harvard University.
  30  *      This product includes software developed by the University of
  31  *      California, Berkeley and its contributors.
  32  * 4. Neither the name of the University nor the names of its contributors
  33  *    may be used to endorse or promote products derived from this software
  34  *    without specific prior written permission.
  35  *
  36  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  37  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  38  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  39  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  40  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  41  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  42  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  43  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  44  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  45  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  46  * SUCH DAMAGE.
  47  *
  48  *      @(#)pte.h       8.1 (Berkeley) 6/11/93
  49  */
  50
  51 #ifndef _SPARC_PTE_H_
  52 #define _SPARC_PTE_H_
  53
  54 #if defined(_KERNEL_OPT)
  55 #include "opt_sparc_arch.h"
  56 #endif
  57
  58 /*
  59  * Sun-4 (sort of), 4c (SparcStation), and 4m Page Table Entries
  60  * (Sun calls them `Page Map Entries').
  61  */
  62
  63 #ifndef _LOCORE
  64 /*
  65  * Segment maps contain `pmeg' (Page Map Entry Group) numbers.
  66  * A PMEG is simply an index that names a group of 32 (sun4) or
  67  * 64 (sun4c) PTEs.
  68  * Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits
  69  * to hold the hardware MMU resource number.
  70  */
  71 typedef u_short pmeg_t;         /* 10 bits needed per Sun-4 segmap entry */
  72 /*
  73  * Region maps contain `smeg' (Segment Entry Group) numbers.
  74  * An SMEG is simply an index that names a group of 64 PMEGs.
  75  */
  76 typedef u_char smeg_t;          /* 8 bits needed per Sun-4 regmap entry */
  77 #endif
  78
  79 /*
  80  * Address translation works as follows:
  81  *
  82  * (for sun4c and 2-level sun4)
  83  *      1. test va<31:29> -- these must be 000 or 111 (or you get a fault)
  84  *      2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number;
  85  *         use this to index the segment maps, yielding a 7 or 9 bit value.
  86  * (for 3-level sun4)
  87  *      1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number;
  88  *         use this to index the region maps, yielding a 10 bit value.
  89  *      2. take the value from (1) above and concatenate va<17:12> to
  90  *         get a `segment map entry' index.  This gives a 9 bit value.
  91  * (for sun4c)
  92  *      3. take the value from (2) above and concatenate va<17:12> to
  93  *         get a `page map entry' index.  This gives a 32-bit PTE.
  94  * (for sun4)
  95  *      3. take the value from (2 or 3) above and concatenate va<17:13> to
  96  *         get a `page map entry' index.  This gives a 32-bit PTE.
  97  **
  98  * For sun4m:
  99  *      1. Use context_reg<3:0> to index the context table (located at
 100  *         (context_reg << 2) | ((ctx_tbl_ptr_reg >> 2) << 6) ). This
 101  *         gives a 32-bit page-table-descriptor (PTP).
 102  *      2. Use va<31:24> to index the region table located by the PTP from (1):
 103  *         PTP<31:6> << 10. This gives another PTP for the segment tables
 104  *      3. Use va<23:18> to index the segment table located by the PTP from (2)
 105  *         as follows: PTP<31:4> << 8. This gives another PTP for the page tbl.
 106  *      4. Use va<17:12> to index the page table given by (3)'s PTP:
 107  *         PTP<31:4> << 8. This gives a 32-bit PTE.
 108  *
 109  * In other words:
 110  *
 111  *      struct sun4_3_levelmmu_virtual_addr {
 112  *              u_int   va_reg:8,       (virtual region)
 113  *                      va_seg:6,       (virtual segment)
 114  *                      va_pg:5,        (virtual page within segment)
 115  *                      va_off:13;      (offset within page)
 116  *      };
 117  *      struct sun4_virtual_addr {
 118  *              u_int   :2,             (required to be the same as bit 29)
 119  *                      va_seg:12,      (virtual segment)
 120  *                      va_pg:5,        (virtual page within segment)
 121  *                      va_off:13;      (offset within page)
 122  *      };
 123  *      struct sun4c_virtual_addr {
 124  *              u_int   :2,             (required to be the same as bit 29)
 125  *                      va_seg:12,      (virtual segment)
 126  *                      va_pg:6,        (virtual page within segment)
 127  *                      va_off:12;      (offset within page)
 128  *      };
 129  *
 130  *      struct sun4m_virtual_addr {
 131  *              u_int   va_reg:8,       (virtual region)
 132  *                      va_seg:6,       (virtual segment within region)
 133  *                      va_pg:6,        (virtual page within segment)
 134  *                      va_off:12;      (offset within page)
 135  *      };
 136  *
 137  * Then, given any `va':
 138  *
 139  *      extern smeg_t regmap[16][1<<8];         (3-level MMU only)
 140  *      extern pmeg_t segmap[8][1<<12];         ([16][1<<12] for sun4)
 141  *      extern int ptetable[128][1<<6];         ([512][1<<5] for sun4)
 142  *
 143  *      extern u_int  s4m_ctxmap[16];           (sun4m SRMMU only)
 144  *      extern u_int  s4m_regmap[16][1<<8];     (sun4m SRMMU only)
 145  *      extern u_int  s4m_segmap[1<<8][1<<6];   (sun4m SRMMU only)
 146  *      extern u_int  s4m_pagmap[1<<14][1<<6];  (sun4m SRMMU only)
 147  *
 148  * (the above being in the hardware, accessed as Alternate Address Spaces on
 149  *  all machines but the Sun4m SRMMU, in which case the tables are in physical
 150  *  kernel memory. In the 4m architecture, the tables are not layed out as
 151  *  2-dim arrays, but are sparsely allocated as needed, and point to each
 152  *  other.)
 153  *
 154  *      if (cputyp==CPU_SUN4M || cputyp==CPU_SUN4D) // SPARC Reference MMU
 155  *              regptp = s4m_ctxmap[curr_ctx];
 156  *              if (!(regptp & SRMMU_TEPTD)) TRAP();
 157  *              segptp = *(u_int *)(((regptp & ~0x3) << 4) | va.va_reg);
 158  *              if (!(segptp & SRMMU_TEPTD)) TRAP();
 159  *              pagptp = *(u_int *)(((segptp & ~0x3) << 4) | va.va_seg);
 160  *              if (!(pagptp & SRMMU_TEPTD)) TRAP();
 161  *              pte = *(u_int *)(((pagptp & ~0x3) << 4) | va.va_pg);
 162  *              if (!(pte & SRMMU_TEPTE)) TRAP();       // like PG_V
 163  *              if (usermode && PTE_PROT_LEVEL(pte) > 0x5) TRAP();
 164  *              if (writing && !PTE_PROT_LEVEL_ALLOWS_WRITING(pte)) TRAP();
 165  *              if (!(pte & SRMMU_PG_C)) DO_NOT_USE_CACHE_FOR_THIS_ACCESS();
 166  *              pte |= SRMMU_PG_U;
 167  *              if (writing) pte |= PG_M;
 168  *              physaddr = ((pte & SRMMU_PG_PFNUM) << SRMMU_PGSHIFT)|va.va_off;
 169  *              return;
 170  *      if (mmu_3l)
 171  *              physreg = regmap[curr_ctx][va.va_reg];
 172  *              physseg = segmap[physreg][va.va_seg];
 173  *      else
 174  *              physseg = segmap[curr_ctx][va.va_seg];
 175  *      pte = ptetable[physseg][va.va_pg];
 176  *      if (!(pte & PG_V)) TRAP();
 177  *      if (writing && !pte.pg_w) TRAP();
 178  *      if (usermode && pte.pg_s) TRAP();
 179  *      if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS();
 180  *      pte |= PG_U;                                    (mark used/accessed)
 181  *      if (writing) pte |= PG_M;                       (mark modified)
 182  *      ptetable[physseg][va.va_pg] = pte;
 183  *      physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off;
 184  */
 185
 186 #if defined(SUN4_MMU3L) && !defined(SUN4)
 187 #error "configuration error"
 188 #endif
 189
 190 #define NBPRG   (1 << 24)       /* bytes per region */
 191 #define RGSHIFT 24              /* log2(NBPRG) */
 192 #define RGOFSET (NBPRG - 1)     /* mask for region offset */
 193 #define NSEGRG  (NBPRG / NBPSG) /* segments per region */
 194
 195 #define NBPSG   (1 << 18)       /* bytes per segment */
 196 #define SGSHIFT 18              /* log2(NBPSG) */
 197 #define SGOFSET (NBPSG - 1)     /* mask for segment offset */
 198
 199 /* number of PTEs that map one segment (not number that fit in one segment!) */
 200 #if defined(SUN4) && (defined(SUN4C) || defined(SUN4M) || defined(SUN4D))
 201 extern int nptesg;
 202 #define NPTESG  nptesg          /* (which someone will have to initialize) */
 203 #else
 204 #define NPTESG  (NBPSG / NBPG)
 205 #endif
 206
 207 /* virtual address to virtual region number */
 208 #define VA_VREG(va)     (((unsigned int)(va) >> RGSHIFT) & 255)
 209
 210 /* virtual address to virtual segment number */
 211 #define VA_VSEG(va)     (((unsigned int)(va) >> SGSHIFT) & 63)
 212
 213 /* virtual address to virtual page number, for Sun-4 and Sun-4c */
 214 #define VA_SUN4_VPG(va)         (((int)(va) >> 13) & 31)
 215 #define VA_SUN4C_VPG(va)        (((int)(va) >> 12) & 63)
 216 #define VA_SUN4M_VPG(va)        (((int)(va) >> 12) & 63)
 217 #define VA_VPG(va)      \
 218         (PGSHIFT==SUN4_PGSHIFT ? VA_SUN4_VPG(va) : VA_SUN4C_VPG(va))
 219
 220 /* virtual address to offset within page */
 221 #define VA_SUN4_OFF(va)         (((int)(va)) & 0x1FFF)
 222 #define VA_SUN4C_OFF(va)        (((int)(va)) & 0xFFF)
 223 #define VA_SUN4M_OFF(va)        (((int)(va)) & 0xFFF)
 224 #define VA_OFF(va)      \
 225         (PGSHIFT==SUN4_PGSHIFT ? VA_SUN4_OFF(va) : VA_SUN4C_OFF(va))
 226
 227
 228 /* truncate virtual address to region base */
 229 #define VA_ROUNDDOWNTOREG(va)   ((int)(va) & ~RGOFSET)
 230
 231 /* truncate virtual address to segment base */
 232 #define VA_ROUNDDOWNTOSEG(va)   ((int)(va) & ~SGOFSET)
 233
 234 /* virtual segment to virtual address (must sign extend on holy MMUs!) */
 235 #define VRTOVA(vr)      ((CPU_HAS_SRMMU || HASSUN4_MMU3L)       \
 236         ? ((int)(vr) << RGSHIFT)                                \
 237         : (((int)(vr) << (RGSHIFT+2)) >> 2))
 238 #define VSTOVA(vr,vs)   ((CPU_HAS_SRMMU || HASSUN4_MMU3L)       \
 239         ? (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT))     \
 240         : ((((int)(vr) << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT)))
 241
 242 extern int mmu_has_hole;
 243 #define VA_INHOLE(va)   (mmu_has_hole \
 244         ? ( (unsigned int)(((int)(va) >> PG_VSHIFT) + 1) > 1) \
 245         : 0)
 246
 247 /* Define the virtual address space hole */
 248 #define MMU_HOLE_START  0x20000000
 249 #define MMU_HOLE_END    0xe0000000
 250
 251 /* there is no `struct pte'; we just use `int'; this is for non-4M only */
 252 #define PG_V            0x80000000
 253 #define PG_PROT         0x60000000      /* both protection bits */
 254 #define PG_W            0x40000000      /* allowed to write */
 255 #define PG_S            0x20000000      /* supervisor only */
 256 #define PG_NC           0x10000000      /* non-cacheable */
 257 #define PG_TYPE         0x0c000000      /* both type bits */
 258
 259 #define PG_OBMEM        0x00000000      /* on board memory */
 260 #define PG_OBIO         0x04000000      /* on board I/O (incl. Sbus on 4c) */
 261 #define PG_VME16        0x08000000      /* 16-bit-data VME space */
 262 #define PG_VME32        0x0c000000      /* 32-bit-data VME space */
 263 #if defined(SUN4M) || defined(SUN4D)
 264 #define PG_SUN4M_OBMEM  0x0             /* No type bits=>obmem on 4m */
 265 #define PG_SUN4M_OBIO   0xf             /* obio maps to 0xf on 4M */
 266 #define SRMMU_PGTYPE    0xf0000000      /* Top 4 bits of pte PPN give type */
 267 #endif
 268
 269 #define PG_U            0x02000000
 270 #define PG_M            0x01000000
 271 #define PG_IOC          0x00800000
 272 #define PG_MBZ          0x00780000      /* unused; must be zero (oh really?) */
 273 #define PG_PFNUM        0x0007ffff      /* n.b.: only 16 bits on sun4c */
 274 #define PG_WIRED        0x00400000      /* S/W only; in MBZ area */
 275
 276 #define PG_TNC_SHIFT    26              /* shift to get PG_TYPE + PG_NC */
 277 #define PG_M_SHIFT      24              /* shift to get PG_M, PG_U */
 278 #define PG_M_SHIFT4M    5               /* shift to get SRMMU_PG_M,R on 4m */
 279 /*efine PG_NOACC        0               ** XXX */
 280 #define PG_KR           0x20000000
 281 #define PG_KW           0x60000000
 282 #define PG_URKR         0
 283 #define PG_UW           0x40000000
 284
 285 #ifdef KGDB
 286 /* but we will define one for gdb anyway */
 287 struct pte {
 288         u_int   pg_v:1,
 289                 pg_w:1,
 290                 pg_s:1,
 291                 pg_nc:1;
 292         enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2;
 293         u_int   pg_u:1,
 294                 pg_m:1,
 295                 pg_mbz:5,
 296                 pg_pfnum:19;
 297 };
 298 #if defined(SUN4M) || defined(SUN4D)
 299 struct srmmu_pte {
 300         u_int   pg_pfnum:20,
 301                 pg_c:1,
 302                 pg_m:1,
 303                 pg_u:1;
 304         enum pgprot { pprot_r_r, pprot_rw_rw, pprot_rx_rx, pprot_rwx_rwx,
 305                       pprot_x_x, pprot_r_rw, pprot_n_rx, pprot_n_rwx }
 306                 pg_prot:3;      /* prot. bits: pprot_<user>_<supervisor> */
 307         u_int   pg_must_be_2:2;
 308 };
 309 #endif
 310 #endif
 311
 312 /*
 313  * These are needed in the register window code
 314  * to check the validity of (ostensible) user stack PTEs.
 315  */
 316 #define PG_VSHIFT       29              /* (va>>vshift)==0 or -1 => valid */
 317         /* XXX fix this name, it is a va shift not a pte bit shift! */
 318
 319 #define PG_PROTSHIFT    29
 320 #define PG_PROTUWRITE   6               /* PG_V,PG_W,!PG_S */
 321 #define PG_PROTUREAD    4               /* PG_V,!PG_W,!PG_S */
 322
 323 /* %%%: Fix above and below for 4m? */
 324
 325 /* static __inline int PG_VALID(void *va) {
 326         register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1);
 327 } */
 328
 329
 330 /*
 331  * Here are the bit definitions for 4M/SRMMU pte's
 332  */
 333                 /* MMU TABLE ENTRIES */
 334 #define SRMMU_TEINVALID 0x0             /* invalid (serves as !valid bit) */
 335 #define SRMMU_TEPTD     0x1             /* Page Table Descriptor */
 336 #define SRMMU_TEPTE     0x2             /* Page Table Entry */
 337 #define SRMMU_TERES     0x3             /* reserved */
 338 #define SRMMU_TETYPE    0x3             /* mask for table entry type */
 339                 /* PTE FIELDS */
 340 #define SRMMU_PPNMASK   0xFFFFFF00
 341 #define SRMMU_PPNSHIFT  0x8
 342 #define SRMMU_PPNPASHIFT 0x4            /* shift to put ppn into PAddr */
 343 #define SRMMU_L1PPNSHFT 0x14
 344 #define SRMMU_L1PPNMASK 0xFFF00000
 345 #define SRMMU_L2PPNSHFT 0xE
 346 #define SRMMU_L2PPNMASK 0xFC000
 347 #define SRMMU_L3PPNSHFT 0x8
 348 #define SRMMU_L3PPNMASK 0x3F00
 349                 /* PTE BITS */
 350 #define SRMMU_PG_C      0x80            /* cacheable */
 351 #define SRMMU_PG_M      0x40            /* modified (dirty) */
 352 #define SRMMU_PG_R      0x20            /* referenced */
 353 #define SRMMU_PGBITSMSK 0xE0
 354                 /* PTE PROTECTION */
 355 #define SRMMU_PROT_MASK 0x1C            /* Mask protection bits out of pte */
 356 #define SRMMU_PROT_SHFT 0x2
 357 #define PPROT_R_R       0x0             /* These are in the form:       */
 358 #define PPROT_RW_RW     0x4             /*      PPROT_<u>_<s>           */
 359 #define PPROT_RX_RX     0x8             /* where <u> is the user-mode   */
 360 #define PPROT_RWX_RWX   0xC             /* permission, and <s> is the   */
 361 #define PPROT_X_X       0x10            /* supervisor mode permission.  */
 362 #define PPROT_R_RW      0x14            /* R=read, W=write, X=execute   */
 363 #define PPROT_N_RX      0x18            /* N=none.                      */
 364 #define PPROT_N_RWX     0x1C
 365 #define PPROT_WRITE     0x4             /* set iff write priv. allowed  */
 366 #define PPROT_S         0x18            /* effective S bit */
 367 #define PPROT_U2S_OMASK 0x18            /* OR with prot. to revoke user priv */
 368                 /* TABLE SIZES */
 369 #define SRMMU_L1SIZE    0x100
 370 #define SRMMU_L2SIZE    0x40
 371 #define SRMMU_L3SIZE    0x40
 372
 373 #define SRMMU_PTE_BITS  "\177\020"                                      \
 374         "f\0\2TYPE\0=\1PTD\0=\2PTE\0f\2\3PROT\0"                        \
 375         "=\0R_R\0=\4RW_RW\0=\10RX_RX\0=\14RWX_RWX\0=\20X_X\0=\24R_RW\0" \
 376         "=\30N_RX\0=\34N_RWX\0"                                         \
 377         "b\5R\0b\6M\0b\7C\0f\10\30PFN\0"
 378
 379 /*
 380  * IOMMU PTE bits.
 381  */
 382 #define IOPTE_PPN_MASK  0x07ffff00
 383 #define IOPTE_PPN_SHIFT 8
 384 #define IOPTE_RSVD      0x000000f1
 385 #define IOPTE_WRITE     0x00000004
 386 #define IOPTE_VALID     0x00000002
 387
 388 #define IOMMU_PTE_BITS  "\177\020"                                      \
 389         "f\10\23PPN\0b\2W\0b\1V\0"
 390
 391
 392 #if defined(_KERNEL) || defined(_STANDALONE)
 393 /*
 394  * Macros to get and set the processor context.
 395  */
 396 #define getcontext4()           lduba(AC_CONTEXT, ASI_CONTROL)
 397 #define getcontext4m()          lda(SRMMU_CXR, ASI_SRMMU)
 398 #define getcontext()            (CPU_HAS_SRMMU ? getcontext4m()         \
 399                                                : getcontext4())
 400
 401 #define setcontext4(c)          stba(AC_CONTEXT, ASI_CONTROL, c)
 402 #define setcontext4m(c)         sta(SRMMU_CXR, ASI_SRMMU, c)
 403 #define setcontext(c)           (CPU_HAS_SRMMU ? setcontext4m(c)        \
 404                                                : setcontext4(c))
 405
 406 /* sun4/sun4c access to MMU-resident PTEs */
 407 #define getpte4(va)             lda(va, ASI_PTE)
 408 #define setpte4(va, pte)        sta(va, ASI_PTE, pte)
 409
 410 /* sun4m TLB probe */
 411 #define getpte4m(va)            lda((va & 0xFFFFF000) | ASI_SRMMUFP_L3, \
 412                                     ASI_SRMMUFP)
 413
 414 #endif /* _KERNEL || _STANDALONE */
 415 #endif /* _SPARC_PTE_H_ */