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[netbsd-mini2440.git] / sys / arch / sparc64 / include / ctlreg.h
blob6c11e5b1c715f90ee85b3360a5f3472780839aea
1 /* $NetBSD: ctlreg.h,v 1.47 2009/12/05 07:58:57 nakayama Exp $ */
2
3 /*
4 * Copyright (c) 1996-2002 Eduardo Horvath
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
22 * SUCH DAMAGE.
23 *
24 */
25
26 #ifndef _SPARC_CTLREG_H_
27 #define _SPARC_CTLREG_H_
28
29 /*
30 * Sun 4u control registers. (includes address space definitions
31 * and some registers in control space).
32 */
33
34 /*
35 * The Alternate address spaces.
36 *
37 * 0x00-0x7f are privileged
38 * 0x80-0xff can be used by users
39 */
40
41 #define ASI_LITTLE 0x08 /* This bit should make an ASI little endian */
42
43 #define ASI_NUCLEUS 0x04 /* [4u] kernel address space */
44 #define ASI_NUCLEUS_LITTLE 0x0c /* [4u] kernel address space, little endian */
45
46 #define ASI_AS_IF_USER_PRIMARY 0x10 /* [4u] primary user address space */
47 #define ASI_AS_IF_USER_SECONDARY 0x11 /* [4u] secondary user address space */
48
49 #define ASI_PHYS_CACHED 0x14 /* [4u] MMU bypass to main memory */
50 #define ASI_PHYS_NON_CACHED 0x15 /* [4u] MMU bypass to I/O location */
51
52 #define ASI_AS_IF_USER_PRIMARY_LITTLE 0x18 /* [4u] primary user address space, little endian */
53 #define ASI_AS_IF_USER_SECONDARY_LITTLE 0x19 /* [4u] secondary user address space, little endian */
54
55 #define ASI_PHYS_CACHED_LITTLE 0x1c /* [4u] MMU bypass to main memory, little endian */
56 #define ASI_PHYS_NON_CACHED_LITTLE 0x1d /* [4u] MMU bypass to I/O location, little endian */
57
58 #define ASI_NUCLEUS_QUAD_LDD 0x24 /* [4u] use w/LDDA to load 128-bit item */
59 #define ASI_NUCLEUS_QUAD_LDD_LITTLE 0x2c /* [4u] use w/LDDA to load 128-bit item, little endian */
60
61 #define ASI_FLUSH_D_PAGE_PRIMARY 0x38 /* [4u] flush D-cache page using primary context */
62 #define ASI_FLUSH_D_PAGE_SECONDARY 0x39 /* [4u] flush D-cache page using secondary context */
63 #define ASI_FLUSH_D_CTX_PRIMARY 0x3a /* [4u] flush D-cache context using primary context */
64 #define ASI_FLUSH_D_CTX_SECONDARY 0x3b /* [4u] flush D-cache context using secondary context */
65
66 #define ASI_DCACHE_INVALIDATE 0x42 /* [III] invalidate D-cache */
67 #define ASI_DCACHE_UTAG 0x43 /* [III] diagnostic access to D-cache micro tag */
68 #define ASI_DCACHE_SNOOP_TAG 0x44 /* [III] diagnostic access to D-cache snoop tag RAM */
69
70 #define ASI_LSU_CONTROL_REGISTER 0x45 /* [4u] load/store unit control register */
71
72 #define ASI_DCACHE_DATA 0x46 /* [4u] diagnostic access to D-cache data RAM */
73 #define ASI_DCACHE_TAG 0x47 /* [4u] diagnostic access to D-cache tag RAM */
74
75 #define ASI_INTR_DISPATCH_STATUS 0x48 /* [4u] interrupt dispatch status register */
76 #define ASI_INTR_RECEIVE 0x49 /* [4u] interrupt receive status register */
77 #define ASI_MID_REG 0x4a /* [4u] hardware config and MID */
78 #define ASI_ERROR_EN_REG 0x4b /* [4u] asynchronous error enables */
79 #define ASI_AFSR 0x4c /* [4u] asynchronous fault status register */
80 #define ASI_AFAR 0x4d /* [4u] asynchronous fault address register */
81
82 #define ASI_ICACHE_DATA 0x66 /* [4u] diagnostic access to D-cache data RAM */
83 #define ASI_ICACHE_TAG 0x67 /* [4u] diagnostic access to D-cache tag RAM */
84 #define ASI_FLUSH_I_PAGE_PRIMARY 0x68 /* [4u] flush D-cache page using primary context */
85 #define ASI_FLUSH_I_PAGE_SECONDARY 0x69 /* [4u] flush D-cache page using secondary context */
86 #define ASI_FLUSH_I_CTX_PRIMARY 0x6a /* [4u] flush D-cache context using primary context */
87 #define ASI_FLUSH_I_CTX_SECONDARY 0x6b /* [4u] flush D-cache context using secondary context */
88
89 #define ASI_BLOCK_AS_IF_USER_PRIMARY 0x70 /* [4u] primary user address space, block loads/stores */
90 #define ASI_BLOCK_AS_IF_USER_SECONDARY 0x71 /* [4u] secondary user address space, block loads/stores */
91
92 #define ASI_ECACHE_DIAG 0x76 /* [4u] diag access to E-cache tag and data */
93 #define ASI_DATAPATH_ERR_REG_WRITE 0x77 /* [4u] ASI is reused */
94
95 #define ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 0x78 /* [4u] primary user address space, block loads/stores */
96 #define ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x79 /* [4u] secondary user address space, block loads/stores */
97
98 #define ASI_INTERRUPT_RECEIVE_DATA 0x7f /* [4u] interrupt receive data registers {0,1,2} */
99 #define ASI_DATAPATH_ERR_REG_READ 0x7f /* [4u] read access to datapath error registers (ASI reused) */
100
101 #define ASI_PRIMARY 0x80 /* [4u] primary address space */
102 #define ASI_SECONDARY 0x81 /* [4u] secondary address space */
103 #define ASI_PRIMARY_NOFAULT 0x82 /* [4u] primary address space, no fault */
104 #define ASI_SECONDARY_NOFAULT 0x83 /* [4u] secondary address space, no fault */
105
106 #define ASI_PRIMARY_LITTLE 0x88 /* [4u] primary address space, little endian */
107 #define ASI_SECONDARY_LITTLE 0x89 /* [4u] secondary address space, little endian */
108 #define ASI_PRIMARY_NOFAULT_LITTLE 0x8a /* [4u] primary address space, no fault, little endian */
109 #define ASI_SECONDARY_NOFAULT_LITTLE 0x8b /* [4u] secondary address space, no fault, little endian */
110
111 #define ASI_PST8_PRIMARY 0xc0 /* [VIS] Eight 8-bit partial store, primary */
112 #define ASI_PST8_SECONDARY 0xc1 /* [VIS] Eight 8-bit partial store, secondary */
113 #define ASI_PST16_PRIMARY 0xc2 /* [VIS] Four 16-bit partial store, primary */
114 #define ASI_PST16_SECONDARY 0xc3 /* [VIS] Fout 16-bit partial store, secondary */
115 #define ASI_PST32_PRIMARY 0xc4 /* [VIS] Two 32-bit partial store, primary */
116 #define ASI_PST32_SECONDARY 0xc5 /* [VIS] Two 32-bit partial store, secondary */
117
118 #define ASI_PST8_PRIMARY_LITTLE 0xc8 /* [VIS] Eight 8-bit partial store, primary, little endian */
119 #define ASI_PST8_SECONDARY_LITTLE 0xc9 /* [VIS] Eight 8-bit partial store, secondary, little endian */
120 #define ASI_PST16_PRIMARY_LITTLE 0xca /* [VIS] Four 16-bit partial store, primary, little endian */
121 #define ASI_PST16_SECONDARY_LITTLE 0xcb /* [VIS] Fout 16-bit partial store, secondary, little endian */
122 #define ASI_PST32_PRIMARY_LITTLE 0xcc /* [VIS] Two 32-bit partial store, primary, little endian */
123 #define ASI_PST32_SECONDARY_LITTLE 0xcd /* [VIS] Two 32-bit partial store, secondary, little endian */
124
125 #define ASI_FL8_PRIMARY 0xd0 /* [VIS] One 8-bit load/store floating, primary */
126 #define ASI_FL8_SECONDARY 0xd1 /* [VIS] One 8-bit load/store floating, secondary */
127 #define ASI_FL16_PRIMARY 0xd2 /* [VIS] One 16-bit load/store floating, primary */
128 #define ASI_FL16_SECONDARY 0xd3 /* [VIS] One 16-bit load/store floating, secondary */
129
130 #define ASI_FL8_PRIMARY_LITTLE 0xd8 /* [VIS] One 8-bit load/store floating, primary, little endian */
131 #define ASI_FL8_SECONDARY_LITTLE 0xd9 /* [VIS] One 8-bit load/store floating, secondary, little endian */
132 #define ASI_FL16_PRIMARY_LITTLE 0xda /* [VIS] One 16-bit load/store floating, primary, little endian */
133 #define ASI_FL16_SECONDARY_LITTLE 0xdb /* [VIS] One 16-bit load/store floating, secondary, little endian */
134
135 #define ASI_BLOCK_COMMIT_PRIMARY 0xe0 /* [4u] block store with commit, primary */
136 #define ASI_BLOCK_COMMIT_SECONDARY 0xe1 /* [4u] block store with commit, secondary */
137 #define ASI_BLOCK_PRIMARY 0xf0 /* [4u] block load/store, primary */
138 #define ASI_BLOCK_SECONDARY 0xf1 /* [4u] block load/store, secondary */
139 #define ASI_BLOCK_PRIMARY_LITTLE 0xf8 /* [4u] block load/store, primary, little endian */
140 #define ASI_BLOCK_SECONDARY_LITTLE 0xf9 /* [4u] block load/store, secondary, little endian */
141
142
143 /*
144 * These are the shorter names used by Solaris
145 */
146
147 #define ASI_N ASI_NUCLEUS
148 #define ASI_NL ASI_NUCLEUS_LITTLE
149 #define ASI_AIUP ASI_AS_IF_USER_PRIMARY
150 #define ASI_AIUS ASI_AS_IF_USER_SECONDARY
151 #define ASI_AIUPL ASI_AS_IF_USER_PRIMARY_LITTLE
152 #define ASI_AIUSL ASI_AS_IF_USER_SECONDARY_LITTLE
153 #define ASI_P ASI_PRIMARY
154 #define ASI_S ASI_SECONDARY
155 #define ASI_PNF ASI_PRIMARY_NOFAULT
156 #define ASI_SNF ASI_SECONDARY_NOFAULT
157 #define ASI_PL ASI_PRIMARY_LITTLE
158 #define ASI_SL ASI_SECONDARY_LITTLE
159 #define ASI_PNFL ASI_PRIMARY_NOFAULT_LITTLE
160 #define ASI_SNFL ASI_SECONDARY_NOFAULT_LITTLE
161 #define ASI_FL8_P ASI_FL8_PRIMARY
162 #define ASI_FL8_S ASI_FL8_SECONDARY
163 #define ASI_FL16_P ASI_FL16_PRIMARY
164 #define ASI_FL16_S ASI_FL16_SECONDARY
165 #define ASI_FL8_PL ASI_FL8_PRIMARY_LITTLE
166 #define ASI_FL8_SL ASI_FL8_SECONDARY_LITTLE
167 #define ASI_FL16_PL ASI_FL16_PRIMARY_LITTLE
168 #define ASI_FL16_SL ASI_FL16_SECONDARY_LITTLE
169 #define ASI_BLK_AIUP ASI_BLOCK_AS_IF_USER_PRIMARY
170 #define ASI_BLK_AIUPL ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
171 #define ASI_BLK_AIUS ASI_BLOCK_AS_IF_USER_SECONDARY
172 #define ASI_BLK_AIUSL ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
173 #define ASI_BLK_COMMIT_P ASI_BLOCK_COMMIT_PRIMARY
174 #define ASI_BLK_COMMIT_PRIMARY ASI_BLOCK_COMMIT_PRIMARY
175 #define ASI_BLK_COMMIT_S ASI_BLOCK_COMMIT_SECONDARY
176 #define ASI_BLK_COMMIT_SECONDARY ASI_BLOCK_COMMIT_SECONDARY
177 #define ASI_BLK_P ASI_BLOCK_PRIMARY
178 #define ASI_BLK_PL ASI_BLOCK_PRIMARY_LITTLE
179 #define ASI_BLK_S ASI_BLOCK_SECONDARY
180 #define ASI_BLK_SL ASI_BLOCK_SECONDARY_LITTLE
181
182 /* Alternative spellings */
183 #define ASI_PRIMARY_NO_FAULT ASI_PRIMARY_NOFAULT
184 #define ASI_PRIMARY_NO_FAULT_LITTLE ASI_PRIMARY_NOFAULT_LITTLE
185 #define ASI_SECONDARY_NO_FAULT ASI_SECONDARY_NOFAULT
186 #define ASI_SECONDARY_NO_FAULT_LITTLE ASI_SECONDARY_NOFAULT_LITTLE
187
188 #define PHYS_ASI(x) (((x) | 0x09) == 0x1d)
189 #define LITTLE_ASI(x) ((x) & ASI_LITTLE)
190
191 /*
192 * The following are 4u control registers
193 */
194
195 /* Get the CPU's UPAID */
196 #define UPA_CR_MID_SHIFT (17)
197 #define UPA_CR_MID_SIZE (5)
198 #define UPA_CR_MID_MASK \
199 (((1 << UPA_CR_MID_SIZE) - 1) << UPA_CR_MID_SHIFT)
200
201 #define UPA_CR_MID(x) (((x)>>UPA_CR_MID_SHIFT)&((1 << UPA_CR_MID_SIZE) - 1))
202
203 #ifdef _LOCORE
204
205 #define UPA_GET_MID(r1) \
206 ldxa [%g0] ASI_MID_REG, r1 ; \
207 srlx r1, UPA_CR_MID_SHIFT, r1 ; \
208 and r1, (1 << UPA_CR_MID_SIZE) - 1, r1
209
210 #else
211 #define CPU_UPAID UPA_CR_MID(ldxa(0, ASI_MID_REG))
212 #endif
213
214 /*
215 * [4u] MMU and Cache Control Register (MCCR)
216 * use ASI = 0x45
217 */
218 #define ASI_MCCR ASI_LSU_CONTROL_REGISTER
219 #define MCCR 0x00
220
221 /* MCCR Bits and their meanings */
222 #define MCCR_DMMU_EN 0x08
223 #define MCCR_IMMU_EN 0x04
224 #define MCCR_DCACHE_EN 0x02
225 #define MCCR_ICACHE_EN 0x01
226
227
228 /*
229 * MMU control registers
230 */
231
232 /* Choose an MMU */
233 #define ASI_DMMU 0x58
234 #define ASI_IMMU 0x50
235
236 /* Other assorted MMU ASIs */
237 #define ASI_IMMU_8KPTR 0x51
238 #define ASI_IMMU_64KPTR 0x52
239 #define ASI_IMMU_DATA_IN 0x54
240 #define ASI_IMMU_TLB_DATA 0x55
241 #define ASI_IMMU_TLB_TAG 0x56
242 #define ASI_DMMU_8KPTR 0x59
243 #define ASI_DMMU_64KPTR 0x5a
244 #define ASI_DMMU_DATA_IN 0x5c
245 #define ASI_DMMU_TLB_DATA 0x5d
246 #define ASI_DMMU_TLB_TAG 0x5e
247
248 /*
249 * The following are the control registers
250 * They work on both MMUs unless noted.
251 * III = cheetah only
252 *
253 * Register contents are defined later on individual registers.
254 */
255 #define TSB_TAG_TARGET 0x0
256 #define TLB_DATA_IN 0x0
257 #define CTX_PRIMARY 0x08 /* primary context -- DMMU only */
258 #define CTX_SECONDARY 0x10 /* secondary context -- DMMU only */
259 #define SFSR 0x18
260 #define SFAR 0x20 /* fault address -- DMMU only */
261 #define TSB 0x28
262 #define TLB_TAG_ACCESS 0x30
263 #define VIRTUAL_WATCHPOINT 0x38
264 #define PHYSICAL_WATCHPOINT 0x40
265 #define TSB_PEXT 0x48 /* III primary ext */
266 #define TSB_SEXT 0x50 /* III 2ndary ext -- DMMU only */
267 #define TSB_NEXT 0x58 /* III nucleus ext */
268
269 /* Tag Target bits */
270 #define TAG_TARGET_VA_MASK 0x03ffffffffffffffffLL
271 #define TAG_TARGET_VA(x) (((x)<<22)&TAG_TARGET_VA_MASK)
272 #define TAG_TARGET_CONTEXT(x) ((x)>>48)
273 #define TAG_TARGET(c,v) ((((uint64_t)c)<<48)|(((uint64_t)v)&TAG_TARGET_VA_MASK))
274
275 /* SFSR bits for both D_SFSR and I_SFSR */
276 #define SFSR_ASI(x) ((x)>>16)
277 #define SFSR_FT_VA_OOR_2 0x02000 /* IMMU: jumpl or return to unsupportd VA */
278 #define SFSR_FT_VA_OOR_1 0x01000 /* fault at unsupported VA */
279 #define SFSR_FT_NFO 0x00800 /* DMMU: Access to page marked NFO */
280 #define SFSR_ILL_ASI 0x00400 /* DMMU: Illegal (unsupported) ASI */
281 #define SFSR_FT_IO_ATOMIC 0x00200 /* DMMU: Atomic access to noncacheable page */
282 #define SFSR_FT_ILL_NF 0x00100 /* DMMU: NF load or flush to page marked E (has side effects) */
283 #define SFSR_FT_PRIV 0x00080 /* Privilege violation */
284 #define SFSR_FT_E 0x00040 /* DMUU: value of E bit associated address */
285 #define SFSR_CTXT(x) (((x)>>4)&0x3)
286 #define SFSR_CTXT_IS_PRIM(x) (SFSR_CTXT(x)==0x00)
287 #define SFSR_CTXT_IS_SECOND(x) (SFSR_CTXT(x)==0x01)
288 #define SFSR_CTXT_IS_NUCLEUS(x) (SFSR_CTXT(x)==0x02)
289 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */
290 #define SFSR_W 0x00004 /* DMMU: attempted write */
291 #define SFSR_OW 0x00002 /* Overwrite; prev vault was still valid */
292 #define SFSR_FV 0x00001 /* Fault is valid */
293 #define SFSR_FT (SFSR_FT_VA_OOR_2|SFSR_FT_VA_OOR_1|SFSR_FT_NFO| \
294 SFSR_ILL_ASI|SFSR_FT_IO_ATOMIC|SFSR_FT_ILL_NF|SFSR_FT_PRIV)
295
296 #define SFSR_BITS "\177\20" \
297 "f\20\30ASI\0" "b\16VAT\0" "b\15VAD\0" "b\14NFO\0" "b\13ASI\0" "b\12A\0" \
298 "b\11NF\0" "b\10PRIV\0" "b\7E\0" "b\6NUCLEUS\0" "b\5SECONDCTX\0" "b\4PRIV\0" \
299 "b\3W\0" "b\2OW\0" "b\1FV\0"
300
301 /* ASFR bits */
302 #define ASFR_ME 0x100000000LL
303 #define ASFR_PRIV 0x080000000LL
304 #define ASFR_ISAP 0x040000000LL
305 #define ASFR_ETP 0x020000000LL
306 #define ASFR_IVUE 0x010000000LL
307 #define ASFR_TO 0x008000000LL
308 #define ASFR_BERR 0x004000000LL
309 #define ASFR_LDP 0x002000000LL
310 #define ASFR_CP 0x001000000LL
311 #define ASFR_WP 0x000800000LL
312 #define ASFR_EDP 0x000400000LL
313 #define ASFR_UE 0x000200000LL
314 #define ASFR_CE 0x000100000LL
315 #define ASFR_ETS 0x0000f0000LL
316 #define ASFT_P_SYND 0x00000ffffLL
317
318 #define AFSR_BITS "\177\20" \
319 "b\40ME\0" "b\37PRIV\0" "b\36ISAP\0" "b\35ETP\0" \
320 "b\34IVUE\0" "b\33TO\0" "b\32BERR\0" "b\31LDP\0" \
321 "b\30CP\0" "b\27WP\0" "b\26EDP\0" "b\25UE\0" \
322 "b\24CE\0" "f\20\4ETS\0" "f\0\20P_SYND\0"
323
324 /*
325 * Here's the spitfire TSB control register bits.
326 *
327 * Each TSB entry is 16-bytes wide. The TSB must be size aligned
328 */
329 #define TSB_SIZE_512 0x0 /* 8kB, etc. */
330 #define TSB_SIZE_1K 0x01
331 #define TSB_SIZE_2K 0x02
332 #define TSB_SIZE_4K 0x03
333 #define TSB_SIZE_8K 0x04
334 #define TSB_SIZE_16K 0x05
335 #define TSB_SIZE_32K 0x06
336 #define TSB_SIZE_64K 0x07
337 #define TSB_SPLIT 0x1000
338 #define TSB_BASE 0xffffffffffffe000
339
340 /* TLB Tag Access bits */
341 #define TLB_TAG_ACCESS_VA 0xffffffffffffe000
342 #define TLB_TAG_ACCESS_CTX 0x0000000000001fff
343
344 /*
345 * TLB demap registers. TTEs are defined in v9pte.h
346 *
347 * Use the address space to select between IMMU and DMMU.
348 * The address of the register selects which context register
349 * to read the ASI from.
350 *
351 * The data stored in the register is interpreted as the VA to
352 * use. The DEMAP_CTX_<> registers ignore the address and demap the
353 * entire ASI.
354 *
355 */
356 #define ASI_IMMU_DEMAP 0x57 /* [4u] IMMU TLB demap */
357 #define ASI_DMMU_DEMAP 0x5f /* [4u] IMMU TLB demap */
358
359 #define DEMAP_PAGE_NUCLEUS ((0x02)<<4) /* Demap page from kernel AS */
360 #define DEMAP_PAGE_PRIMARY ((0x00)<<4) /* Demap a page from primary CTXT */
361 #define DEMAP_PAGE_SECONDARY ((0x01)<<4) /* Demap page from secondary CTXT (DMMU only) */
362 #define DEMAP_CTX_NUCLEUS ((0x06)<<4) /* Demap all of kernel CTXT */
363 #define DEMAP_CTX_PRIMARY ((0x04)<<4) /* Demap all of primary CTXT */
364 #define DEMAP_CTX_SECONDARY ((0x05)<<4) /* Demap all of secondary CTXT */
365
366 /*
367 * Interrupt registers. This really gets hairy.
368 */
369
370 /* IRSR -- Interrupt Receive Status Ragister */
371 #define ASI_IRSR 0x49
372 #define IRSR 0x00
373 #define IRSR_BUSY 0x020
374 #define IRSR_MID(x) (x&0x1f)
375
376 /* IRDR -- Interrupt Receive Data Registers */
377 #define ASI_IRDR 0x7f
378 #define IRDR_0H 0x40
379 #define IRDR_0L 0x48 /* unimplemented */
380 #define IRDR_1H 0x50
381 #define IRDR_1L 0x58 /* unimplemented */
382 #define IRDR_2H 0x60
383 #define IRDR_2L 0x68 /* unimplemented */
384 #define IRDR_3H 0x70 /* unimplemented */
385 #define IRDR_3L 0x78 /* unimplemented */
386
387 /* SOFTINT ASRs */
388 #define SET_SOFTINT %asr20 /* Sets these bits */
389 #define CLEAR_SOFTINT %asr21 /* Clears these bits */
390 #define SOFTINT %asr22 /* Reads the register */
391 #define TICK_CMPR %asr23
392
393 #define TICK_INT 0x01 /* level-14 clock tick */
394 #define SOFTINT1 (0x1<<1)
395 #define SOFTINT2 (0x1<<2)
396 #define SOFTINT3 (0x1<<3)
397 #define SOFTINT4 (0x1<<4)
398 #define SOFTINT5 (0x1<<5)
399 #define SOFTINT6 (0x1<<6)
400 #define SOFTINT7 (0x1<<7)
401 #define SOFTINT8 (0x1<<8)
402 #define SOFTINT9 (0x1<<9)
403 #define SOFTINT10 (0x1<<10)
404 #define SOFTINT11 (0x1<<11)
405 #define SOFTINT12 (0x1<<12)
406 #define SOFTINT13 (0x1<<13)
407 #define SOFTINT14 (0x1<<14)
408 #define SOFTINT15 (0x1<<15)
409
410 /* Interrupt Dispatch -- usually reserved for cross-calls */
411 #define ASR_IDSR 0x48 /* Interrupt dispatch status reg */
412 #define IDSR 0x00
413 #define IDSR_NACK 0x02
414 #define IDSR_BUSY 0x01
415
416 #define ASI_INTERRUPT_DISPATCH 0x77 /* [4u] spitfire interrupt dispatch regs */
417
418 /* Interrupt delivery initiation */
419 #define IDCR(x) ((((uint64_t)(x)) << 14) | 0x70)
420
421 #define IDDR_0H 0x40 /* Store data to send in these regs */
422 #define IDDR_0L 0x48 /* unimplemented */
423 #define IDDR_1H 0x50
424 #define IDDR_1L 0x58 /* unimplemented */
425 #define IDDR_2H 0x60
426 #define IDDR_2L 0x68 /* unimplemented */
427 #define IDDR_3H 0x70 /* unimplemented */
428 #define IDDR_3L 0x78 /* unimplemented */
429
430 /*
431 * Error registers
432 */
433
434 /* Since we won't try to fix async errs, we don't care about the bits in the regs */
435 #define ASI_AFAR 0x4d /* Asynchronous fault address register */
436 #define AFAR 0x00
437 #define ASI_AFSR 0x4c /* Asynchronous fault status register */
438 #define AFSR 0x00
439
440 #define ASI_P_EER 0x4b /* Error enable register */
441 #define P_EER 0x00
442 #define P_EER_ISAPEN 0x04 /* Enable fatal on ISAP */
443 #define P_EER_NCEEN 0x02 /* Enable trap on uncorrectable errs */
444 #define P_EER_CEEN 0x01 /* Enable trap on correctable errs */
445
446 #define ASI_DATAPATH_READ 0x7f /* Read the regs */
447 #define ASI_DATAPATH_WRITE 0x77 /* Write to the regs */
448 #define P_DPER_0 0x00 /* Datapath err reg 0 */
449 #define P_DPER_1 0x18 /* Datapath err reg 1 */
450 #define P_DCR_0 0x20 /* Datapath control reg 0 */
451 #define P_DCR_1 0x38 /* Datapath control reg 0 */
452
453
454 /* From sparc64/asm.h which I think I'll deprecate since it makes bus.h a pain. */
455
456 #ifndef _LOCORE
457 /*
458 * GCC __asm constructs for doing assembly stuff.
459 */
460
461 /*
462 * ``Routines'' to load and store from/to alternate address space.
463 * The location can be a variable, the asi value (address space indicator)
464 * must be a constant.
465 *
466 * N.B.: You can put as many special functions here as you like, since
467 * they cost no kernel space or time if they are not used.
468 *
469 * These were static inline functions, but gcc screws up the constraints
470 * on the address space identifiers (the "n"umeric value part) because
471 * it inlines too late, so we have to use the funny valued-macro syntax.
472 */
473
474 /*
475 * Apparently the definition of bypass ASIs is that they all use the
476 * D$ so we need to flush the D$ to make sure we don't get data pollution.
477 */
478
479 #ifdef __arch64__
480
481 /* 64-bit kernel, non-constant */
482 #define SPARC64_LD_NONCONST(ld) \
483 __asm volatile( \
484 "wr %2,%%g0,%%asi; " \
485 #ld " [%1]%%asi,%0 " \
486 : "=r" (_v) \
487 : "r" ((__uintptr_t)(loc)), "r" (asi))
488
489 #if defined(__GNUC__) && defined(__OPTIMIZE__)
490 #define SPARC64_LD_DEF(ld, type, vtype) \
491 static __inline type ld(paddr_t loc, int asi) \
492 { \
493 vtype _v; \
494 if (__builtin_constant_p(asi)) \
495 __asm volatile( \
496 #ld " [%1]%2,%0 " \
497 : "=r" (_v) \
498 : "r" ((__uintptr_t)(loc)), "n" (asi)); \
499 else \
500 SPARC64_LD_NONCONST(ld); \
501 return _v; \
502 }
503 #else
504 #define SPARC64_LD_DEF(ld, type, vtype) \
505 static __inline type ld(paddr_t loc, int asi) \
506 { \
507 vtype _v; \
508 SPARC64_LD_NONCONST(ld); \
509 return _v; \
510 }
511 #endif
512 #define SPARC64_LD_DEF64(ld, type) SPARC64_LD_DEF(ld, type, uint64_t)
513
514 #else /* __arch64__ */
515
516 /* 32-bit kernel, MMU bypass, non-constant */
517 #define SPARC64_LD_PHYS_NONCONST(ld) \
518 __asm volatile( \
519 "rdpr %%pstate,%1; " \
520 "sllx %3,32,%0; " \
521 "wrpr %1,8,%%pstate; " \
522 "or %0,%2,%0; " \
523 "wr %4,%%g0,%%asi; " \
524 #ld " [%0]%%asi,%0; " \
525 "wrpr %1,0,%%pstate " \
526 : "=&r" (_v), "=&r" (_pstate) \
527 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi))
528 /* 32-bit kernel, non-constant */
529 #define SPARC64_LD_NONCONST(ld) \
530 __asm volatile( \
531 "wr %2,%%g0,%%asi; " \
532 #ld " [%1]%%asi,%0 " \
533 : "=&r" (_v) \
534 : "r" ((uint32_t)(loc)), "r" (asi))
535 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */
536 #define SPARC64_LD_PHYS_NONCONST64(ld) \
537 __asm volatile( \
538 "rdpr %%pstate,%1; " \
539 "sllx %3,32,%0; " \
540 "wrpr %1,8,%%pstate; " \
541 "or %0,%2,%0; " \
542 "wr %4,%%g0,%%asi; " \
543 #ld " [%0]%%asi,%0; " \
544 "wrpr %1,0,%%pstate; " \
545 "srlx %0,32,%1; " \
546 "srl %0,0,%0 " \
547 : "=&r" (_vlo), "=&r" (_vhi) \
548 : "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi))
549 /* 32-bit kernel, non-constant, 64-bit value */
550 #define SPARC64_LD_NONCONST64(ld) \
551 __asm volatile( \
552 "wr %3,%%g0,%%asi; " \
553 #ld " [%2]%%asi,%0; " \
554 "srlx %0,32,%1; " \
555 "srl %0,0,%0 " \
556 : "=&r" (_vlo), "=&r" (_vhi) \
557 : "r" ((uint32_t)(loc)), "r" (asi))
558
559 #if defined(__GNUC__) && defined(__OPTIMIZE__)
560 #define SPARC64_LD_DEF(ld, type, vtype) \
561 static __inline type ld(paddr_t loc, int asi) \
562 { \
563 vtype _v; \
564 uint32_t _hi, _pstate; \
565 if (PHYS_ASI(asi)) { \
566 _hi = (uint64_t)(loc) >> 32; \
567 if (__builtin_constant_p(asi)) \
568 __asm volatile( \
569 "rdpr %%pstate,%1; " \
570 "sllx %3,32,%0; " \
571 "wrpr %1,8,%%pstate; " \
572 "or %0,%2,%0; " \
573 #ld " [%0]%4,%0; " \
574 "wrpr %1,0,%%pstate; " \
575 : "=&r" (_v), "=&r" (_pstate) \
576 : "r" ((uint32_t)(loc)), "r" (_hi), \
577 "n" (asi)); \
578 else \
579 SPARC64_LD_PHYS_NONCONST(ld); \
580 } else { \
581 if (__builtin_constant_p(asi)) \
582 __asm volatile( \
583 #ld " [%1]%2,%0 " \
584 : "=&r" (_v) \
585 : "r" ((uint32_t)(loc)), "n" (asi)); \
586 else \
587 SPARC64_LD_NONCONST(ld); \
588 } \
589 return _v; \
590 }
591 #define SPARC64_LD_DEF64(ld, type) \
592 static __inline type ld(paddr_t loc, int asi) \
593 { \
594 uint32_t _vlo, _vhi, _hi; \
595 if (PHYS_ASI(asi)) { \
596 _hi = (uint64_t)(loc) >> 32; \
597 if (__builtin_constant_p(asi)) \
598 __asm volatile( \
599 "rdpr %%pstate,%1; " \
600 "sllx %3,32,%0; " \
601 "wrpr %1,8,%%pstate; " \
602 "or %0,%2,%0; " \
603 #ld " [%0]%4,%0; " \
604 "wrpr %1,0,%%pstate; " \
605 "srlx %0,32,%1; " \
606 "srl %0,0,%0 " \
607 : "=&r" (_vlo), "=&r" (_vhi) \
608 : "r" ((uint32_t)(loc)), "r" (_hi), \
609 "n" (asi)); \
610 else \
611 SPARC64_LD_PHYS_NONCONST64(ld); \
612 } else { \
613 if (__builtin_constant_p(asi)) \
614 __asm volatile( \
615 #ld " [%2]%3,%0; " \
616 "srlx %0,32,%1; " \
617 "srl %0,0,%0 " \
618 : "=&r" (_vlo), "=&r" (_vhi) \
619 : "r" ((uint32_t)(loc)), "n" (asi)); \
620 else \
621 SPARC64_LD_NONCONST64(ld); \
622 } \
623 return ((uint64_t)_vhi << 32) | _vlo; \
624 }
625 #else
626 #define SPARC64_LD_DEF(ld, type, vtype) \
627 static __inline type ld(paddr_t loc, int asi) \
628 { \
629 vtype _v; \
630 uint32_t _hi, _pstate; \
631 if (PHYS_ASI(asi)) { \
632 _hi = (uint64_t)(loc) >> 32; \
633 SPARC64_LD_PHYS_NONCONST(ld); \
634 } else \
635 SPARC64_LD_NONCONST(ld); \
636 return _v; \
637 }
638 #define SPARC64_LD_DEF64(ld, type) \
639 static __inline type ld(paddr_t loc, int asi) \
640 { \
641 uint32_t _vlo, _vhi, _hi; \
642 if (PHYS_ASI(asi)) { \
643 _hi = (uint64_t)(loc) >> 32; \
644 SPARC64_LD_PHYS_NONCONST64(ld); \
645 } else \
646 SPARC64_LD_NONCONST64(ld); \
647 return ((uint64_t)_vhi << 32) | _vlo; \
648 }
649 #endif
650
651 #endif /* __arch64__ */
652
653 /* load byte from alternate address space */
654 SPARC64_LD_DEF(lduba, uint8_t, uint32_t)
655 /* load half-word from alternate address space */
656 SPARC64_LD_DEF(lduha, uint16_t, uint32_t)
657 /* load unsigned int from alternate address space */
658 SPARC64_LD_DEF(lda, uint32_t, uint32_t)
659 /* load signed int from alternate address space */
660 SPARC64_LD_DEF(ldswa, int, int)
661 /* load 64-bit unsigned int from alternate address space */
662 SPARC64_LD_DEF64(ldxa, uint64_t)
663
664
665 #ifdef __arch64__
666
667 /* 64-bit kernel, non-constant */
668 #define SPARC64_ST_NONCONST(st) \
669 __asm volatile( \
670 "wr %2,%%g0,%%asi; " \
671 #st " %0,[%1]%%asi " \
672 : : "r" (value), "r" ((__uintptr_t)(loc)), \
673 "r" (asi))
674
675 #if defined(__GNUC__) && defined(__OPTIMIZE__)
676 #define SPARC64_ST_DEF(st, type) \
677 static __inline void st(paddr_t loc, int asi, type value) \
678 { \
679 if (__builtin_constant_p(asi)) \
680 __asm volatile( \
681 #st " %0,[%1]%2 " \
682 : : "r" (value), "r" ((__uintptr_t)(loc)), \
683 "n" (asi)); \
684 else \
685 SPARC64_ST_NONCONST(st); \
686 }
687 #else
688 #define SPARC64_ST_DEF(st, type) \
689 static __inline void st(paddr_t loc, int asi, type value) \
690 { \
691 SPARC64_ST_NONCONST(st); \
692 }
693 #endif
694 #define SPARC64_ST_DEF64(st, type) SPARC64_ST_DEF(st, type)
695
696 #else /* __arch64__ */
697
698 /* 32-bit kernel, MMU bypass, non-constant */
699 #define SPARC64_ST_PHYS_NONCONST(st) \
700 __asm volatile( \
701 "rdpr %%pstate,%1; " \
702 "sllx %4,32,%0; " \
703 "wrpr %1,8,%%pstate; " \
704 "or %0,%3,%0; " \
705 "wr %5,%%g0,%%asi; " \
706 #st " %2,[%0]%%asi; " \
707 "wrpr %1,0,%%pstate " \
708 : "=&r" (_hi), "=&r" (_pstate) \
709 : "r" (value), "r" ((uint32_t)(loc)), \
710 "r" (_hi), "r" (asi))
711 /* 32-bit kernel, non-constant */
712 #define SPARC64_ST_NONCONST(st) \
713 __asm volatile( \
714 "wr %2,%%g0,%%asi; " \
715 #st " %0,[%1]%%asi " \
716 : : "r" (value), "r" ((uint32_t)(loc)), "r" (asi))
717 /* 32-bit kernel, MMU bypass, non-constant, 64-bit value */
718 #define SPARC64_ST_PHYS_NONCONST64(st) \
719 __asm volatile( \
720 "sllx %4,32,%1; " \
721 "sllx %6,32,%0; " \
722 "rdpr %%pstate,%2; " \
723 "or %1,%3,%1; " \
724 "wrpr %2,8,%%pstate; " \
725 "or %0,%5,%0; " \
726 "wr %7,%%g0,%%asi; " \
727 #st " %1,[%0]%%asi; " \
728 "wrpr %2,0,%%pstate " \
729 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \
730 : "r" (_vlo), "r" (_vhi), \
731 "r" ((uint32_t)(loc)), "r" (_hi), "r" (asi))
732 /* 32-bit kernel, non-constant, 64-bit value */
733 #define SPARC64_ST_NONCONST64(st) \
734 __asm volatile( \
735 "sllx %2,32,%0; " \
736 "or %0,%1,%0; " \
737 "wr %4,%%g0,%%asi; " \
738 #st " %0,[%3]%%asi " \
739 : "=&r" (_vhi) \
740 : "r" (_vlo), "r" (_vhi), \
741 "r" ((uint32_t)(loc)), "r" (asi))
742
743 #if defined(__GNUC__) && defined(__OPTIMIZE__)
744 #define SPARC64_ST_DEF(st, type) \
745 static __inline void st(paddr_t loc, int asi, type value) \
746 { \
747 uint32_t _hi, _pstate; \
748 if (PHYS_ASI(asi)) { \
749 _hi = (uint64_t)(loc) >> 32; \
750 if (__builtin_constant_p(asi)) \
751 __asm volatile( \
752 "sllx %4,32,%0; " \
753 "rdpr %%pstate,%1; " \
754 "or %0,%3,%0; " \
755 "wrpr %1,8,%%pstate; " \
756 #st " %2,[%0]%5; " \
757 "wrpr %1,0,%%pstate " \
758 : "=&r" (_hi), "=&r" (_pstate) \
759 : "r" (value), "r" ((uint32_t)(loc)), \
760 "r" (_hi), "n" (asi)); \
761 else \
762 SPARC64_ST_PHYS_NONCONST(st); \
763 } else { \
764 if (__builtin_constant_p(asi)) \
765 __asm volatile( \
766 #st " %0,[%1]%2 " \
767 : : "r" (value), "r" ((uint32_t)(loc)), \
768 "n" (asi)); \
769 else \
770 SPARC64_ST_NONCONST(st); \
771 } \
772 }
773 #define SPARC64_ST_DEF64(st, type) \
774 static __inline void st(paddr_t loc, int asi, type value) \
775 { \
776 uint32_t _vlo, _vhi, _hi; \
777 _vlo = value; \
778 _vhi = (uint64_t)(value) >> 32; \
779 if (PHYS_ASI(asi)) { \
780 _hi = (uint64_t)(loc) >> 32; \
781 if (__builtin_constant_p(asi)) \
782 __asm volatile( \
783 "sllx %4,32,%1; " \
784 "sllx %6,32,%0; " \
785 "rdpr %%pstate,%2; " \
786 "or %1,%3,%1; " \
787 "or %0,%5,%0; " \
788 "wrpr %2,8,%%pstate; " \
789 #st " %1,[%0]%7; " \
790 "wrpr %2,0,%%pstate " \
791 : "=&r" (_hi), "=&r" (_vhi), "=&r" (_vlo) \
792 : "r" (_vlo), "r" (_vhi), \
793 "r" ((uint32_t)(loc)), "r" (_hi), \
794 "n" (asi)); \
795 else \
796 SPARC64_ST_PHYS_NONCONST64(st); \
797 } else { \
798 if (__builtin_constant_p(asi)) \
799 __asm volatile( \
800 "sllx %2,32,%0; " \
801 "or %0,%1,%0; " \
802 #st " %0,[%3]%4 " \
803 : "=&r" (_vhi) \
804 : "r" (_vlo), "r" (_vhi), \
805 "r" ((uint32_t)(loc)), "n" (asi)); \
806 else \
807 SPARC64_ST_NONCONST64(st); \
808 } \
809 }
810 #else
811 #define SPARC64_ST_DEF(st, type) \
812 static __inline void st(paddr_t loc, int asi, type value) \
813 { \
814 uint32_t _hi, _pstate; \
815 if (PHYS_ASI(asi)) { \
816 _hi = (uint64_t)(loc) >> 32; \
817 SPARC64_ST_PHYS_NONCONST(st); \
818 } else \
819 SPARC64_ST_NONCONST(st); \
820 }
821 #define SPARC64_ST_DEF64(st, type) \
822 static __inline void st(paddr_t loc, int asi, type value) \
823 { \
824 uint32_t _vlo, _vhi, _hi; \
825 _vlo = value; \
826 _vhi = (uint64_t)(value) >> 32; \
827 if (PHYS_ASI(asi)) { \
828 _hi = (uint64_t)(loc) >> 32; \
829 SPARC64_ST_PHYS_NONCONST64(st); \
830 } else \
831 SPARC64_ST_NONCONST64(st); \
832 }
833 #endif
834
835 #endif /* __arch64__ */
836
837 /* store byte to alternate address space */
838 SPARC64_ST_DEF(stba, uint8_t)
839 /* store half-word to alternate address space */
840 SPARC64_ST_DEF(stha, uint16_t)
841 /* store unsigned int to alternate address space */
842 SPARC64_ST_DEF(sta, uint32_t)
843 /* store 64-bit unsigned int to alternate address space */
844 SPARC64_ST_DEF64(stxa, uint64_t)
845
846
847 /* set dmmu secondary context */
848 static __inline void
849 dmmu_set_secondary_context(uint ctx)
850 {
851 __asm volatile(
852 "stxa %0,[%1]%2; "
853 "membar #Sync "
854 : : "r" (ctx), "r" (CTX_SECONDARY), "n" (ASI_DMMU)
855 : "memory");
856 }
857
858 /* flush address from data cache */
859 #define flush(loc) __asm volatile("flush %0" : : "r" ((__uintptr_t)(loc)))
860
861 /*
862 * SPARC V9 memory barrier instructions.
863 */
864 /* Make all stores complete before next store */
865 #define membar_storestore() __asm volatile("membar #StoreStore" : :)
866 /* Make all loads complete before next store */
867 #define membar_loadstore() __asm volatile("membar #LoadStore" : :)
868 /* Make all stores complete before next load */
869 #define membar_storeload() __asm volatile("membar #StoreLoad" : :)
870 /* Make all loads complete before next load */
871 #define membar_loadload() __asm volatile("membar #LoadLoad" : :)
872 /* Complete all outstanding memory operations and exceptions */
873 #define membar_sync() __asm volatile("membar #Sync" : :)
874 /* Complete all outstanding memory operations */
875 #define membar_memissue() __asm volatile("membar #MemIssue" : :)
876 /* Complete all outstanding stores before any new loads */
877 #define membar_lookaside() __asm volatile("membar #Lookaside" : :)
878
879 #define membar_load() __asm volatile("membar #LoadLoad | #LoadStore" : :)
880 #define membar_store() __asm volatile("membar #LoadStore | #StoreStore" : :)
881
882 #endif
883
884 #endif /* _SPARC_CTLREG_H_ */
NetBSD on the FriendlyARM MINI2440