sys/arch/sparc64/include/psl.h

   1 /*      $NetBSD: psl.h,v 1.42 2009/11/25 14:28:50 rmind Exp $ */
   2
   3 /*
   4  * Copyright (c) 1992, 1993
   5  *      The Regents of the University of California.  All rights reserved.
   6  *
   7  * This software was developed by the Computer Systems Engineering group
   8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
   9  * contributed to Berkeley.
  10  *
  11  * All advertising materials mentioning features or use of this software
  12  * must display the following acknowledgement:
  13  *      This product includes software developed by the University of
  14  *      California, Lawrence Berkeley Laboratory.
  15  *
  16  * Redistribution and use in source and binary forms, with or without
  17  * modification, are permitted provided that the following conditions
  18  * are met:
  19  * 1. Redistributions of source code must retain the above copyright
  20  *    notice, this list of conditions and the following disclaimer.
  21  * 2. Redistributions in binary form must reproduce the above copyright
  22  *    notice, this list of conditions and the following disclaimer in the
  23  *    documentation and/or other materials provided with the distribution.
  24  * 3. Neither the name of the University nor the names of its contributors
  25  *    may be used to endorse or promote products derived from this software
  26  *    without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  *      @(#)psl.h       8.1 (Berkeley) 6/11/93
  41  */
  42
  43 #ifndef PSR_IMPL
  44
  45 /*
  46  * SPARC Process Status Register (in psl.h for hysterical raisins).  This
  47  * doesn't exist on the V9.
  48  *
  49  * The picture in the Sun manuals looks like this:
  50  *                                           1 1
  51  *       31   28 27   24 23   20 19       14 3 2 11    8 7 6 5 4       0
  52  *      +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
  53  *      |  impl |  ver  |  icc  |  reserved |E|E|  pil  |S|P|E|   CWP   |
  54  *      |       |       |n z v c|           |C|F|       | |S|T|         |
  55  *      +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
  56  */
  57
  58 #define PSR_IMPL        0xf0000000      /* implementation */
  59 #define PSR_VER         0x0f000000      /* version */
  60 #define PSR_ICC         0x00f00000      /* integer condition codes */
  61 #define PSR_N           0x00800000      /* negative */
  62 #define PSR_Z           0x00400000      /* zero */
  63 #define PSR_O           0x00200000      /* overflow */
  64 #define PSR_C           0x00100000      /* carry */
  65 #define PSR_EC          0x00002000      /* coprocessor enable */
  66 #define PSR_EF          0x00001000      /* FP enable */
  67 #define PSR_PIL         0x00000f00      /* interrupt level */
  68 #define PSR_S           0x00000080      /* supervisor (kernel) mode */
  69 #define PSR_PS          0x00000040      /* previous supervisor mode (traps) */
  70 #define PSR_ET          0x00000020      /* trap enable */
  71 #define PSR_CWP         0x0000001f      /* current window pointer */
  72
  73 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
  74
  75 /* Interesting spl()s */
  76 #define PIL_SCSI        3
  77 #define PIL_FDSOFT      4
  78 #define PIL_AUSOFT      4
  79 #define PIL_BIO         5
  80 #define PIL_VIDEO       5
  81 #define PIL_TTY         6
  82 #define PIL_LPT         6
  83 #define PIL_NET         6
  84 #define PIL_VM          7
  85 #define PIL_AUD         8
  86 #define PIL_CLOCK       10
  87 #define PIL_FD          11
  88 #define PIL_SER         12
  89 #define PIL_STATCLOCK   14
  90 #define PIL_HIGH        15
  91 #define PIL_SCHED       PIL_CLOCK
  92 #define PIL_LOCK        PIL_HIGH
  93
  94 /*
  95  * SPARC V9 CCR register
  96  */
  97
  98 #define ICC_C   0x01L
  99 #define ICC_V   0x02L
 100 #define ICC_Z   0x04L
 101 #define ICC_N   0x08L
 102 #define XCC_SHIFT       4
 103 #define XCC_C   (ICC_C<<XCC_SHIFT)
 104 #define XCC_V   (ICC_V<<XCC_SHIFT)
 105 #define XCC_Z   (ICC_Z<<XCC_SHIFT)
 106 #define XCC_N   (ICC_N<<XCC_SHIFT)
 107
 108
 109 /*
 110  * SPARC V9 PSTATE register (what replaces the PSR in V9)
 111  *
 112  * Here's the layout:
 113  *
 114  *    11   10    9     8   7  6   5     4     3     2     1   0
 115  *  +------------------------------------------------------------+
 116  *  | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
 117  *  +------------------------------------------------------------+
 118  */
 119
 120 #define PSTATE_IG       0x800   /* enable spitfire interrupt globals */
 121 #define PSTATE_MG       0x400   /* enable spitfire MMU globals */
 122 #define PSTATE_CLE      0x200   /* current little endian */
 123 #define PSTATE_TLE      0x100   /* traps little endian */
 124 #define PSTATE_MM       0x0c0   /* memory model */
 125 #define PSTATE_MM_TSO   0x000   /* total store order */
 126 #define PSTATE_MM_PSO   0x040   /* partial store order */
 127 #define PSTATE_MM_RMO   0x080   /* Relaxed memory order */
 128 #define PSTATE_RED      0x020   /* RED state */
 129 #define PSTATE_PEF      0x010   /* enable floating point */
 130 #define PSTATE_AM       0x008   /* 32-bit address masking */
 131 #define PSTATE_PRIV     0x004   /* privileged mode */
 132 #define PSTATE_IE       0x002   /* interrupt enable */
 133 #define PSTATE_AG       0x001   /* enable alternate globals */
 134
 135 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
 136
 137
 138 /*
 139  * 32-bit code requires TSO or at best PSO since that's what's supported on
 140  * SPARC V8 and earlier machines.
 141  *
 142  * 64-bit code sets the memory model in the ELF header.
 143  *
 144  * We're running kernel code in TSO for the moment so we don't need to worry
 145  * about possible memory barrier bugs.
 146  */
 147
 148 #ifdef __arch64__
 149 #define PSTATE_PROM     (PSTATE_MM_TSO|PSTATE_PRIV)
 150 #define PSTATE_NUCLEUS  (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG)
 151 #define PSTATE_KERN     (PSTATE_MM_TSO|PSTATE_PRIV)
 152 #define PSTATE_INTR     (PSTATE_KERN|PSTATE_IE)
 153 #define PSTATE_USER32   (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
 154 #define PSTATE_USER     (PSTATE_MM_RMO|PSTATE_IE)
 155 #else
 156 #define PSTATE_PROM     (PSTATE_MM_TSO|PSTATE_PRIV)
 157 #define PSTATE_NUCLEUS  (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG)
 158 #define PSTATE_KERN     (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV)
 159 #define PSTATE_INTR     (PSTATE_KERN|PSTATE_IE)
 160 #define PSTATE_USER32   (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
 161 #define PSTATE_USER     (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
 162 #endif
 163
 164
 165 /*
 166  * SPARC V9 TSTATE register
 167  *
 168  *   39 32 31 24 23 18  17   8  7 5 4   0
 169  *  +-----+-----+-----+--------+---+-----+
 170  *  | CCR | ASI |  -  | PSTATE | - | CWP |
 171  *  +-----+-----+-----+--------+---+-----+
 172  */
 173
 174 #define TSTATE_CWP              0x01f
 175 #define TSTATE_PSTATE           0x6ff00
 176 #define TSTATE_PSTATE_SHIFT     8
 177 #define TSTATE_ASI              0xff000000LL
 178 #define TSTATE_ASI_SHIFT        24
 179 #define TSTATE_CCR              0xff00000000LL
 180 #define TSTATE_CCR_SHIFT        32
 181
 182 #define PSRCC_TO_TSTATE(x)      (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-20))
 183 #define TSTATECCR_TO_PSR(x)     (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-20))
 184
 185 /*
 186  * These are here to simplify life.
 187  */
 188 #define TSTATE_IG       (PSTATE_IG<<TSTATE_PSTATE_SHIFT)
 189 #define TSTATE_MG       (PSTATE_MG<<TSTATE_PSTATE_SHIFT)
 190 #define TSTATE_CLE      (PSTATE_CLE<<TSTATE_PSTATE_SHIFT)
 191 #define TSTATE_TLE      (PSTATE_TLE<<TSTATE_PSTATE_SHIFT)
 192 #define TSTATE_MM       (PSTATE_MM<<TSTATE_PSTATE_SHIFT)
 193 #define TSTATE_MM_TSO   (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT)
 194 #define TSTATE_MM_PSO   (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT)
 195 #define TSTATE_MM_RMO   (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT)
 196 #define TSTATE_RED      (PSTATE_RED<<TSTATE_PSTATE_SHIFT)
 197 #define TSTATE_PEF      (PSTATE_PEF<<TSTATE_PSTATE_SHIFT)
 198 #define TSTATE_AM       (PSTATE_AM<<TSTATE_PSTATE_SHIFT)
 199 #define TSTATE_PRIV     (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT)
 200 #define TSTATE_IE       (PSTATE_IE<<TSTATE_PSTATE_SHIFT)
 201 #define TSTATE_AG       (PSTATE_AG<<TSTATE_PSTATE_SHIFT)
 202
 203 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
 204
 205 #define TSTATE_KERN     ((PSTATE_KERN)<<TSTATE_PSTATE_SHIFT)
 206 #define TSTATE_USER     ((PSTATE_USER)<<TSTATE_PSTATE_SHIFT)
 207 /*
 208  * SPARC V9 VER version register.
 209  *
 210  *  63   48 47  32 31  24 23 16 15    8 7 5 4      0
 211  * +-------+------+------+-----+-------+---+--------+
 212  * | manuf | impl | mask |  -  | maxtl | - | maxwin |
 213  * +-------+------+------+-----+-------+---+--------+
 214  *
 215  */
 216
 217 #define VER_MANUF       0xffff000000000000LL
 218 #define VER_MANUF_SHIFT 48
 219 #define VER_IMPL        0x0000ffff00000000LL
 220 #define VER_IMPL_SHIFT  32
 221 #define VER_MASK        0x00000000ff000000LL
 222 #define VER_MASK_SHIFT  24
 223 #define VER_MAXTL       0x000000000000ff00LL
 224 #define VER_MAXTL_SHIFT 8
 225 #define VER_MAXWIN      0x000000000000001fLL
 226
 227 /*
 228  * Here are a few things to help us transition between user and kernel mode:
 229  */
 230
 231 /* Memory models */
 232 #define KERN_MM         PSTATE_MM_TSO
 233 #define USER_MM         PSTATE_MM_RMO
 234
 235 /*
 236  * Register window handlers.  These point to generic routines that check the
 237  * stack pointer and then vector to the real handler.  We could optimize this
 238  * if we could guarantee only 32-bit or 64-bit stacks.
 239  */
 240 #define WSTATE_KERN     026
 241 #define WSTATE_USER     022
 242
 243 #define CWP             0x01f
 244
 245 /* 64-byte alignment -- this seems the best place to put this. */
 246 #define BLOCK_SIZE      64
 247 #define BLOCK_ALIGN     0x3f
 248
 249 #if defined(_KERNEL) && !defined(_LOCORE)
 250
 251 /*
 252  * Inlines for manipulating privileged registers
 253  */
 254 #define SPARC64_GETPR_DEF(pr, type)     \
 255 static __inline type get##pr(void)                                      \
 256 {                                                                       \
 257         type pr;                                                        \
 258         __asm volatile("rdpr %%" #pr ",%0" : "=r" (pr));                \
 259         return pr;                                                      \
 260 }
 261 #define SPARC64_SETPR_DEF(pr, type)     \
 262 static __inline void set##pr(type pr)                                   \
 263 {                                                                       \
 264         __asm volatile("wrpr %0,0,%%" #pr : : "r" (pr) : "memory");     \
 265 }
 266
 267 #ifdef __arch64__
 268 #define SPARC64_GETPR64_DEF(pr) SPARC64_GETPR_DEF(pr, uint64_t)
 269 #define SPARC64_SETPR64_DEF(pr) SPARC64_SETPR_DEF(pr, uint64_t)
 270 #else
 271 #define SPARC64_GETPR64_DEF(pr) \
 272 static __inline uint64_t get##pr(void)                                  \
 273 {                                                                       \
 274         uint32_t _hi, _lo;                                              \
 275         __asm volatile("rdpr %%" #pr ",%0; srl %0,0,%1; srlx %0,32,%0"  \
 276                 : "=r" (_hi), "=r" (_lo));                              \
 277         return ((uint64_t)_hi << 32) | _lo;                             \
 278 }
 279 #define SPARC64_SETPR64_DEF(pr) \
 280 static __inline void set##pr(uint64_t pr)                               \
 281 {                                                                       \
 282         uint32_t _hi = pr >> 32, _lo = pr;                              \
 283         __asm volatile("sllx %1,32,%0; or %0,%2,%0; wrpr %0,0,%%" #pr   \
 284                        : "=&r" (_hi) /* scratch register */             \
 285                        : "r" (_hi), "r" (_lo) : "memory");              \
 286 }
 287 #endif
 288
 289 /* Tick Register (PR 4) */
 290 SPARC64_GETPR64_DEF(tick)
 291 SPARC64_SETPR64_DEF(tick)
 292
 293 /* Processor State Register (PR 6) */
 294 SPARC64_GETPR_DEF(pstate, int)
 295 SPARC64_SETPR_DEF(pstate, int)
 296
 297 /* Trap Level Register (PR 7) */
 298 SPARC64_GETPR_DEF(tl, int)
 299
 300 /* Current Window Pointer Register (PR 9) */
 301 SPARC64_GETPR_DEF(cwp, int)
 302 SPARC64_SETPR_DEF(cwp, int)
 303
 304 /* Version Register (PR 31) */
 305 SPARC64_GETPR64_DEF(ver)
 306
 307 static __inline int
 308 intr_disable(void)
 309 {
 310         int pstate = getpstate();
 311
 312         setpstate(pstate & ~PSTATE_IE);
 313         return pstate;
 314 }
 315
 316 static __inline void
 317 intr_restore(int pstate)
 318 {
 319         setpstate(pstate);
 320 }
 321
 322 /*
 323  * GCC pseudo-functions for manipulating PIL
 324  */
 325
 326 #ifdef SPLDEBUG
 327 void prom_printf(const char *fmt, ...);
 328 extern int printspl;
 329 #define SPLPRINT(x) \
 330 { \
 331         if (printspl) { \
 332                 int i = 10000000; \
 333                 prom_printf x ; \
 334                 while (i--) \
 335                         ; \
 336         } \
 337 }
 338 #define SPL(name, newpil) \
 339 static __inline int name##X(const char* file, int line) \
 340 { \
 341         int oldpil; \
 342         __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
 343         SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \
 344         __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
 345         return (oldpil); \
 346 }
 347 /* A non-priority-decreasing version of SPL */
 348 #define SPLHOLD(name, newpil) \
 349 static __inline int name##X(const char* file, int line) \
 350 { \
 351         int oldpil; \
 352         __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
 353         if (newpil <= oldpil) \
 354                 return oldpil; \
 355         SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \
 356         __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
 357         return (oldpil); \
 358 }
 359
 360 #else
 361 #define SPLPRINT(x)
 362 #define SPL(name, newpil) \
 363 static __inline int name(void) \
 364 { \
 365         int oldpil; \
 366         __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
 367         __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
 368         return (oldpil); \
 369 }
 370 /* A non-priority-decreasing version of SPL */
 371 #define SPLHOLD(name, newpil) \
 372 static __inline int name(void) \
 373 { \
 374         int oldpil; \
 375         __asm volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
 376         if (newpil <= oldpil) \
 377                 return oldpil; \
 378         __asm volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil) : "memory"); \
 379         return (oldpil); \
 380 }
 381 #endif
 382
 383 typedef uint8_t ipl_t;
 384 typedef struct {
 385         ipl_t _ipl;
 386 } ipl_cookie_t;
 387
 388 static __inline ipl_cookie_t
 389 makeiplcookie(ipl_t ipl)
 390 {
 391
 392         return (ipl_cookie_t){._ipl = ipl};
 393 }
 394
 395 static __inline int __attribute__((__unused__))
 396 splraiseipl(ipl_cookie_t icookie)
 397 {
 398         int newpil = icookie._ipl;
 399         int oldpil;
 400
 401         /*
 402          * NetBSD/sparc64's IPL_* constants equate directly to the
 403          * corresponding PIL_* names; no need to map them here.
 404          */
 405         __asm volatile("rdpr %%pil,%0" : "=r" (oldpil));
 406         if (newpil <= oldpil)
 407                 return (oldpil);
 408         __asm volatile("wrpr %0,0,%%pil" : : "r" (newpil) : "memory");
 409         return (oldpil);
 410 }
 411
 412 SPL(spl0, 0)
 413
 414 SPLHOLD(splsoftint, 1)
 415 #define splsoftclock    splsoftint
 416 #define splsoftnet      splsoftint
 417
 418 SPLHOLD(splsoftserial, 4)
 419
 420 /* audio software interrupts are at software level 4 */
 421 SPLHOLD(splausoft, PIL_AUSOFT)
 422
 423 /* floppy software interrupts are at software level 4 too */
 424 SPLHOLD(splfdsoft, PIL_FDSOFT)
 425
 426 /*
 427  * Memory allocation (must be as high as highest network, tty, or disk device)
 428  */
 429 SPLHOLD(splvm, PIL_VM)
 430
 431 /* fd hardware interrupts are at level 11 */
 432 SPLHOLD(splfd, PIL_FD)
 433
 434 /* zs hardware interrupts are at level 12 */
 435 SPLHOLD(splzs, PIL_SER)
 436 SPLHOLD(splserial, PIL_SER)
 437
 438 /* audio hardware interrupts are at level 13 */
 439 SPLHOLD(splaudio, PIL_AUD)
 440
 441 /* second sparc timer interrupts at level 14 */
 442 SPLHOLD(splstatclock, PIL_STATCLOCK)
 443
 444 SPLHOLD(splsched, PIL_SCHED)
 445 SPLHOLD(spllock, PIL_LOCK)
 446
 447 SPLHOLD(splhigh, PIL_HIGH)
 448
 449 /* splx does not have a return value */
 450 #ifdef SPLDEBUG
 451 #define spl0()  spl0X(__FILE__, __LINE__)
 452 #define splsoftint()    splsoftintX(__FILE__, __LINE__)
 453 #define splsoftserial() splsoftserialX(__FILE__, __LINE__)
 454 #define splausoft()     splausoftX(__FILE__, __LINE__)
 455 #define splfdsoft()     splfdsoftX(__FILE__, __LINE__)
 456 #define splvm()         splvmX(__FILE__, __LINE__)
 457 #define splclock()      splclockX(__FILE__, __LINE__)
 458 #define splfd()         splfdX(__FILE__, __LINE__)
 459 #define splzs()         splzsX(__FILE__, __LINE__)
 460 #define splserial()     splzerialX(__FILE__, __LINE__)
 461 #define splaudio()      splaudioX(__FILE__, __LINE__)
 462 #define splstatclock()  splstatclockX(__FILE__, __LINE__)
 463 #define splsched()      splschedX(__FILE__, __LINE__)
 464 #define spllock()       spllockX(__FILE__, __LINE__)
 465 #define splhigh()       splhighX(__FILE__, __LINE__)
 466 #define splx(x)         splxX((x),__FILE__, __LINE__)
 467
 468 static __inline void splxX(int newpil, const char *file, int line)
 469 #else
 470 static __inline void splx(int newpil)
 471 #endif
 472 {
 473 #ifdef SPLDEBUG
 474         int pil;
 475
 476         __asm volatile("rdpr %%pil,%0" : "=r" (pil));
 477         SPLPRINT(("{%d->%d}", pil, newpil));
 478 #endif
 479         __asm volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil) : "memory");
 480 }
 481 #endif /* KERNEL && !_LOCORE */
 482
 483 #endif /* PSR_IMPL */