1 /* $NetBSD: hdc9224.h,v 1.4.22.3 2004/09/21 13:24:07 skrll Exp $ */
3 * Copyright (c) 1996 Ludd, University of Lule}, Sweden.
6 * This code is derived from software contributed to Ludd by Bertram Barth.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed at Ludd, University of
19 * Lule}, Sweden and its contributors.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 struct hdc9224_DKCreg
{
37 unsigned char dkc_reg
; /* Disk Register Data Access Port (rw)*/
38 unsigned char fill
[3]; /* bytes are longword aligned */
39 unsigned char dkc_cmd
; /* Disk Controller Command Port (wo) */
40 #define dkc_stat dkc_cmd /* Interrupt Status Port (ro) */
44 * definition of some commands (constant bits only, incomplete!)
46 #define DKC_CMD_RESET 0x00 /* terminate non-data-transfer cmds */
47 #define DKC_CMD_DRDESELECT 0x01 /* done when no drive is in use */
48 #define DKC_CMD_SETREGPTR 0x40 /* logically or-ed with reg-number */
49 #define DKC_CMD_DRSELECT 0x20
50 #define DKC_CMD_DRSEL_HDD 0x24 /* select HDD, or-ed with unit-numb. */
51 #define DKC_CMD_DRSEL_RX33 0x28 /* or-ed with unit-number of RX33 */
52 #define DKC_CMD_DRSEL_RX50 0x2C /* or-ed with unit-number of RX50 */
53 #define DKC_CMD_RESTORE 0x02
54 #define DKC_CMD_STEP 0x04
55 #define DKC_CMD_STEPIN_FDD 0x04 /* one step inward for floppy */
56 #define DKC_CMD_STEPOUT_FDD 0x06 /* one step outward (toward cyl #0) */
57 #define DKC_CMD_POLLDRIVE 0x10
58 #define DKC_CMD_SEEKREADID 0x50
59 #define DKC_CMD_FORMATTRACK 0x60
60 #define DKC_CMD_READTRACK 0x5A
61 #define DKC_CMD_READPHYSICAL 0x58
62 #define DKC_CMD_READLOGICAL 0x5C
63 #define DKC_CMD_READ_HDD 0x5D /* read-logical, bypass=0, xfer=1 */
64 #define DKC_CMD_READ_RX33 0x5D /* ??? */
65 #define DKC_CMD_WRITEPHYSICAL 0x80
66 #define DKC_CMD_WRITELOGICAL 0xC0
67 #define DKC_CMD_WRITE_HDD 0xA0 /* bypass=0, ddmark=0 */
68 #define DKC_CMD_WRITE_RX33 0xA1 /* precompensation differs... */
69 #define DKC_CMD_WRITE_RX50 0xA4
72 * Definition of bits in the DKC_STAT register
74 #define DKC_ST_INTPEND (1<<7) /* interrupt pending */
75 #define DKC_ST_DMAREQ (1<<6) /* DMA request */
76 #define DKC_ST_DONE (1<<5) /* command done */
77 #define DKC_ST_TERMCOD (3<<3) /* termination code (see below) */
78 #define DKC_ST_RDYCHNG (1<<2) /* ready change */
79 #define DKC_ST_OVRUN (1<<1) /* overrun/underrun */
80 #define DKC_ST_BADSECT (1<<0) /* bad sector */
83 * Definition of the termination codes
85 #define DKC_TC_SUCCESS (0<<3) /* Successful completion */
86 #define DKC_TC_RDIDERR (1<<3) /* Error in READ-ID sequence */
87 #define DKC_TC_VRFYERR (2<<3) /* Error in VERIFY sequence */
88 #define DKC_TC_DATAERR (3<<3) /* Error in DATA-TRANSFER seq. */
91 * Definitions of delays necessary for floppy-operation
93 #define DKC_DELAY_MOTOR 500 /* allow 500 ms to reach speed */
94 #define DKC_DELAY_SELECT 70 /* 70 ms for data-recovery-circuit */
95 #define DKC_DELAY_POSITION 59 /* 59 ms for RX33, 100 ms for RX50 */
96 #define DKC_DELAY_HEADSET 18 /* 18 ms when changing head-number */
99 * The HDC9224 has 11/15(?) internal registers which are accessible via
100 * the Disk-Register-Data-Access-Port DKC_REG
102 struct hdc9224_UDCreg
{ /* internal disk controller registers */
103 u_char udc_dma7
; /* 0: DMA address bits 0 - 7 */
104 u_char udc_dma15
; /* 1: DMA address bits 8 - 15 */
105 u_char udc_dma23
; /* 2: DMA address bits 16 - 23 */
106 u_char udc_dsect
; /* 3: desired/starting sector number */
107 #define udc_csect udc_dsect /* current sector number */
108 u_char udc_dhead
; /* 4: cyl-bits 8-10, desired head number */
109 #define udc_chead udc_dhead /* current head number */
110 u_char udc_dcyl
; /* 5: desired cylinder number */
111 #define udc_ccyl udc_dcyl /* current cylinder number */
112 u_char udc_scnt
; /* 6: sector count register */
113 u_char udc_rtcnt
; /* 7: retry count register */
114 u_char udc_mode
; /* 8: operation mode/chip status */
115 #define udc_cstat udc_mode /* chip status register */
116 u_char udc_term
; /* 9: termination conditions/drive status */
117 #define udc_dstat udc_term /* drive status register */
118 u_char udc_data
; /* 10: data */
125 * Definition of bits in the Current-Head register
127 #define UDC_CH_BADSECT (1<<7) /* indicates a bad sector (if bypass=0) */
128 #define UDC_CH_CYLBITS (0x70) /* bits 10-8 of current cylinder number */
129 #define UDC_CH_HEADNO (0x0F) /* current head number */
132 * Definition of bits in the Retry-Count register
134 #define UDC_RC_RTRYCNT (0xF0) /* 1's compl. in read-log, 0 all others */
135 #define UDC_RC_RXDISAB (1<<3) /* must/should be 0 for normal operation */
136 #define UDC_RC_INVRDY (1<<2) /* polarity of floppy-status, important! */
137 #define UDC_RC_MOTOR (1<<1) /* turn on floppy-motor, no effect on HDD */
138 #define UDC_RC_LOSPEED (1<<0) /* floppy-speed select, RX33: 0, RX50: 1 */
140 #define UDC_RC_HDD_READ 0xF2 /* 0x72 ??? */
141 #define UDC_RC_HDD_WRT 0xF2 /* 0xF0 ??? */
142 #define UDC_RC_RX33READ 0x76 /* enable retries when reading floppies */
143 #define UDC_RC_RX33WRT 0xF6
144 #define UDC_RC_RX50READ 0x77 /* enable retries when reading floppies */
145 #define UDC_RC_RX50WRT 0xF7
148 * Definition of bits in the Operating-Mode register
150 #define UDC_MD_HDMODE (1<<7) /* must be 1 for all FDD and HDD */
151 #define UDC_MD_CHKCOD (3<<5) /* error-check: FDD/CRC: 0, HDD/ECC: 1 */
152 #define UDC_MD_DENS (1<<4) /* density select, must be 0 */
153 #define UDC_MD_UNUSED (1<<3) /* bit 3 is not used and must be 0 */
154 #define UDC_MD_SRATE (7<<0) /* seek step rate */
156 #define UDC_MD_HDD 0xC0
157 #define UDC_MD_RX33 0x82
158 #define UDC_MD_RX50 0x81
161 * Definition of bits in the Chip-Status register
163 #define UDC_CS_RETREQ (1<<7) /* retry required */
164 #define UDC_CS_ECCATT (1<<6) /* error correction attempted */
165 #define UDC_CS_ECCERR (1<<5) /* ECC/CRC error */
166 #define UDC_CS_DELDATA (1<<4) /* deleted data mark */
167 #define UDC_CS_SYNCERR (1<<3) /* synchronization error */
168 #define UDC_CS_COMPERR (1<<2) /* compare error */
169 #define UDC_CS_PRESDRV (0x3) /* present drive selected */
172 * Definition of bits in the Termination-Conditions register
174 #define UDC_TC_CRCPRE (1<<7) /* CRC register preset, must be 1 */
175 #define UDC_TC_UNUSED (1<<6) /* bit 6 is not used and must be 0 */
176 #define UDC_TC_INTDONE (1<<5) /* interrupt on done */
177 #define UDC_TC_TDELDAT (1<<4) /* terminate on deleted data */
178 #define UDC_TC_TDSTAT3 (1<<3) /* terminate on drive status 3 change */
179 #define UDC_TC_TWPROT (1<<2) /* terminate on write-protect (FDD only) */
180 #define UDC_TC_INTRDCH (1<<1) /* interrupt on ready change (FDD only) */
181 #define UDC_TC_TWRFLT (1<<0) /* interrupt on write-fault (HDD only) */
183 #define UDC_TC_HDD 0xA5 /* 0xB5 ??? */
184 #define UDC_TC_FDD 0xA0 /* 0xAA ??? 0xB4 ??? */
187 * Definition of bits in the Disk-Status register
189 #define UDC_DS_SELACK (1<<7) /* select acknowledge (harddisk only!) */
190 #define UDC_DS_INDEX (1<<6) /* index point */
191 #define UDC_DS_SKCOM (1<<5) /* seek complete */
192 #define UDC_DS_TRK00 (1<<4) /* track 0 */
193 #define UDC_DS_DSTAT3 (1<<3) /* drive status 3 (MBZ) */
194 #define UDC_DS_WRPROT (1<<2) /* write protect (floppy only!) */
195 #define UDC_DS_READY (1<<1) /* drive ready bit */
196 #define UDC_DS_WRFAULT (1<<0) /* write fault */
