sys/dev/bi/bireg.h

   1 /*      $NetBSD: bireg.h,v 1.7.24.3 2004/09/21 13:27:24 skrll Exp $     */
   2 /*
   3  * Copyright (c) 1988 Regents of the University of California.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to Berkeley by
   7  * Chris Torek.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  *      @(#)bireg.h     7.3 (Berkeley) 6/28/90
  34  */
  35
  36 /*
  37  * VAXBI node definitions.
  38  */
  39
  40 /*
  41  * BI node addresses
  42  */
  43 #define BI_NODESIZE     0x2000  /* Size of one BI node */
  44 #define BI_NODE(node)   (BI_NODESIZE * (node))
  45 #define BI_BASE(bi,nod) ((0x20000000 + (bi) * 0x2000000) + BI_NODE(nod))
  46 #define MAXNBI          16      /* Spec says there can be 16 anyway */
  47 #define NNODEBI         16      /* 16 nodes per BI */
  48
  49 #define BI_PROBE        0x80000 /* CPU on 8200, NBIA on 8800 */
  50 /*
  51  * BI nodes all start with BI interface registers (those on the BIIC chip).
  52  * These are followed with interface-specific registers.
  53  *
  54  * NB: This structure does NOT include the four GPRs (not anymore!)
  55  *
  56  * 990712: The structs not used anymore due to conversion to bus.h.
  57  */
  58 #ifdef notdef
  59 struct biiregs {
  60         u_short bi_dtype;       /* device type */
  61         u_short bi_revs;        /* revisions */
  62         u_long  bi_csr;         /* control and status register */
  63         u_long  bi_ber;         /* bus error register */
  64         u_long  bi_eintrcsr;    /* error interrupt control register */
  65         u_long  bi_intrdes;     /* interrupt destination register */
  66                                 /* the rest are not required for all nodes */
  67         u_long  bi_ipintrmsk;   /* IP interrupt mask register */
  68         u_long  bi_fipsdes;     /* Force-Bit IPINTR/STOP destination reg */
  69         u_long  bi_ipintrsrc;   /* IPINTR source register */
  70         u_long  bi_sadr;        /* starting address register */
  71         u_long  bi_eadr;        /* ending address register */
  72         u_long  bi_bcicsr;      /* BCI control and status register */
  73         u_long  bi_wstat;       /* write status register */
  74         u_long  bi_fipscmd;     /* Force-Bit IPINTR/STOP command reg */
  75         u_long  bi_xxx1[3];     /* unused */
  76         u_long  bi_uintrcsr;    /* user interface interrupt control reg */
  77         u_long  bi_xxx2[43];    /* unused */
  78 /* although these are on the BIIC, their interpretation varies */
  79 /*      u_long  bi_gpr[4]; */   /* general purpose registers */
  80 };
  81
  82 /*
  83  * A generic BI node.
  84  */
  85 struct bi_node {
  86         struct  biiregs biic;   /* interface */
  87         u_long  bi_xxx[1988];   /* pad to 8K */
  88 };
  89
  90 /*
  91  * A CPU node.
  92  */
  93 struct bi_cpu {
  94         struct  biiregs biic;   /* interface chip */
  95         u_long  bi_gpr[4];      /* gprs (unused) */
  96         u_long  bi_sosr;        /* slave only status register */
  97         u_long  bi_xxx[63];     /* pad */
  98         u_long  bi_rxcd;        /* receive console data register */
  99 };
 100 #endif
 101
 102 #define BIREG_DTYPE             0x00
 103 #define BIREG_VAXBICSR          0x04
 104 #define BIREG_BER               0x08
 105 #define BIREG_EINTRCSR          0x0c
 106 #define BIREG_INTRDES           0x10
 107 #define BIREG_IPINTRMSK         0x14
 108 #define BIREG_FIPSDES           0x18
 109 #define BIREG_IPINTRSRC         0x1c
 110 #define BIREG_SADR              0x20
 111 #define BIREG_EADR              0x24
 112 #define BIREG_BCICSR            0x28
 113 #define BIREG_WSTAT             0x2c
 114 #define BIREG_FIPSCMD           0x30
 115 #define BIREG_UINTRCSR          0x40
 116
 117 /* device types */
 118 #define BIDT_MS820      0x0001  /* MS820 memory board */
 119 #define BIDT_DRB32      0x0101  /* DRB32 (MFA) Supercomputer gateway */
 120 #define BIDT_DWBUA      0x0102  /* DWBUA Unibus adapter */
 121 #define BIDT_KLESI      0x0103  /* KLESI-B (DWBLA) adapter */
 122 #define BIDT_HSB70      0x4104  /* HSB70 */
 123 #define BIDT_KA820      0x0105  /* KA820 CPU */
 124 #define BIDT_DB88       0x0106  /* DB88 (NBI) adapter */
 125 #define BIDT_DWMBA      0x2107  /* XMI-BI (XBI) adapter */
 126 #define BIDT_DWMBB      0x0107  /* XMI-BI (XBI) adapter */
 127 #define BIDT_CIBCA      0x0108  /* Computer Interconnect adapter */
 128 #define BIDT_DMB32      0x0109  /* DMB32 (COMB) adapter */
 129 #define BIDT_BAA        0x010a  /* BAA */
 130 #define BIDT_CIBCI      0x010b  /* Computer Interconnect adapter (old) */
 131 #define BIDT_DEBNT      0x410b  /* (AIE_TK70) Ethernet+TK50/TBK70  */
 132 #define BIDT_KA800      0x010c  /* KA800 (ACP) slave processor */
 133 #define BIDT_KFBTA      0x410d  /* RD/RX disk controller */
 134 #define BIDT_KDB50      0x010e  /* KDB50 (BDA) disk controller */
 135 #define BIDT_DEBNK      0x410e  /* (AIE_TK) BI Ethernet (Lance) + TK50 */
 136 #define BIDT_DEBNA      0x410f  /* (AIE) BI Ethernet (Lance) adapter */
 137 #define BIDT_DEBNI      0x0118  /* (XNA) BI Ethernet adapter */
 138
 139
 140 /* bits in bi_csr */
 141 #define BICSR_IREV(x)   ((u_char)((x) >> 24))   /* VAXBI interface rev */
 142 #define BICSR_TYPE(x)   ((u_char)((x) >> 16))   /* BIIC type */
 143 #define BICSR_HES       0x8000          /* hard error summary */
 144 #define BICSR_SES       0x4000          /* soft error summary */
 145 #define BICSR_INIT      0x2000          /* initialise node */
 146 #define BICSR_BROKE     0x1000          /* broke */
 147 #define BICSR_STS       0x0800          /* self test status */
 148 #define BICSR_NRST      0x0400          /* node reset */
 149 #define BICSR_UWP       0x0100          /* unlock write pending */
 150 #define BICSR_HEIE      0x0080          /* hard error interrupt enable */
 151 #define BICSR_SEIE      0x0040          /* soft error interrupt enable */
 152 #define BICSR_ARB_MASK  0x0030          /* mask to get arbitration codes */
 153 #define BICSR_ARB_NONE  0x0030          /* no arbitration */
 154 #define BICSR_ARB_LOG   0x0020          /* low priority */
 155 #define BICSR_ARB_HIGH  0x0010          /* high priority */
 156 #define BICSR_ARB_RR    0x0000          /* round robin */
 157 #define BICSR_NODEMASK  0x000f          /* node ID */
 158
 159 #define BICSR_BITS \
 160 "\20\20HES\17SES\16INIT\15BROKE\14STS\13NRST\11UWP\10HEIE\7SEIE"
 161
 162 /* bits in bi_ber */
 163 #define BIBER_MBZ       0x8000fff0
 164 #define BIBER_NMR       0x40000000      /* no ack to multi-responder command */
 165 #define BIBER_MTCE      0x20000000      /* master transmit check error */
 166 #define BIBER_CTE       0x10000000      /* control transmit error */
 167 #define BIBER_MPE       0x08000000      /* master parity error */
 168 #define BIBER_ISE       0x04000000      /* interlock sequence error */
 169 #define BIBER_TDF       0x02000000      /* transmitter during fault */
 170 #define BIBER_IVE       0x01000000      /* ident vector error */
 171 #define BIBER_CPE       0x00800000      /* command parity error */
 172 #define BIBER_SPE       0x00400000      /* slave parity error */
 173 #define BIBER_RDS       0x00200000      /* read data substitute */
 174 #define BIBER_RTO       0x00100000      /* retry timeout */
 175 #define BIBER_STO       0x00080000      /* stall timeout */
 176 #define BIBER_BTO       0x00040000      /* bus timeout */
 177 #define BIBER_NEX       0x00020000      /* nonexistent address */
 178 #define BIBER_ICE       0x00010000      /* illegal confirmation error */
 179 #define BIBER_UPEN      0x00000008      /* user parity enable */
 180 #define BIBER_IPE       0x00000004      /* ID parity error */
 181 #define BIBER_CRD       0x00000002      /* corrected read data */
 182 #define BIBER_NPE       0x00000001      /* null bus parity error */
 183 #define BIBER_HARD      0x4fff0000
 184
 185 #define BIBER_BITS \
 186 "\20\37NMR\36MTCE\35CTE\34MPE\33ISE\32TDF\31IVE\30CPE\
 187 \27SPE\26RDS\25RTO\24STO\23BTO\22NEX\21ICE\4UPEN\3IPE\2CRD\1NPE"
 188
 189 /* bits in bi_eintrcsr */
 190 #define BIEIC_INTRAB    0x01000000      /* interrupt abort */
 191 #define BIEIC_INTRC     0x00800000      /* interrupt complete */
 192 #define BIEIC_INTRSENT  0x00200000      /* interrupt command sent */
 193 #define BIEIC_INTRFORCE 0x00100000      /* interrupt force */
 194 #define BIEIC_LEVELMASK 0x000f0000      /* mask for interrupt levels */
 195 #define BIEIC_IPL17     0x00080000      /* ipl 0x17 */
 196 #define BIEIC_IPL16     0x00040000      /* ipl 0x16 */
 197 #define BIEIC_IPL15     0x00020000      /* ipl 0x15 */
 198 #define BIEIC_IPL14     0x00010000      /* ipl 0x14 */
 199 #define BIEIC_VECMASK   0x00003ffc      /* vector mask for error intr */
 200
 201 /* bits in bi_intrdes */
 202 #define BIDEST_MASK     0x0000ffff      /* one bit per node to be intr'ed */
 203
 204 /* bits in bi_ipintrmsk */
 205 #define BIIPINTR_MASK   0xffff0000      /* one per node to allow to ipintr */
 206
 207 /* bits in bi_fipsdes */
 208 #define BIFIPSD_MASK    0x0000ffff
 209
 210 /* bits in bi_ipintrsrc */
 211 #define BIIPSRC_MASK    0xffff0000
 212
 213 /* sadr and eadr are simple addresses */
 214
 215 /* bits in bi_bcicsr */
 216 #define BCI_BURSTEN     0x00020000      /* burst mode enable */
 217 #define BCI_IPSTOP_FRC  0x00010000      /* ipintr/stop force */
 218 #define BCI_MCASTEN     0x00008000      /* multicast space enable */
 219 #define BCI_BCASTEN     0x00004000      /* broadcast enable */
 220 #define BCI_STOPEN      0x00002000      /* stop enable */
 221 #define BCI_RSRVDEN     0x00001000      /* reserved enable */
 222 #define BCI_IDENTEN     0x00000800      /* ident enable */
 223 #define BCI_INVALEN     0x00000400      /* inval enable */
 224 #define BCI_WINVEN      0x00000200      /* write invalidate enable */
 225 #define BCI_UINTEN      0x00000100      /* user interface csr space enable */
 226 #define BCI_BIICEN      0x00000080      /* BIIC csr space enable */
 227 #define BCI_INTEN       0x00000040      /* interrupt enable */
 228 #define BCI_IPINTEN     0x00000020      /* ipintr enable */
 229 #define BCI_PIPEEN      0x00000010      /* pipeline NXT enable */
 230 #define BCI_RTOEVEN     0x00000008      /* read timeout EV enable */
 231
 232 #define BCI_BITS \
 233 "\20\22BURSTEN\21IPSTOP_FRC\20MCASTEN\
 234 \17BCASTEN\16STOPEN\15RSRVDEN\14IDENTEN\13INVALEN\12WINVEN\11UINTEN\
 235 \10BIICEN\7INTEN\6IPINTEN\5PIPEEN\4RTOEVEN"
 236
 237 /* bits in bi_wstat */
 238 #define BIW_GPR3        0x80000000      /* gpr 3 was written */
 239 #define BIW_GPR2        0x40000000      /* gpr 2 was written */
 240 #define BIW_GPR1        0x20000000      /* gpr 1 was written */
 241 #define BIW_GPR0        0x10000000      /* gpr 0 was written */
 242
 243 /* bits in force-bit ipintr/stop command register */
 244 #define BIFIPSC_CMDMASK 0x0000f000      /* command */
 245 #define BIFIPSC_MIDEN   0x00000800      /* master ID enable */
 246
 247 /* bits in bi_uintcsr */
 248 #define BIUI_INTAB      0xf0000000      /* interrupt abort level */
 249 #define BIUI_INTC       0x0f000000      /* interrupt complete bits */
 250 #define BIUI_SENT       0x00f00000      /* interrupt sent bits */
 251 #define BIUI_FORCE      0x000f0000      /* force interrupt level */
 252 #define BIUI_EVECEN     0x00008000      /* external vector enable */
 253 #define BIUI_VEC        0x00003ffc      /* interrupt vector */
 254
 255 /* tell if a bi device is a slave (hence has SOSR) */
 256 #define BIDT_ISSLAVE(x) (((x) & 0x7f00) == 0)
 257
 258 /* bits in bi_sosr */
 259 #define BISOSR_MEMSIZE  0x1ffc0000      /* memory size */
 260 #define BISOSR_BROKE    0x00001000      /* broke */
 261
 262 /* bits in bi_rxcd */
 263 #define BIRXCD_BUSY2    0x80000000      /* busy 2 */
 264 #define BIRXCD_NODE2    0x0f000000      /* node id 2 */
 265 #define BIRXCD_CHAR2    0x00ff0000      /* character 2 */
 266 #define BIRXCD_BUSY1    0x00008000      /* busy 1 */
 267 #define BIRXCD_NODE1    0x00000f00      /* node id 1 */
 268 #define BIRXCD_CHAR1    0x000000ff      /* character 1 */