sys/dev/ic/adwmcode.h

   1 /*      $NetBSD: adwmcode.h,v 1.8.2.2 2005/03/04 16:41:25 skrll Exp $        */
   2
   3 /*
   4  * Generic driver definitions and exported functions for the Advanced
   5  * Systems Inc. SCSI controllers
   6  *
   7  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
   8  * All rights reserved.
   9  *
  10  * Author: Baldassare Dante Profeta <dante@mclink.it>
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *      This product includes software developed by the NetBSD
  23  *      Foundation, Inc. and its contributors.
  24  * 4. Neither the name of The NetBSD Foundation nor the names of its
  25  *    contributors may be used to endorse or promote products derived
  26  *    from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38  * POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef ADW_MCODE_H
  42 #define ADW_MCODE_H
  43
  44 /******************************************************************************/
  45
  46 #define ADW_MAX_CARRIER 253     /* Max. number of host commands (253) */
  47
  48 /*
  49  * ADW_CARRIER must be exactly 16 BYTES
  50  * Every adw_carrier structure _MUST_ always be aligned on a 16 bytes boundary
  51  */
  52 struct adw_carrier {
  53 /* ---------- the microcode wants the field below ---------- */
  54         u_int32_t       carr_id;  /* Carrier ID */
  55         u_int32_t       carr_ba;  /* Carrier Bus Address */
  56         u_int32_t       areq_ba;  /* ADW_SCSI_REQ_Q Bus Address */
  57         /*
  58          * next_ba [31:4]       Carrier Physical Next Pointer
  59          *
  60          * next_ba [3:1]        Reserved Bits
  61          * next_ba [0]          Done Flag set in Response Queue.
  62          */
  63         u_int32_t       next_ba;  /* see next_ba flags below */
  64 /* ----------                                     ---------- */
  65 };
  66
  67 typedef struct adw_carrier ADW_CARRIER;
  68
  69 /*
  70  * next_ba flags
  71  */
  72 #define ASC_RQ_DONE             0x00000001
  73 #define ASC_RQ_GOOD             0x00000002
  74 #define ASC_CQ_STOPPER          0x00000000
  75
  76 /*
  77  * Mask used to eliminate low 4 bits of carrier 'next_ba' field.
  78  */
  79 #define ASC_NEXT_BA_MASK        0xFFFFFFF0
  80 #define ASC_GET_CARRP(carrp)    htole32((le32toh(carrp)) & ASC_NEXT_BA_MASK)
  81
  82 /*
  83  * Bus Address of a Carrier.
  84  * ba = base_ba + v_address - base_va
  85  */
  86 #define ADW_CARRIER_BADDR(dmamap, carriers, x)  \
  87         htole32((dmamap)->dm_segs[0].ds_addr + ((u_long)x - (u_long)(carriers)))
  88 /*
  89  * Virtual Address of a Carrier.
  90  * va = base_va + bus_address - base_ba
  91  */
  92 #define ADW_CARRIER_VADDR(sc, x)        ((ADW_CARRIER *) \
  93                         (((u_int8_t *)(sc)->sc_control->carriers) + \
  94                         le32toh((u_long)x) - \
  95                         (sc)->sc_dmamap_carrier->dm_segs[0].ds_addr))
  96
  97 /******************************************************************************/
  98
  99 struct adw_mcode {
 100         const u_int8_t  * const mcode_data;
 101         const u_int32_t  mcode_chksum;
 102         const u_int16_t  mcode_size;
 103 };
 104
 105
 106 /******************************************************************************/
 107
 108 /*
 109  * Fixed locations of microcode operating variables.
 110  */
 111 #define ADW_MC_CODE_BEGIN_ADDR          0x0028 /* microcode start address */
 112 #define ADW_MC_CODE_END_ADDR            0x002A /* microcode end address */
 113 #define ADW_MC_CODE_CHK_SUM             0x002C /* microcode code checksum */
 114 #define ADW_MC_VERSION_DATE             0x0038 /* microcode version */
 115 #define ADW_MC_VERSION_NUM              0x003A /* microcode number */
 116 #define ADW_MC_BIOSMEM                  0x0040 /* BIOS RISC Memory Start */
 117 #define ADW_MC_BIOSLEN                  0x0050 /* BIOS RISC Memory Length */
 118 #define ADW_MC_BIOS_SIGNATURE           0x0058 /* BIOS Signature 0x55AA */
 119 #define ADW_MC_BIOS_VERSION             0x005A /* BIOS Version (2 bytes) */
 120
 121 #define ADW_MC_SDTR_SPEED1              0x0090 /* SDTR Speed for TID 0-3 */
 122 #define ADW_MC_SDTR_SPEED2              0x0092 /* SDTR Speed for TID 4-7 */
 123 #define ADW_MC_SDTR_SPEED3              0x0094 /* SDTR Speed for TID 8-11 */
 124 #define ADW_MC_SDTR_SPEED4              0x0096 /* SDTR Speed for TID 12-15 */
 125                                         /*
 126                                          * 4-bit speed  SDTR speed name
 127                                          * ===========  ===============
 128                                          * 0000b (0x0)  SDTR disabled
 129                                          * 0001b (0x1)  5 MHz
 130                                          * 0010b (0x2)  10 MHz
 131                                          * 0011b (0x3)  20 MHz (Ultra)
 132                                          * 0100b (0x4)  40 MHz (LVD/Ultra2)
 133                                          * 0101b (0x5)  80 MHz (LVD2/Ultra3)
 134                                          * 0110b (0x6)  Undefined
 135                                          * ...
 136                                          * 1111b (0xF)  Undefined
 137                                          */
 138 #define ADW_MC_CHIP_TYPE                0x009A
 139 #define ADW_MC_INTRB_CODE               0x009B
 140 #define ADW_MC_WDTR_ABLE                0x009C
 141 #define ADW_MC_SDTR_ABLE                0x009E
 142 #define ADW_MC_TAGQNG_ABLE              0x00A0
 143 #define ADW_MC_DISC_ENABLE              0x00A2
 144 #define ADW_MC_IDLE_CMD_STATUS          0x00A4
 145 #define ADW_MC_IDLE_CMD                 0x00A6
 146 #define ADW_MC_IDLE_CMD_PARAMETER       0x00A8
 147 #define ADW_MC_DEFAULT_SCSI_CFG0        0x00AC
 148 #define ADW_MC_DEFAULT_SCSI_CFG1        0x00AE
 149 #define ADW_MC_DEFAULT_MEM_CFG          0x00B0
 150 #define ADW_MC_DEFAULT_SEL_MASK         0x00B2
 151 #define ADW_MC_SDTR_DONE                0x00B6
 152 #define ADW_MC_NUMBER_OF_QUEUED_CMD     0x00C0
 153 #define ADW_MC_NUMBER_OF_MAX_CMD        0x00D0
 154 #define ADW_MC_DEVICE_HSHK_CFG_TABLE    0x0100
 155 #define ADW_MC_CONTROL_FLAG             0x0122 /* Microcode control flag. */
 156 #define ADW_MC_WDTR_DONE                0x0124
 157 #define ADW_MC_CAM_MODE_MASK            0x015E /* CAM mode TID bitmask. */
 158 #define ADW_MC_ICQ                      0x0160
 159 #define ADW_MC_IRQ                      0x0164
 160 #define ADW_MC_PPR_ABLE                 0x017A
 161
 162
 163 /*
 164  * Microcode Control Flags
 165  *
 166  * Flags set by the Adw Library in RISC variable 'control_flag' (0x122)
 167  * and handled by the microcode.
 168  */
 169 #define CONTROL_FLAG_IGNORE_PERR        0x0001 /* Ignore DMA Parity Errors */
 170 #define CONTROL_FLAG_ENABLE_AIPP        0x0002 /* Enabled AIPP checking. */
 171
 172
 173 /*
 174  * ADW_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
 175  */
 176 #define HSHK_CFG_WIDE_XFR       0x8000
 177 #define HSHK_CFG_RATE           0x0F00
 178 #define HSHK_CFG_OFFSET         0x001F
 179
 180 #define ADW_DEF_MAX_HOST_QNG    0xFD /* Max. number of host commands (253) */
 181 #define ADW_DEF_MIN_HOST_QNG    0x10 /* Min. number of host commands (16) */
 182 #define ADW_DEF_MAX_DVC_QNG     0x3F /* Max. number commands per device (63) */
 183 #define ADW_DEF_MIN_DVC_QNG     0x04 /* Min. number commands per device (4) */
 184
 185 #define ADW_QC_DATA_CHECK       0x01 /* Require ADW_QC_DATA_OUT set or clear. */
 186 #define ADW_QC_DATA_OUT         0x02 /* Data out DMA transfer. */
 187 #define ADW_QC_START_MOTOR      0x04 /* Send auto-start motor before request. */
 188 #define ADW_QC_NO_OVERRUN       0x08 /* Don't report overrun. */
 189 #define ADW_QC_FREEZE_TIDQ      0x10 /* Freeze TID queue after request.XXX TBD*/
 190
 191 #define ADW_QSC_NO_DISC         0x01 /* Don't allow disconnect for request. */
 192 #define ADW_QSC_NO_TAGMSG       0x02 /* Don't allow tag queuing for request. */
 193 #define ADW_QSC_NO_SYNC         0x04 /* Don't use Synch. transfer on request. */
 194 #define ADW_QSC_NO_WIDE         0x08 /* Don't use Wide transfer on request. */
 195 #define ADW_QSC_REDO_DTR        0x10 /* Renegotiate WDTR/SDTR before request. */
 196 /*
 197  * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or
 198  * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
 199  */
 200 #define ADW_QSC_HEAD_TAG        0x40 /* Use Head Tag Message (0x21). */
 201 #define ADW_QSC_ORDERED_TAG     0x80 /* Use Ordered Tag Message (0x22). */
 202
 203
 204 /******************************************************************************/
 205
 206 ADW_CARRIER *AdwInitCarriers(bus_dmamap_t, ADW_CARRIER *);
 207
 208 extern const struct adw_mcode adw_asc3550_mcode_data;
 209 extern const struct adw_mcode adw_asc38C0800_mcode_data;
 210 extern const struct adw_mcode adw_asc38C1600_mcode_data;
 211
 212 /******************************************************************************/
 213
 214 #endif  /* ADW_MCODE_H */