sys/dev/ic/ahcisatavar.h

   1 /*      $NetBSD: ahcisatavar.h,v 1.3 2008/02/11 08:23:48 xtraeme Exp $  */
   2
   3 /*
   4  * Copyright (c) 2006 Manuel Bouyer.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Manuel Bouyer.
  17  * 4. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  */
  32
  33 #include <dev/ic/ahcisatareg.h>
  34
  35 #define AHCI_DEBUG
  36
  37 #define DEBUG_INTR   0x01
  38 #define DEBUG_XFERS  0x02
  39 #define DEBUG_FUNCS  0x08
  40 #define DEBUG_PROBE  0x10
  41 #define DEBUG_DETACH 0x20
  42 #ifdef AHCI_DEBUG
  43 extern int ahcidebug_mask;
  44 #define AHCIDEBUG_PRINT(args, level) \
  45         if (ahcidebug_mask & (level)) \
  46                 printf args
  47 #else
  48 #define AHCIDEBUG_PRINT(args, level)
  49 #endif
  50
  51 struct ahci_softc {
  52         struct atac_softc sc_atac;
  53         bus_space_tag_t sc_ahcit; /* ahci registers mapping */
  54         bus_space_handle_t sc_ahcih;
  55         bus_dma_tag_t sc_dmat; /* DMA memory mappings: */
  56         void *sc_cmd_hdr; /* command tables and received FIS */
  57         bus_dmamap_t sc_cmd_hdrd;
  58         int sc_atac_capflags;
  59
  60         int sc_ncmds; /* number of command slots */
  61         struct ata_channel *sc_chanarray[AHCI_MAX_PORTS];
  62         struct ahci_channel {
  63                 struct ata_channel ata_channel; /* generic part */
  64                 bus_space_handle_t ahcic_scontrol;
  65                 bus_space_handle_t ahcic_sstatus;
  66                 bus_space_handle_t ahcic_serror;
  67                 /* pointers allocated from sc_cmd_hdrd */
  68                 struct ahci_r_fis *ahcic_rfis; /* received FIS */
  69                 bus_addr_t ahcic_bus_rfis;
  70                 struct ahci_cmd_header *ahcic_cmdh; /* command headers */
  71                 bus_addr_t ahcic_bus_cmdh;
  72                 /* command tables (allocated per-channel) */
  73                 bus_dmamap_t ahcic_cmd_tbld;
  74                 struct ahci_cmd_tbl *ahcic_cmd_tbl[AHCI_MAX_CMDS];
  75                 bus_addr_t ahcic_bus_cmd_tbl[AHCI_MAX_CMDS];
  76                 bus_dmamap_t ahcic_datad[AHCI_MAX_CMDS];
  77                 u_int32_t  ahcic_cmds_active; /* active commands */
  78         } sc_channels[AHCI_MAX_PORTS];
  79 };
  80
  81 #define AHCINAME(sc) (device_xname((sc)->sc_atac.atac_dev))
  82
  83 #define AHCI_CMDH_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
  84     (sc)->sc_cmd_hdrd, \
  85     (char *)(&(achp)->ahcic_cmdh[(cmd)]) - (char *)(sc)->sc_cmd_hdr, \
  86     sizeof(struct ahci_cmd_header), (op))
  87 #define AHCI_RFIS_SYNC(sc, achp, op) bus_dmamap_sync((sc)->sc_dmat, \
  88     (sc)->sc_cmd_hdrd, (void *)(achp)->ahcic_rfis - (sc)->sc_cmd_hdr, \
  89     AHCI_RFIS_SIZE, (op))
  90 #define AHCI_CMDTBL_SYNC(sc, achp, cmd, op) bus_dmamap_sync((sc)->sc_dmat, \
  91     (achp)->ahcic_cmd_tbld, AHCI_CMDTBL_SIZE * (cmd), \
  92     AHCI_CMDTBL_SIZE, (op))
  93
  94 #define AHCI_READ(sc, reg) bus_space_read_4((sc)->sc_ahcit, \
  95     (sc)->sc_ahcih, (reg))
  96 #define AHCI_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_ahcit, \
  97     (sc)->sc_ahcih, (reg), (val))
  98
  99
 100 void ahci_attach(struct ahci_softc *);
 101 void ahci_enable_intrs(struct ahci_softc *);
 102 int  ahci_reset(struct ahci_softc *);
 103 void ahci_setup_ports(struct ahci_softc *);
 104 void ahci_reprobe_drives(struct ahci_softc *);
 105
 106 int  ahci_intr(void *);
 107