1 /* $NetBSD: hme.c,v 1.83 2009/09/19 04:55:45 tsutsui Exp $ */
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
33 * HME Ethernet module driver.
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.83 2009/09/19 04:55:45 tsutsui Exp $");
39 /* #define HMEDEBUG */
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
49 #include <sys/syslog.h>
50 #include <sys/socket.h>
51 #include <sys/device.h>
52 #include <sys/malloc.h>
53 #include <sys/ioctl.h>
54 #include <sys/errno.h>
60 #include <net/if_dl.h>
61 #include <net/if_ether.h>
62 #include <net/if_media.h>
65 #include <net/if_vlanvar.h>
66 #include <netinet/in.h>
67 #include <netinet/if_inarp.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/in_var.h>
70 #include <netinet/ip.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
78 #include <net/bpfdesc.h>
81 #include <dev/mii/mii.h>
82 #include <dev/mii/miivar.h>
86 #include <dev/ic/hmereg.h>
87 #include <dev/ic/hmevar.h>
89 static void hme_start(struct ifnet
*);
90 static void hme_stop(struct ifnet
*, int);
91 static int hme_ioctl(struct ifnet
*, u_long
, void *);
92 static void hme_tick(void *);
93 static void hme_watchdog(struct ifnet
*);
94 static bool hme_shutdown(device_t
, int);
95 static int hme_init(struct ifnet
*);
96 static void hme_meminit(struct hme_softc
*);
97 static void hme_mifinit(struct hme_softc
*);
98 static void hme_reset(struct hme_softc
*);
99 static void hme_chipreset(struct hme_softc
*);
100 static void hme_setladrf(struct hme_softc
*);
102 /* MII methods & callbacks */
103 static int hme_mii_readreg(device_t
, int, int);
104 static void hme_mii_writereg(device_t
, int, int, int);
105 static void hme_mii_statchg(device_t
);
107 static int hme_mediachange(struct ifnet
*);
109 static struct mbuf
*hme_get(struct hme_softc
*, int, uint32_t);
110 static int hme_put(struct hme_softc
*, int, struct mbuf
*);
111 static void hme_read(struct hme_softc
*, int, uint32_t);
112 static int hme_eint(struct hme_softc
*, u_int
);
113 static int hme_rint(struct hme_softc
*);
114 static int hme_tint(struct hme_softc
*);
117 /* Default buffer copy routines */
118 static void hme_copytobuf_contig(struct hme_softc
*, void *, int, int);
119 static void hme_copyfrombuf_contig(struct hme_softc
*, void *, int, int);
123 hme_config(struct hme_softc
*sc
)
125 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
126 struct mii_data
*mii
= &sc
->sc_mii
;
127 struct mii_softc
*child
;
128 bus_dma_tag_t dmatag
= sc
->sc_dmatag
;
129 bus_dma_segment_t seg
;
134 * HME common initialization.
136 * hme_softc fields that must be initialized by the front-end:
145 * sc_seb (Shared Ethernet Block registers)
146 * sc_erx (Receiver Unit registers)
147 * sc_etx (Transmitter Unit registers)
148 * sc_mac (MAC registers)
149 * sc_mif (Management Interface registers)
151 * the maximum bus burst size:
154 * (notyet:DMA capable memory for the ring descriptors & packet buffers:
155 * rb_membase, rb_dmabase)
157 * the local Ethernet address:
162 /* Make sure the chip is stopped. */
166 * Allocate descriptors and buffers
167 * XXX - do all this differently.. and more configurably,
168 * eg. use things as `dma_load_mbuf()' on transmit,
169 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped
170 * all the time) on the receiver side.
172 * Note: receive buffers must be 64-byte aligned.
173 * Also, apparently, the buffers must extend to a DMA burst
174 * boundary beyond the maximum packet size.
176 #define _HME_NDESC 128
177 #define _HME_BUFSZ 1600
179 /* Note: the # of descriptors must be a multiple of 16 */
180 sc
->sc_rb
.rb_ntbuf
= _HME_NDESC
;
181 sc
->sc_rb
.rb_nrbuf
= _HME_NDESC
;
184 * Allocate DMA capable memory
185 * Buffer descriptors must be aligned on a 2048 byte boundary;
186 * take this into account when calculating the size. Note that
187 * the maximum number of descriptors (256) occupies 2048 bytes,
188 * so we allocate that much regardless of _HME_NDESC.
190 size
= 2048 + /* TX descriptors */
191 2048 + /* RX descriptors */
192 sc
->sc_rb
.rb_ntbuf
* _HME_BUFSZ
+ /* TX buffers */
193 sc
->sc_rb
.rb_nrbuf
* _HME_BUFSZ
; /* RX buffers */
195 /* Allocate DMA buffer */
196 if ((error
= bus_dmamem_alloc(dmatag
, size
,
198 &seg
, 1, &rseg
, BUS_DMA_NOWAIT
)) != 0) {
199 aprint_error_dev(sc
->sc_dev
, "DMA buffer alloc error %d\n",
204 /* Map DMA memory in CPU addressable space */
205 if ((error
= bus_dmamem_map(dmatag
, &seg
, rseg
, size
,
206 &sc
->sc_rb
.rb_membase
,
207 BUS_DMA_NOWAIT
|BUS_DMA_COHERENT
)) != 0) {
208 aprint_error_dev(sc
->sc_dev
, "DMA buffer map error %d\n",
210 bus_dmamap_unload(dmatag
, sc
->sc_dmamap
);
211 bus_dmamem_free(dmatag
, &seg
, rseg
);
215 if ((error
= bus_dmamap_create(dmatag
, size
, 1, size
, 0,
216 BUS_DMA_NOWAIT
, &sc
->sc_dmamap
)) != 0) {
217 aprint_error_dev(sc
->sc_dev
, "DMA map create error %d\n",
222 /* Load the buffer */
223 if ((error
= bus_dmamap_load(dmatag
, sc
->sc_dmamap
,
224 sc
->sc_rb
.rb_membase
, size
, NULL
,
225 BUS_DMA_NOWAIT
|BUS_DMA_COHERENT
)) != 0) {
226 aprint_error_dev(sc
->sc_dev
, "DMA buffer map load error %d\n",
228 bus_dmamem_free(dmatag
, &seg
, rseg
);
231 sc
->sc_rb
.rb_dmabase
= sc
->sc_dmamap
->dm_segs
[0].ds_addr
;
233 aprint_normal_dev(sc
->sc_dev
, "Ethernet address %s\n",
234 ether_sprintf(sc
->sc_enaddr
));
236 /* Initialize ifnet structure. */
237 strlcpy(ifp
->if_xname
, device_xname(sc
->sc_dev
), IFNAMSIZ
);
239 ifp
->if_start
= hme_start
;
240 ifp
->if_stop
= hme_stop
;
241 ifp
->if_ioctl
= hme_ioctl
;
242 ifp
->if_init
= hme_init
;
243 ifp
->if_watchdog
= hme_watchdog
;
245 IFF_BROADCAST
| IFF_SIMPLEX
| IFF_NOTRAILERS
| IFF_MULTICAST
;
246 sc
->sc_if_flags
= ifp
->if_flags
;
247 ifp
->if_capabilities
|=
248 IFCAP_CSUM_TCPv4_Tx
| IFCAP_CSUM_TCPv4_Rx
|
249 IFCAP_CSUM_UDPv4_Tx
| IFCAP_CSUM_UDPv4_Rx
;
250 IFQ_SET_READY(&ifp
->if_snd
);
252 /* Initialize ifmedia structures and MII info */
254 mii
->mii_readreg
= hme_mii_readreg
;
255 mii
->mii_writereg
= hme_mii_writereg
;
256 mii
->mii_statchg
= hme_mii_statchg
;
258 sc
->sc_ethercom
.ec_mii
= mii
;
259 ifmedia_init(&mii
->mii_media
, 0, hme_mediachange
, ether_mediastatus
);
264 * Some HME's have an MII connector, as well as RJ45. Try attaching
265 * the RJ45 (internal) PHY first, so that the MII PHY is always
268 mii_attach(sc
->sc_dev
, mii
, 0xffffffff,
269 HME_PHYAD_INTERNAL
, MII_OFFSET_ANY
, MIIF_FORCEANEG
);
270 mii_attach(sc
->sc_dev
, mii
, 0xffffffff,
271 HME_PHYAD_EXTERNAL
, MII_OFFSET_ANY
, MIIF_FORCEANEG
);
273 child
= LIST_FIRST(&mii
->mii_phys
);
275 /* No PHY attached */
276 ifmedia_add(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_MANUAL
, 0, NULL
);
277 ifmedia_set(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_MANUAL
);
280 * Walk along the list of attached MII devices and
281 * establish an `MII instance' to `phy number'
282 * mapping. We'll use this mapping in media change
283 * requests to determine which phy to use to program
284 * the MIF configuration register.
286 for (; child
!= NULL
; child
= LIST_NEXT(child
, mii_list
)) {
288 * Note: we support just two PHYs: the built-in
289 * internal device and an external on the MII
292 if (child
->mii_phy
> 1 || child
->mii_inst
> 1) {
293 aprint_error_dev(sc
->sc_dev
,
294 "cannot accommodate MII device %s"
295 " at phy %d, instance %d\n",
296 device_xname(child
->mii_dev
),
297 child
->mii_phy
, child
->mii_inst
);
301 sc
->sc_phys
[child
->mii_inst
] = child
->mii_phy
;
305 * Set the default media to auto negotiation if the phy has
306 * the auto negotiation capability.
307 * XXX; What to do otherwise?
309 if (ifmedia_match(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_AUTO
, 0))
310 ifmedia_set(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_AUTO
);
313 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia);
317 /* claim 802.1q capability */
318 sc
->sc_ethercom
.ec_capabilities
|= ETHERCAP_VLAN_MTU
;
320 /* Attach the interface. */
322 ether_ifattach(ifp
, sc
->sc_enaddr
);
324 if (pmf_device_register1(sc
->sc_dev
, NULL
, NULL
, hme_shutdown
))
325 pmf_class_network_register(sc
->sc_dev
, ifp
);
327 aprint_error_dev(sc
->sc_dev
,
328 "couldn't establish power handler\n");
331 rnd_attach_source(&sc
->rnd_source
, device_xname(sc
->sc_dev
),
335 callout_init(&sc
->sc_tick_ch
, 0);
341 struct hme_softc
*sc
= arg
;
345 mii_tick(&sc
->sc_mii
);
348 callout_reset(&sc
->sc_tick_ch
, hz
, hme_tick
, sc
);
352 hme_reset(struct hme_softc
*sc
)
357 (void)hme_init(&sc
->sc_ethercom
.ec_if
);
362 hme_chipreset(struct hme_softc
*sc
)
364 bus_space_tag_t t
= sc
->sc_bustag
;
365 bus_space_handle_t seb
= sc
->sc_seb
;
368 /* Mask all interrupts */
369 bus_space_write_4(t
, seb
, HME_SEBI_IMASK
, 0xffffffff);
371 /* Reset transmitter and receiver */
372 bus_space_write_4(t
, seb
, HME_SEBI_RESET
,
373 (HME_SEB_RESET_ETX
| HME_SEB_RESET_ERX
));
375 for (n
= 0; n
< 20; n
++) {
376 uint32_t v
= bus_space_read_4(t
, seb
, HME_SEBI_RESET
);
377 if ((v
& (HME_SEB_RESET_ETX
| HME_SEB_RESET_ERX
)) == 0)
382 printf("%s: %s: reset failed\n", device_xname(sc
->sc_dev
), __func__
);
386 hme_stop(struct ifnet
*ifp
, int disable
)
388 struct hme_softc
*sc
;
393 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
395 callout_stop(&sc
->sc_tick_ch
);
396 mii_down(&sc
->sc_mii
);
402 hme_meminit(struct hme_softc
*sc
)
404 bus_addr_t txbufdma
, rxbufdma
;
407 unsigned int ntbuf
, nrbuf
, i
;
408 struct hme_ring
*hr
= &sc
->sc_rb
;
411 dma
= hr
->rb_dmabase
;
413 ntbuf
= hr
->rb_ntbuf
;
414 nrbuf
= hr
->rb_nrbuf
;
417 * Allocate transmit descriptors
421 p
+= ntbuf
* HME_XD_SIZE
;
422 dma
+= ntbuf
* HME_XD_SIZE
;
423 /* We have reserved descriptor space until the next 2048 byte boundary.*/
424 dma
= (bus_addr_t
)roundup((u_long
)dma
, 2048);
425 p
= (void *)roundup((u_long
)p
, 2048);
428 * Allocate receive descriptors
432 p
+= nrbuf
* HME_XD_SIZE
;
433 dma
+= nrbuf
* HME_XD_SIZE
;
434 /* Again move forward to the next 2048 byte boundary.*/
435 dma
= (bus_addr_t
)roundup((u_long
)dma
, 2048);
436 p
= (void *)roundup((u_long
)p
, 2048);
440 * Allocate transmit buffers
444 p
+= ntbuf
* _HME_BUFSZ
;
445 dma
+= ntbuf
* _HME_BUFSZ
;
448 * Allocate receive buffers
452 p
+= nrbuf
* _HME_BUFSZ
;
453 dma
+= nrbuf
* _HME_BUFSZ
;
456 * Initialize transmit buffer descriptors
458 for (i
= 0; i
< ntbuf
; i
++) {
459 HME_XD_SETADDR(sc
->sc_pci
, hr
->rb_txd
, i
, txbufdma
+ i
* _HME_BUFSZ
);
460 HME_XD_SETFLAGS(sc
->sc_pci
, hr
->rb_txd
, i
, 0);
464 * Initialize receive buffer descriptors
466 for (i
= 0; i
< nrbuf
; i
++) {
467 HME_XD_SETADDR(sc
->sc_pci
, hr
->rb_rxd
, i
, rxbufdma
+ i
* _HME_BUFSZ
);
468 HME_XD_SETFLAGS(sc
->sc_pci
, hr
->rb_rxd
, i
,
469 HME_XD_OWN
| HME_XD_ENCODE_RSIZE(_HME_BUFSZ
));
472 hr
->rb_tdhead
= hr
->rb_tdtail
= 0;
478 * Initialization of interface; set up initialization block
479 * and transmit/receive descriptor rings.
482 hme_init(struct ifnet
*ifp
)
484 struct hme_softc
*sc
= ifp
->if_softc
;
485 bus_space_tag_t t
= sc
->sc_bustag
;
486 bus_space_handle_t seb
= sc
->sc_seb
;
487 bus_space_handle_t etx
= sc
->sc_etx
;
488 bus_space_handle_t erx
= sc
->sc_erx
;
489 bus_space_handle_t mac
= sc
->sc_mac
;
495 * Initialization sequence. The numbered steps below correspond
496 * to the sequence outlined in section 6.3.5.1 in the Ethernet
497 * Channel Engine manual (part of the PCIO manual).
498 * See also the STP2002-STQ document from Sun Microsystems.
501 /* step 1 & 2. Reset the Ethernet Channel */
504 /* Re-initialize the MIF */
507 /* Call MI reset function if any */
509 (*sc
->sc_hwreset
)(sc
);
512 /* Mask all MIF interrupts, just in case */
513 bus_space_write_4(t
, mif
, HME_MIFI_IMASK
, 0xffff);
516 /* step 3. Setup data structures in host memory */
519 /* step 4. TX MAC registers & counters */
520 bus_space_write_4(t
, mac
, HME_MACI_NCCNT
, 0);
521 bus_space_write_4(t
, mac
, HME_MACI_FCCNT
, 0);
522 bus_space_write_4(t
, mac
, HME_MACI_EXCNT
, 0);
523 bus_space_write_4(t
, mac
, HME_MACI_LTCNT
, 0);
524 bus_space_write_4(t
, mac
, HME_MACI_TXSIZE
,
525 (sc
->sc_ethercom
.ec_capenable
& ETHERCAP_VLAN_MTU
) ?
526 ETHER_VLAN_ENCAP_LEN
+ ETHER_MAX_LEN
: ETHER_MAX_LEN
);
527 sc
->sc_ec_capenable
= sc
->sc_ethercom
.ec_capenable
;
529 /* Load station MAC address */
531 bus_space_write_4(t
, mac
, HME_MACI_MACADDR0
, (ea
[0] << 8) | ea
[1]);
532 bus_space_write_4(t
, mac
, HME_MACI_MACADDR1
, (ea
[2] << 8) | ea
[3]);
533 bus_space_write_4(t
, mac
, HME_MACI_MACADDR2
, (ea
[4] << 8) | ea
[5]);
536 * Init seed for backoff
537 * (source suggested by manual: low 10 bits of MAC address)
539 v
= ((ea
[4] << 8) | ea
[5]) & 0x3fff;
540 bus_space_write_4(t
, mac
, HME_MACI_RANDSEED
, v
);
543 /* Note: Accepting power-on default for other MAC registers here.. */
546 /* step 5. RX MAC registers & counters */
549 /* step 6 & 7. Program Descriptor Ring Base Addresses */
550 bus_space_write_4(t
, etx
, HME_ETXI_RING
, sc
->sc_rb
.rb_txddma
);
551 bus_space_write_4(t
, etx
, HME_ETXI_RSIZE
, sc
->sc_rb
.rb_ntbuf
);
553 bus_space_write_4(t
, erx
, HME_ERXI_RING
, sc
->sc_rb
.rb_rxddma
);
554 bus_space_write_4(t
, mac
, HME_MACI_RXSIZE
,
555 (sc
->sc_ethercom
.ec_capenable
& ETHERCAP_VLAN_MTU
) ?
556 ETHER_VLAN_ENCAP_LEN
+ ETHER_MAX_LEN
: ETHER_MAX_LEN
);
558 /* step 8. Global Configuration & Interrupt Mask */
559 bus_space_write_4(t
, seb
, HME_SEBI_IMASK
,
561 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/
562 HME_SEB_STAT_HOSTTOTX
|
563 HME_SEB_STAT_RXTOHOST
|
565 HME_SEB_STAT_TXPERR
|
566 HME_SEB_STAT_RCNTEXP
|
567 HME_SEB_STAT_MIFIRQ
|
568 HME_SEB_STAT_ALL_ERRORS
));
570 switch (sc
->sc_burst
) {
575 v
= HME_SEB_CFG_BURST16
;
578 v
= HME_SEB_CFG_BURST32
;
581 v
= HME_SEB_CFG_BURST64
;
584 bus_space_write_4(t
, seb
, HME_SEBI_CFG
, v
);
586 /* step 9. ETX Configuration: use mostly default values */
589 v
= bus_space_read_4(t
, etx
, HME_ETXI_CFG
);
590 v
|= HME_ETX_CFG_DMAENABLE
;
591 bus_space_write_4(t
, etx
, HME_ETXI_CFG
, v
);
593 /* Transmit Descriptor ring size: in increments of 16 */
594 bus_space_write_4(t
, etx
, HME_ETXI_RSIZE
, _HME_NDESC
/ 16 - 1);
597 /* step 10. ERX Configuration */
598 v
= bus_space_read_4(t
, erx
, HME_ERXI_CFG
);
600 /* Encode Receive Descriptor ring size: four possible values */
601 switch (_HME_NDESC
/*XXX*/) {
603 v
|= HME_ERX_CFG_RINGSIZE32
;
606 v
|= HME_ERX_CFG_RINGSIZE64
;
609 v
|= HME_ERX_CFG_RINGSIZE128
;
612 v
|= HME_ERX_CFG_RINGSIZE256
;
615 printf("hme: invalid Receive Descriptor ring size\n");
620 v
|= HME_ERX_CFG_DMAENABLE
;
622 /* set h/w rx checksum start offset (# of half-words) */
624 v
|= (((ETHER_HDR_LEN
+ sizeof(struct ip
)) / sizeof(uint16_t))
625 << HME_ERX_CFG_CSUMSHIFT
) &
626 HME_ERX_CFG_CSUMSTART
;
628 bus_space_write_4(t
, erx
, HME_ERXI_CFG
, v
);
630 /* step 11. XIF Configuration */
631 v
= bus_space_read_4(t
, mac
, HME_MACI_XIF
);
633 bus_space_write_4(t
, mac
, HME_MACI_XIF
, v
);
635 /* step 12. RX_MAC Configuration Register */
636 v
= bus_space_read_4(t
, mac
, HME_MACI_RXCFG
);
637 v
|= HME_MAC_RXCFG_ENABLE
| HME_MAC_RXCFG_PSTRIP
;
638 bus_space_write_4(t
, mac
, HME_MACI_RXCFG
, v
);
640 /* step 13. TX_MAC Configuration Register */
641 v
= bus_space_read_4(t
, mac
, HME_MACI_TXCFG
);
642 v
|= (HME_MAC_TXCFG_ENABLE
| HME_MAC_TXCFG_DGIVEUP
);
643 bus_space_write_4(t
, mac
, HME_MACI_TXCFG
, v
);
645 /* step 14. Issue Transmit Pending command */
647 /* Call MI initialization function if any */
649 (*sc
->sc_hwinit
)(sc
);
651 /* Set the current media. */
652 if ((rc
= hme_mediachange(ifp
)) != 0)
655 /* Start the one second timer. */
656 callout_reset(&sc
->sc_tick_ch
, hz
, hme_tick
, sc
);
658 ifp
->if_flags
|= IFF_RUNNING
;
659 ifp
->if_flags
&= ~IFF_OACTIVE
;
660 sc
->sc_if_flags
= ifp
->if_flags
;
667 * Routine to copy from mbuf chain to transmit buffer in
668 * network buffer memory.
669 * Returns the amount of data copied.
672 hme_put(struct hme_softc
*sc
, int ri
, struct mbuf
*m
)
679 bp
= (char *)sc
->sc_rb
.rb_txbuf
+ (ri
% sc
->sc_rb
.rb_ntbuf
) * _HME_BUFSZ
;
686 memcpy(bp
, mtod(m
, void *), len
);
695 * Pull data off an interface.
696 * Len is length of data, with local net header stripped.
697 * We copy the data into mbufs. When full cluster sized units are present
698 * we copy into clusters.
701 hme_get(struct hme_softc
*sc
, int ri
, uint32_t flags
)
703 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
704 struct mbuf
*m
, *m0
, *newm
;
711 totlen
= HME_XD_DECODE_RSIZE(flags
);
712 MGETHDR(m0
, M_DONTWAIT
, MT_DATA
);
715 m0
->m_pkthdr
.rcvif
= ifp
;
716 m0
->m_pkthdr
.len
= totlen
;
720 bp
= (char *)sc
->sc_rb
.rb_rxbuf
+ (ri
% sc
->sc_rb
.rb_nrbuf
) * _HME_BUFSZ
;
723 if (totlen
>= MINCLSIZE
) {
724 MCLGET(m
, M_DONTWAIT
);
725 if ((m
->m_flags
& M_EXT
) == 0)
731 char *newdata
= (char *)
732 ALIGN(m
->m_data
+ sizeof(struct ether_header
)) -
733 sizeof(struct ether_header
);
734 len
-= newdata
- m
->m_data
;
738 m
->m_len
= len
= min(totlen
, len
);
739 memcpy(mtod(m
, void *), bp
, len
);
744 MGET(newm
, M_DONTWAIT
, MT_DATA
);
748 m
= m
->m_next
= newm
;
753 /* hardware checksum */
755 if (ifp
->if_csum_flags_rx
& (M_CSUM_TCPv4
| M_CSUM_UDPv4
)) {
756 struct ether_header
*eh
;
757 struct ether_vlan_header
*evh
;
761 int32_t hlen
, pktlen
;
764 eh
= mtod(m0
, struct ether_header
*);
765 if (ntohs(eh
->ether_type
) == ETHERTYPE_IP
) {
766 ip
= (struct ip
*)((char *)eh
+ ETHER_HDR_LEN
);
767 pktlen
= m0
->m_pkthdr
.len
- ETHER_HDR_LEN
;
768 } else if (ntohs(eh
->ether_type
) == ETHERTYPE_VLAN
) {
769 evh
= (struct ether_vlan_header
*)eh
;
770 if (ntohs(evh
->evl_proto
!= ETHERTYPE_IP
))
772 ip
= (struct ip
*)((char *)eh
+ ETHER_HDR_LEN
+
773 ETHER_VLAN_ENCAP_LEN
);
774 pktlen
= m0
->m_pkthdr
.len
-
775 ETHER_HDR_LEN
- ETHER_VLAN_ENCAP_LEN
;
780 if (ip
->ip_v
!= IPVERSION
)
783 hlen
= ip
->ip_hl
<< 2;
784 if (hlen
< sizeof(struct ip
))
788 * bail if too short, has random trailing garbage, truncated,
789 * fragment, or has ethernet pad.
791 if (ntohs(ip
->ip_len
) < hlen
||
792 ntohs(ip
->ip_len
) != pktlen
||
793 (ntohs(ip
->ip_off
) & (IP_MF
| IP_OFFMASK
)) != 0)
798 if ((ifp
->if_csum_flags_rx
& M_CSUM_TCPv4
) == 0)
800 if (pktlen
< (hlen
+ sizeof(struct tcphdr
)))
803 M_CSUM_TCPv4
| M_CSUM_DATA
| M_CSUM_NO_PSEUDOHDR
;
806 if ((ifp
->if_csum_flags_rx
& M_CSUM_UDPv4
) == 0)
808 if (pktlen
< (hlen
+ sizeof(struct udphdr
)))
810 uh
= (struct udphdr
*)((char *)ip
+ hlen
);
815 M_CSUM_UDPv4
| M_CSUM_DATA
| M_CSUM_NO_PSEUDOHDR
;
821 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */
822 csum_data
= ~flags
& HME_XD_RXCKSUM
;
825 * If data offset is different from RX cksum start offset,
826 * we have to deduct them.
828 hlen
= ((char *)ip
+ hlen
) -
829 ((char *)eh
+ ETHER_HDR_LEN
+ sizeof(struct ip
));
834 opts
= (uint16_t *)((char *)eh
+
835 ETHER_HDR_LEN
+ sizeof(struct ip
));
838 optsum
+= ntohs(*opts
++);
842 optsum
= (optsum
>> 16) + (optsum
& 0xffff);
844 /* Deduct the ip opts sum from the hwsum. */
845 csum_data
+= (uint16_t)~optsum
;
847 while (csum_data
>> 16)
849 (csum_data
>> 16) + (csum_data
& 0xffff);
851 m0
->m_pkthdr
.csum_data
= csum_data
;
854 m0
->m_pkthdr
.csum_flags
= csum_flags
;
865 * Pass a packet to the higher levels.
868 hme_read(struct hme_softc
*sc
, int ix
, uint32_t flags
)
870 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
874 len
= HME_XD_DECODE_RSIZE(flags
);
875 if (len
<= sizeof(struct ether_header
) ||
876 len
> ((sc
->sc_ethercom
.ec_capenable
& ETHERCAP_VLAN_MTU
) ?
877 ETHER_VLAN_ENCAP_LEN
+ ETHERMTU
+ sizeof(struct ether_header
) :
878 ETHERMTU
+ sizeof(struct ether_header
))) {
880 printf("%s: invalid packet size %d; dropping\n",
881 device_xname(sc
->sc_dev
), len
);
887 /* Pull packet off interface. */
888 m
= hme_get(sc
, ix
, flags
);
898 * Check if there's a BPF listener on this interface.
899 * If so, hand off the raw packet to BPF.
902 bpf_mtap(ifp
->if_bpf
, m
);
905 /* Pass the packet up. */
906 (*ifp
->if_input
)(ifp
, m
);
910 hme_start(struct ifnet
*ifp
)
912 struct hme_softc
*sc
= ifp
->if_softc
;
913 void *txd
= sc
->sc_rb
.rb_txd
;
915 unsigned int txflags
;
916 unsigned int ri
, len
, obusy
;
917 unsigned int ntbuf
= sc
->sc_rb
.rb_ntbuf
;
919 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_OACTIVE
)) != IFF_RUNNING
)
922 ri
= sc
->sc_rb
.rb_tdhead
;
923 obusy
= sc
->sc_rb
.rb_td_nbusy
;
926 IFQ_DEQUEUE(&ifp
->if_snd
, m
);
932 * If BPF is listening on this interface, let it see the
933 * packet before we commit it to the wire.
936 bpf_mtap(ifp
->if_bpf
, m
);
940 /* collect bits for h/w csum, before hme_put frees the mbuf */
941 if (ifp
->if_csum_flags_tx
& (M_CSUM_TCPv4
| M_CSUM_UDPv4
) &&
942 m
->m_pkthdr
.csum_flags
& (M_CSUM_TCPv4
| M_CSUM_UDPv4
)) {
943 struct ether_header
*eh
;
944 uint16_t offset
, start
;
946 eh
= mtod(m
, struct ether_header
*);
947 switch (ntohs(eh
->ether_type
)) {
949 start
= ETHER_HDR_LEN
;
952 start
= ETHER_HDR_LEN
+ ETHER_VLAN_ENCAP_LEN
;
955 /* unsupported, drop it */
959 start
+= M_CSUM_DATA_IPv4_IPHL(m
->m_pkthdr
.csum_data
);
960 offset
= M_CSUM_DATA_IPv4_OFFSET(m
->m_pkthdr
.csum_data
)
962 txflags
= HME_XD_TXCKSUM
|
963 (offset
<< HME_XD_TXCSSTUFFSHIFT
) |
964 (start
<< HME_XD_TXCSSTARTSHIFT
);
970 * Copy the mbuf chain into the transmit buffer.
972 len
= hme_put(sc
, ri
, m
);
975 * Initialize transmit registers and start transmission
977 HME_XD_SETFLAGS(sc
->sc_pci
, txd
, ri
,
978 HME_XD_OWN
| HME_XD_SOP
| HME_XD_EOP
|
979 HME_XD_ENCODE_TSIZE(len
) | txflags
);
981 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/
982 bus_space_write_4(sc
->sc_bustag
, sc
->sc_etx
, HME_ETXI_PENDING
,
983 HME_ETX_TP_DMAWAKEUP
);
988 if (++sc
->sc_rb
.rb_td_nbusy
== ntbuf
) {
989 ifp
->if_flags
|= IFF_OACTIVE
;
994 if (obusy
!= sc
->sc_rb
.rb_td_nbusy
) {
995 sc
->sc_rb
.rb_tdhead
= ri
;
1001 * Transmit interrupt.
1004 hme_tint(struct hme_softc
*sc
)
1006 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1007 bus_space_tag_t t
= sc
->sc_bustag
;
1008 bus_space_handle_t mac
= sc
->sc_mac
;
1009 unsigned int ri
, txflags
;
1012 * Unload collision counters
1014 ifp
->if_collisions
+=
1015 bus_space_read_4(t
, mac
, HME_MACI_NCCNT
) +
1016 bus_space_read_4(t
, mac
, HME_MACI_FCCNT
);
1018 bus_space_read_4(t
, mac
, HME_MACI_EXCNT
) +
1019 bus_space_read_4(t
, mac
, HME_MACI_LTCNT
);
1022 * then clear the hardware counters.
1024 bus_space_write_4(t
, mac
, HME_MACI_NCCNT
, 0);
1025 bus_space_write_4(t
, mac
, HME_MACI_FCCNT
, 0);
1026 bus_space_write_4(t
, mac
, HME_MACI_EXCNT
, 0);
1027 bus_space_write_4(t
, mac
, HME_MACI_LTCNT
, 0);
1029 /* Fetch current position in the transmit ring */
1030 ri
= sc
->sc_rb
.rb_tdtail
;
1033 if (sc
->sc_rb
.rb_td_nbusy
<= 0)
1036 txflags
= HME_XD_GETFLAGS(sc
->sc_pci
, sc
->sc_rb
.rb_txd
, ri
);
1038 if (txflags
& HME_XD_OWN
)
1041 ifp
->if_flags
&= ~IFF_OACTIVE
;
1044 if (++ri
== sc
->sc_rb
.rb_ntbuf
)
1047 --sc
->sc_rb
.rb_td_nbusy
;
1051 sc
->sc_rb
.rb_tdtail
= ri
;
1055 if (sc
->sc_rb
.rb_td_nbusy
== 0)
1062 * Receive interrupt.
1065 hme_rint(struct hme_softc
*sc
)
1067 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1068 bus_space_tag_t t
= sc
->sc_bustag
;
1069 bus_space_handle_t mac
= sc
->sc_mac
;
1070 void *xdr
= sc
->sc_rb
.rb_rxd
;
1071 unsigned int nrbuf
= sc
->sc_rb
.rb_nrbuf
;
1075 ri
= sc
->sc_rb
.rb_rdtail
;
1078 * Process all buffers with valid data.
1081 flags
= HME_XD_GETFLAGS(sc
->sc_pci
, xdr
, ri
);
1082 if (flags
& HME_XD_OWN
)
1085 if (flags
& HME_XD_OFL
) {
1086 printf("%s: buffer overflow, ri=%d; flags=0x%x\n",
1087 device_xname(sc
->sc_dev
), ri
, flags
);
1089 hme_read(sc
, ri
, flags
);
1091 /* This buffer can be used by the hardware again */
1092 HME_XD_SETFLAGS(sc
->sc_pci
, xdr
, ri
,
1093 HME_XD_OWN
| HME_XD_ENCODE_RSIZE(_HME_BUFSZ
));
1099 sc
->sc_rb
.rb_rdtail
= ri
;
1101 /* Read error counters ... */
1103 bus_space_read_4(t
, mac
, HME_MACI_STAT_LCNT
) +
1104 bus_space_read_4(t
, mac
, HME_MACI_STAT_ACNT
) +
1105 bus_space_read_4(t
, mac
, HME_MACI_STAT_CCNT
) +
1106 bus_space_read_4(t
, mac
, HME_MACI_STAT_CVCNT
);
1108 /* ... then clear the hardware counters. */
1109 bus_space_write_4(t
, mac
, HME_MACI_STAT_LCNT
, 0);
1110 bus_space_write_4(t
, mac
, HME_MACI_STAT_ACNT
, 0);
1111 bus_space_write_4(t
, mac
, HME_MACI_STAT_CCNT
, 0);
1112 bus_space_write_4(t
, mac
, HME_MACI_STAT_CVCNT
, 0);
1117 hme_eint(struct hme_softc
*sc
, u_int status
)
1119 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1122 if ((status
& HME_SEB_STAT_MIFIRQ
) != 0) {
1123 bus_space_tag_t t
= sc
->sc_bustag
;
1124 bus_space_handle_t mif
= sc
->sc_mif
;
1125 uint32_t cf
, st
, sm
;
1126 cf
= bus_space_read_4(t
, mif
, HME_MIFI_CFG
);
1127 st
= bus_space_read_4(t
, mif
, HME_MIFI_STAT
);
1128 sm
= bus_space_read_4(t
, mif
, HME_MIFI_SM
);
1129 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n",
1130 device_xname(sc
->sc_dev
), cf
, st
, sm
);
1134 /* Receive error counters rolled over */
1135 if (status
& HME_SEB_STAT_ACNTEXP
)
1136 ifp
->if_ierrors
+= 0xff;
1137 if (status
& HME_SEB_STAT_CCNTEXP
)
1138 ifp
->if_ierrors
+= 0xff;
1139 if (status
& HME_SEB_STAT_LCNTEXP
)
1140 ifp
->if_ierrors
+= 0xff;
1141 if (status
& HME_SEB_STAT_CVCNTEXP
)
1142 ifp
->if_ierrors
+= 0xff;
1144 /* RXTERR locks up the interface, so do a reset */
1145 if (status
& HME_SEB_STAT_RXTERR
)
1148 snprintb(bits
, sizeof(bits
), HME_SEB_STAT_BITS
, status
);
1149 printf("%s: status=%s\n", device_xname(sc
->sc_dev
), bits
);
1157 struct hme_softc
*sc
= v
;
1158 bus_space_tag_t t
= sc
->sc_bustag
;
1159 bus_space_handle_t seb
= sc
->sc_seb
;
1163 status
= bus_space_read_4(t
, seb
, HME_SEBI_STAT
);
1165 if ((status
& HME_SEB_STAT_ALL_ERRORS
) != 0)
1166 r
|= hme_eint(sc
, status
);
1168 if ((status
& (HME_SEB_STAT_TXALL
| HME_SEB_STAT_HOSTTOTX
)) != 0)
1171 if ((status
& HME_SEB_STAT_RXTOHOST
) != 0)
1175 rnd_add_uint32(&sc
->rnd_source
, status
);
1183 hme_watchdog(struct ifnet
*ifp
)
1185 struct hme_softc
*sc
= ifp
->if_softc
;
1187 log(LOG_ERR
, "%s: device timeout\n", device_xname(sc
->sc_dev
));
1194 * Initialize the MII Management Interface
1197 hme_mifinit(struct hme_softc
*sc
)
1199 bus_space_tag_t t
= sc
->sc_bustag
;
1200 bus_space_handle_t mif
= sc
->sc_mif
;
1201 bus_space_handle_t mac
= sc
->sc_mac
;
1205 if (sc
->sc_mii
.mii_media
.ifm_cur
!= NULL
) {
1206 instance
= IFM_INST(sc
->sc_mii
.mii_media
.ifm_cur
->ifm_media
);
1207 phy
= sc
->sc_phys
[instance
];
1209 /* No media set yet, pick phy arbitrarily.. */
1210 phy
= HME_PHYAD_EXTERNAL
;
1212 /* Configure the MIF in frame mode, no poll, current phy select */
1214 if (phy
== HME_PHYAD_EXTERNAL
)
1215 v
|= HME_MIF_CFG_PHY
;
1216 bus_space_write_4(t
, mif
, HME_MIFI_CFG
, v
);
1218 /* If an external transceiver is selected, enable its MII drivers */
1219 v
= bus_space_read_4(t
, mac
, HME_MACI_XIF
);
1220 v
&= ~HME_MAC_XIF_MIIENABLE
;
1221 if (phy
== HME_PHYAD_EXTERNAL
)
1222 v
|= HME_MAC_XIF_MIIENABLE
;
1223 bus_space_write_4(t
, mac
, HME_MACI_XIF
, v
);
1230 hme_mii_readreg(device_t self
, int phy
, int reg
)
1232 struct hme_softc
*sc
= device_private(self
);
1233 bus_space_tag_t t
= sc
->sc_bustag
;
1234 bus_space_handle_t mif
= sc
->sc_mif
;
1235 bus_space_handle_t mac
= sc
->sc_mac
;
1236 uint32_t v
, xif_cfg
, mifi_cfg
;
1239 /* We can at most have two PHYs */
1240 if (phy
!= HME_PHYAD_EXTERNAL
&& phy
!= HME_PHYAD_INTERNAL
)
1243 /* Select the desired PHY in the MIF configuration register */
1244 v
= mifi_cfg
= bus_space_read_4(t
, mif
, HME_MIFI_CFG
);
1245 v
&= ~HME_MIF_CFG_PHY
;
1246 if (phy
== HME_PHYAD_EXTERNAL
)
1247 v
|= HME_MIF_CFG_PHY
;
1248 bus_space_write_4(t
, mif
, HME_MIFI_CFG
, v
);
1250 /* Enable MII drivers on external transceiver */
1251 v
= xif_cfg
= bus_space_read_4(t
, mac
, HME_MACI_XIF
);
1252 if (phy
== HME_PHYAD_EXTERNAL
)
1253 v
|= HME_MAC_XIF_MIIENABLE
;
1255 v
&= ~HME_MAC_XIF_MIIENABLE
;
1256 bus_space_write_4(t
, mac
, HME_MACI_XIF
, v
);
1259 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */
1261 * Check whether a transceiver is connected by testing
1262 * the MIF configuration register's MDI_X bits. Note that
1263 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h
1265 mif_mdi_bit
= 1 << (8 + (1 - phy
));
1267 v
= bus_space_read_4(t
, mif
, HME_MIFI_CFG
);
1268 if ((v
& mif_mdi_bit
) == 0)
1272 /* Construct the frame command */
1273 v
= (MII_COMMAND_START
<< HME_MIF_FO_ST_SHIFT
) |
1275 (MII_COMMAND_READ
<< HME_MIF_FO_OPC_SHIFT
) |
1276 (phy
<< HME_MIF_FO_PHYAD_SHIFT
) |
1277 (reg
<< HME_MIF_FO_REGAD_SHIFT
);
1279 bus_space_write_4(t
, mif
, HME_MIFI_FO
, v
);
1280 for (n
= 0; n
< 100; n
++) {
1282 v
= bus_space_read_4(t
, mif
, HME_MIFI_FO
);
1283 if (v
& HME_MIF_FO_TALSB
) {
1284 v
&= HME_MIF_FO_DATA
;
1290 printf("%s: mii_read timeout\n", device_xname(sc
->sc_dev
));
1293 /* Restore MIFI_CFG register */
1294 bus_space_write_4(t
, mif
, HME_MIFI_CFG
, mifi_cfg
);
1295 /* Restore XIF register */
1296 bus_space_write_4(t
, mac
, HME_MACI_XIF
, xif_cfg
);
1301 hme_mii_writereg(device_t self
, int phy
, int reg
, int val
)
1303 struct hme_softc
*sc
= device_private(self
);
1304 bus_space_tag_t t
= sc
->sc_bustag
;
1305 bus_space_handle_t mif
= sc
->sc_mif
;
1306 bus_space_handle_t mac
= sc
->sc_mac
;
1307 uint32_t v
, xif_cfg
, mifi_cfg
;
1310 /* We can at most have two PHYs */
1311 if (phy
!= HME_PHYAD_EXTERNAL
&& phy
!= HME_PHYAD_INTERNAL
)
1314 /* Select the desired PHY in the MIF configuration register */
1315 v
= mifi_cfg
= bus_space_read_4(t
, mif
, HME_MIFI_CFG
);
1316 v
&= ~HME_MIF_CFG_PHY
;
1317 if (phy
== HME_PHYAD_EXTERNAL
)
1318 v
|= HME_MIF_CFG_PHY
;
1319 bus_space_write_4(t
, mif
, HME_MIFI_CFG
, v
);
1321 /* Enable MII drivers on external transceiver */
1322 v
= xif_cfg
= bus_space_read_4(t
, mac
, HME_MACI_XIF
);
1323 if (phy
== HME_PHYAD_EXTERNAL
)
1324 v
|= HME_MAC_XIF_MIIENABLE
;
1326 v
&= ~HME_MAC_XIF_MIIENABLE
;
1327 bus_space_write_4(t
, mac
, HME_MACI_XIF
, v
);
1330 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */
1332 * Check whether a transceiver is connected by testing
1333 * the MIF configuration register's MDI_X bits. Note that
1334 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h
1336 mif_mdi_bit
= 1 << (8 + (1 - phy
));
1338 v
= bus_space_read_4(t
, mif
, HME_MIFI_CFG
);
1339 if ((v
& mif_mdi_bit
) == 0)
1343 /* Construct the frame command */
1344 v
= (MII_COMMAND_START
<< HME_MIF_FO_ST_SHIFT
) |
1346 (MII_COMMAND_WRITE
<< HME_MIF_FO_OPC_SHIFT
) |
1347 (phy
<< HME_MIF_FO_PHYAD_SHIFT
) |
1348 (reg
<< HME_MIF_FO_REGAD_SHIFT
) |
1349 (val
& HME_MIF_FO_DATA
);
1351 bus_space_write_4(t
, mif
, HME_MIFI_FO
, v
);
1352 for (n
= 0; n
< 100; n
++) {
1354 v
= bus_space_read_4(t
, mif
, HME_MIFI_FO
);
1355 if (v
& HME_MIF_FO_TALSB
)
1359 printf("%s: mii_write timeout\n", device_xname(sc
->sc_dev
));
1361 /* Restore MIFI_CFG register */
1362 bus_space_write_4(t
, mif
, HME_MIFI_CFG
, mifi_cfg
);
1363 /* Restore XIF register */
1364 bus_space_write_4(t
, mac
, HME_MACI_XIF
, xif_cfg
);
1368 hme_mii_statchg(device_t dev
)
1370 struct hme_softc
*sc
= device_private(dev
);
1371 bus_space_tag_t t
= sc
->sc_bustag
;
1372 bus_space_handle_t mac
= sc
->sc_mac
;
1377 printf("hme_mii_statchg: status change\n");
1380 /* Set the MAC Full Duplex bit appropriately */
1381 /* Apparently the hme chip is SIMPLEX if working in full duplex mode,
1382 but not otherwise. */
1383 v
= bus_space_read_4(t
, mac
, HME_MACI_TXCFG
);
1384 if ((IFM_OPTIONS(sc
->sc_mii
.mii_media_active
) & IFM_FDX
) != 0) {
1385 v
|= HME_MAC_TXCFG_FULLDPLX
;
1386 sc
->sc_ethercom
.ec_if
.if_flags
|= IFF_SIMPLEX
;
1388 v
&= ~HME_MAC_TXCFG_FULLDPLX
;
1389 sc
->sc_ethercom
.ec_if
.if_flags
&= ~IFF_SIMPLEX
;
1391 sc
->sc_if_flags
= sc
->sc_ethercom
.ec_if
.if_flags
;
1392 bus_space_write_4(t
, mac
, HME_MACI_TXCFG
, v
);
1396 hme_mediachange(struct ifnet
*ifp
)
1398 struct hme_softc
*sc
= ifp
->if_softc
;
1399 bus_space_tag_t t
= sc
->sc_bustag
;
1400 bus_space_handle_t mif
= sc
->sc_mif
;
1401 bus_space_handle_t mac
= sc
->sc_mac
;
1402 int instance
= IFM_INST(sc
->sc_mii
.mii_media
.ifm_cur
->ifm_media
);
1403 int phy
= sc
->sc_phys
[instance
];
1409 printf("hme_mediachange: phy = %d\n", phy
);
1412 /* Select the current PHY in the MIF configuration register */
1413 v
= bus_space_read_4(t
, mif
, HME_MIFI_CFG
);
1414 v
&= ~HME_MIF_CFG_PHY
;
1415 if (phy
== HME_PHYAD_EXTERNAL
)
1416 v
|= HME_MIF_CFG_PHY
;
1417 bus_space_write_4(t
, mif
, HME_MIFI_CFG
, v
);
1419 /* If an external transceiver is selected, enable its MII drivers */
1420 v
= bus_space_read_4(t
, mac
, HME_MACI_XIF
);
1421 v
&= ~HME_MAC_XIF_MIIENABLE
;
1422 if (phy
== HME_PHYAD_EXTERNAL
)
1423 v
|= HME_MAC_XIF_MIIENABLE
;
1424 bus_space_write_4(t
, mac
, HME_MACI_XIF
, v
);
1426 if ((rc
= mii_mediachg(&sc
->sc_mii
)) == ENXIO
)
1432 * Process an ioctl request.
1435 hme_ioctl(struct ifnet
*ifp
, unsigned long cmd
, void *data
)
1437 struct hme_softc
*sc
= ifp
->if_softc
;
1438 struct ifaddr
*ifa
= (struct ifaddr
*)data
;
1445 case SIOCINITIFADDR
:
1446 switch (ifa
->ifa_addr
->sa_family
) {
1449 if (ifp
->if_flags
& IFF_UP
)
1452 ifp
->if_flags
|= IFF_UP
;
1453 error
= hme_init(ifp
);
1455 arp_ifinit(ifp
, ifa
);
1459 ifp
->if_flags
|= IFF_UP
;
1460 error
= hme_init(ifp
);
1468 struct ifreq
*ifr
= data
;
1470 (ifr
->ifr_flags
& IFF_DEBUG
) != 0 ? 1 : 0;
1473 if ((error
= ifioctl_common(ifp
, cmd
, data
)) != 0)
1476 switch (ifp
->if_flags
& (IFF_UP
|IFF_RUNNING
)) {
1479 * If interface is marked down and it is running, then
1483 ifp
->if_flags
&= ~IFF_RUNNING
;
1487 * If interface is marked up and it is stopped, then
1490 error
= hme_init(ifp
);
1492 case IFF_UP
|IFF_RUNNING
:
1494 * If setting debug or promiscuous mode, do not reset
1495 * the chip; for everything else, call hme_init()
1496 * which will trigger a reset.
1498 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG)
1499 if (ifp
->if_flags
!= sc
->sc_if_flags
) {
1500 if ((ifp
->if_flags
& (~RESETIGN
))
1501 == (sc
->sc_if_flags
& (~RESETIGN
)))
1504 error
= hme_init(ifp
);
1512 if (sc
->sc_ec_capenable
!= sc
->sc_ethercom
.ec_capenable
)
1513 error
= hme_init(ifp
);
1518 if ((error
= ether_ioctl(ifp
, cmd
, data
)) != ENETRESET
)
1523 if (cmd
!= SIOCADDMULTI
&& cmd
!= SIOCDELMULTI
)
1525 else if (ifp
->if_flags
& IFF_RUNNING
) {
1527 * Multicast list has changed; set the hardware filter
1535 sc
->sc_if_flags
= ifp
->if_flags
;
1541 hme_shutdown(device_t self
, int howto
)
1543 struct hme_softc
*sc
;
1546 sc
= device_private(self
);
1547 ifp
= &sc
->sc_ethercom
.ec_if
;
1554 * Set up the logical address filter.
1557 hme_setladrf(struct hme_softc
*sc
)
1559 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1560 struct ether_multi
*enm
;
1561 struct ether_multistep step
;
1562 struct ethercom
*ec
= &sc
->sc_ethercom
;
1563 bus_space_tag_t t
= sc
->sc_bustag
;
1564 bus_space_handle_t mac
= sc
->sc_mac
;
1569 /* Clear hash table */
1570 hash
[3] = hash
[2] = hash
[1] = hash
[0] = 0;
1572 /* Get current RX configuration */
1573 v
= bus_space_read_4(t
, mac
, HME_MACI_RXCFG
);
1575 if ((ifp
->if_flags
& IFF_PROMISC
) != 0) {
1576 /* Turn on promiscuous mode; turn off the hash filter */
1577 v
|= HME_MAC_RXCFG_PMISC
;
1578 v
&= ~HME_MAC_RXCFG_HENABLE
;
1579 ifp
->if_flags
|= IFF_ALLMULTI
;
1583 /* Turn off promiscuous mode; turn on the hash filter */
1584 v
&= ~HME_MAC_RXCFG_PMISC
;
1585 v
|= HME_MAC_RXCFG_HENABLE
;
1588 * Set up multicast address filter by passing all multicast addresses
1589 * through a crc generator, and then using the high order 6 bits as an
1590 * index into the 64 bit logical address filter. The high order bit
1591 * selects the word, while the rest of the bits select the bit within
1595 ETHER_FIRST_MULTI(step
, ec
, enm
);
1596 while (enm
!= NULL
) {
1597 if (memcmp(enm
->enm_addrlo
, enm
->enm_addrhi
, ETHER_ADDR_LEN
)) {
1599 * We must listen to a range of multicast addresses.
1600 * For now, just accept all multicasts, rather than
1601 * trying to set only those filter bits needed to match
1602 * the range. (At this time, the only use of address
1603 * ranges is for IP multicast routing, for which the
1604 * range is big enough to require all bits set.)
1606 hash
[3] = hash
[2] = hash
[1] = hash
[0] = 0xffff;
1607 ifp
->if_flags
|= IFF_ALLMULTI
;
1611 crc
= ether_crc32_le(enm
->enm_addrlo
, ETHER_ADDR_LEN
);
1613 /* Just want the 6 most significant bits. */
1616 /* Set the corresponding bit in the filter. */
1617 hash
[crc
>> 4] |= 1 << (crc
& 0xf);
1619 ETHER_NEXT_MULTI(step
, enm
);
1622 ifp
->if_flags
&= ~IFF_ALLMULTI
;
1625 /* Now load the hash table into the chip */
1626 bus_space_write_4(t
, mac
, HME_MACI_HASHTAB0
, hash
[0]);
1627 bus_space_write_4(t
, mac
, HME_MACI_HASHTAB1
, hash
[1]);
1628 bus_space_write_4(t
, mac
, HME_MACI_HASHTAB2
, hash
[2]);
1629 bus_space_write_4(t
, mac
, HME_MACI_HASHTAB3
, hash
[3]);
1630 bus_space_write_4(t
, mac
, HME_MACI_RXCFG
, v
);
1634 * Routines for accessing the transmit and receive buffers.
1635 * The various CPU and adapter configurations supported by this
1636 * driver require three different access methods for buffers
1638 * (1) contig (contiguous data; no padding),
1639 * (2) gap2 (two bytes of data followed by two bytes of padding),
1640 * (3) gap16 (16 bytes of data followed by 16 bytes of padding).
1645 * contig: contiguous data with no padding.
1647 * Buffers may have any alignment.
1651 hme_copytobuf_contig(struct hme_softc
*sc
, void *from
, int ri
, int len
)
1653 volatile void *buf
= sc
->sc_rb
.rb_txbuf
+ (ri
* _HME_BUFSZ
);
1656 * Just call memcpy() to do the work.
1658 memcpy(buf
, from
, len
);
1662 hme_copyfrombuf_contig(struct hme_softc
*sc
, void *to
, int boff
, int len
)
1664 volatile void *buf
= sc
->sc_rb
.rb_rxbuf
+ (ri
* _HME_BUFSZ
);
1667 * Just call memcpy() to do the work.
1669 memcpy(to
, buf
, len
);