sys/dev/ic/i82365var.h

   1 /*      $NetBSD: i82365var.h,v 1.30 2009/09/14 12:49:34 tsutsui Exp $   */
   2
   3 /*
   4  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Marc Horowitz.
  17  * 4. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <sys/device.h>
  33 #include <sys/callout.h>
  34 #include <sys/mutex.h>
  35
  36 #include <dev/pcmcia/pcmciareg.h>
  37 #include <dev/pcmcia/pcmciachip.h>
  38
  39 #include <dev/ic/i82365reg.h>
  40
  41 struct proc;
  42
  43 struct pcic_event {
  44         SIMPLEQ_ENTRY(pcic_event) pe_q;
  45         int pe_type;
  46 };
  47
  48 /* pe_type */
  49 #define PCIC_EVENT_INSERTION    0
  50 #define PCIC_EVENT_REMOVAL      1
  51
  52 struct pcic_handle {
  53         device_t ph_parent;
  54         bus_space_tag_t ph_bus_t;       /* I/O or MEM?  I don't mind */
  55         bus_space_handle_t ph_bus_h;
  56         uint8_t (*ph_read)(struct pcic_handle *, int);
  57         void (*ph_write)(struct pcic_handle *, int, uint8_t);
  58
  59         int     vendor;         /* vendor of chip */
  60         int     chip;           /* chip index 0 or 1 */
  61         int     socket;         /* socket index 0 or 1 */
  62         int     sock;           /* register offset */
  63         int     flags;
  64         int     laststate;
  65         int     memalloc;
  66         struct {
  67                 bus_addr_t      addr;
  68                 bus_size_t      size;
  69                 long            offset;
  70                 int             kind;
  71         } mem[PCIC_MEM_WINS];
  72         int     ioalloc;
  73         struct {
  74                 bus_addr_t      addr;
  75                 bus_size_t      size;
  76                 int             width;
  77         } io[PCIC_IO_WINS];
  78         int     ih_irq;
  79         device_t pcmcia;
  80
  81         int shutdown;
  82         struct lwp *event_thread;
  83         SIMPLEQ_HEAD(, pcic_event) events;
  84 };
  85
  86 #define PCIC_FLAG_SOCKETP       0x0001
  87 #define PCIC_FLAG_CARDP         0x0002
  88 #define PCIC_FLAG_ENABLED       0x0004
  89
  90 #define PCIC_LASTSTATE_PRESENT  0x0001
  91 #define PCIC_LASTSTATE_EMPTY    0x0000
  92
  93 #define C0SA    0
  94 #define C0SB    PCIC_SOCKET_OFFSET
  95 #define C1SA    PCIC_CHIP_OFFSET
  96 #define C1SB    PCIC_CHIP_OFFSET + PCIC_SOCKET_OFFSET
  97
  98 #define PCIC_VENDOR_NONE                -1
  99 #define PCIC_VENDOR_UNKNOWN             0
 100 #define PCIC_VENDOR_I82365SLR0          1
 101 #define PCIC_VENDOR_I82365SLR1          2
 102 #define PCIC_VENDOR_CIRRUS_PD67XX       3
 103 #define PCIC_VENDOR_I82365SL_DF         4
 104 #define PCIC_VENDOR_IBM                 5
 105 #define PCIC_VENDOR_IBM_KING            6
 106 #define PCIC_VENDOR_RICOH_5C296         7
 107 #define PCIC_VENDOR_RICOH_5C396         8
 108
 109 /*
 110  * This is sort of arbitrary.  It merely needs to be "enough". It can be
 111  * overridden in the conf file, anyway.
 112  */
 113
 114 #define PCIC_MEM_PAGES  4
 115 #define PCIC_MEMSIZE    PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE
 116
 117 #define PCIC_NSLOTS     4
 118
 119 struct pcic_softc {
 120         struct device dev;
 121
 122         bus_space_tag_t memt;
 123         bus_space_handle_t memh;
 124         bus_space_tag_t iot;
 125         bus_space_handle_t ioh;
 126
 127         struct callout poll_ch;
 128         int poll_established;
 129
 130         pcmcia_chipset_tag_t pct;
 131
 132         kmutex_t sc_pcic_lock;
 133
 134         /* this needs to be large enough to hold PCIC_MEM_PAGES bits */
 135         int     subregionmask;
 136 #define PCIC_MAX_MEM_PAGES      (8 * sizeof(int))
 137
 138         /* used by memory window mapping functions */
 139         bus_addr_t membase;
 140
 141         /*
 142          * used by io window mapping functions.  These can actually overlap
 143          * with another pcic, since the underlying extent mapper will deal
 144          * with individual allocations.  This is here to deal with the fact
 145          * that different busses have different real widths (different pc
 146          * hardware seems to use 10 or 12 bits for the I/O bus).
 147          */
 148         bus_addr_t iobase;
 149         bus_addr_t iosize;
 150
 151         int     irq;
 152         void    *ih;
 153
 154         struct pcic_handle handle[PCIC_NSLOTS];
 155
 156         /* for use by underlying chip code for discovering irqs */
 157         int intr_detect, intr_false;
 158         int intr_mask[PCIC_NSLOTS / 2]; /* probed intterupts if possible */
 159 };
 160
 161
 162 int     pcic_ident_ok(int);
 163 int     pcic_vendor(struct pcic_handle *);
 164 const char *pcic_vendor_to_string(int);
 165
 166 void    pcic_attach(struct pcic_softc *);
 167 void    pcic_attach_sockets(struct pcic_softc *);
 168 void    pcic_attach_sockets_finish(struct pcic_softc *);
 169 int     pcic_intr(void *arg);
 170
 171 #if 0
 172 static __inline int pcic_read(struct pcic_handle *, int);
 173 static __inline void pcic_write(struct pcic_handle *, int, uint8_t);
 174 #endif
 175
 176 int     pcic_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
 177             struct pcmcia_mem_handle *);
 178 void    pcic_chip_mem_free(pcmcia_chipset_handle_t,
 179             struct pcmcia_mem_handle *);
 180 int     pcic_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
 181             bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
 182 void    pcic_chip_mem_unmap(pcmcia_chipset_handle_t, int);
 183
 184 int     pcic_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
 185             bus_size_t, bus_size_t, struct pcmcia_io_handle *);
 186 void    pcic_chip_io_free(pcmcia_chipset_handle_t,
 187             struct pcmcia_io_handle *);
 188 int     pcic_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
 189             bus_size_t, struct pcmcia_io_handle *, int *);
 190 void    pcic_chip_io_unmap(pcmcia_chipset_handle_t, int);
 191
 192 void    pcic_chip_socket_enable(pcmcia_chipset_handle_t);
 193 void    pcic_chip_socket_disable(pcmcia_chipset_handle_t);
 194 void    pcic_chip_socket_settype(pcmcia_chipset_handle_t, int);
 195
 196 #if 0
 197
 198 static __inline int pcic_read(struct pcic_handle *, int);
 199 static __inline int
 200 pcic_read(h, idx)
 201         struct pcic_handle *h;
 202         int idx;
 203 {
 204         if (idx != -1)
 205                 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
 206                     h->sock + idx);
 207         return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA));
 208 }
 209
 210 static __inline void pcic_write(struct pcic_handle *, int, int);
 211 static __inline void
 212 pcic_write(h, idx, data)
 213         struct pcic_handle *h;
 214         int idx;
 215         int data;
 216 {
 217         if (idx != -1)
 218                 bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
 219                     h->sock + idx);
 220         bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data));
 221 }
 222 #else
 223 #define pcic_read(h, idx) \
 224         (*(h)->ph_read)((h), (idx))
 225
 226 #define pcic_write(h, idx, data) \
 227         (*(h)->ph_write)((h), (idx), (data))
 228
 229 #endif