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[netbsd-mini2440.git] / sys / dev / ic / isacsx.h
blob89e0f76ad5111002f1dbf2169e4892aa096e5dac
1 /* $NetBSD: isacsx.h,v 1.3 2005/12/11 12:21:27 christos Exp $ */
2 /*
3 * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 * 4. Altered versions must be plainly marked as such, and must not be
18 * misrepresented as being the original software and/or documentation.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 *---------------------------------------------------------------------------
33 *
34 * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_isacsx.h,v 1.1.2.1 2002/04/25 20:26:50 gj Exp $
35 *
36 * last edit-date: [Wed Jan 24 09:10:42 2001]
37 *
38 *---------------------------------------------------------------------------*/
39
40 #ifndef I4B_ISACSX_H_
41 #define I4B_ISACSX_H_
42
43 /*
44 * XXX: Leo: It is unclear to me if this is a necessity for the isacsx too...
45 *
46 * The ISAC databook specifies a delay of 2.5 DCL clock cycles between
47 * writes to the ISAC command register CMDR. This is the delay used to
48 * satisfy this requirement.
49 */
50 #define I4B_ISAC_CMDRWRDELAY 30
51
52 #if (I4B_ISAC_CMDRWRDELAY > 0)
53 #define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY)
54 #else
55 #warning "I4B_ISAC_CMDRWRDELAY set to 0!"
56 #define ISACCMDRWRDELAY()
57 #endif
58
59 #define ISACSX_FIFO_LEN 32 /* 32 bytes FIFO on chip */
60
61 #define ISACSX_V13 0x01
62
63 /*
64 * definitions of registers and bits for the ISAC-SX ISDN chip.
65 */
66
67 typedef struct isacsx_reg {
68
69 /* 32 byte deep FIFO always first */
70
71 unsigned char isacsx_fifo [ISACSX_FIFO_LEN];
72
73 /* most registers can be read/written, but have different names */
74 /* so define a union with read/write names to make that clear */
75
76 union {
77 struct {
78 unsigned char isacsx_istad;
79 unsigned char isacsx_stard;
80 unsigned char isacsx_moded;
81 unsigned char isacsx_exmd1;
82 unsigned char isacsx_timr1;
83 unsigned char dummy_25;
84 unsigned char isacsx_rbcld;
85 unsigned char isacsx_rbchd;
86 unsigned char isacsx_rstad;
87 unsigned char isacsx_tmd;
88 unsigned char dummy_2a;
89 unsigned char dummy_2b;
90 unsigned char dummy_2c;
91 unsigned char dummy_2d;
92 unsigned char isacsx_cir0;
93 unsigned char isacsx_codr1;
94 unsigned char isacsx_tr_conf0;
95 unsigned char isacsx_tr_conf1;
96 unsigned char isacsx_tr_conf2;
97 unsigned char isacsx_tr_sta;
98 unsigned char dummy_34;
99 unsigned char isacsx_sqrr1;
100 unsigned char isacsx_sqrr2;
101 unsigned char isacsx_sqrr3;
102 unsigned char isacsx_istatr;
103 unsigned char isacsx_masktr;
104 unsigned char dummy_3a;
105 unsigned char dummy_3b;
106 unsigned char isacsx_acgf2;
107 unsigned char dummy_3d;
108 unsigned char dummy_3e;
109 unsigned char dummy_3f;
110 unsigned char isacsx_cda10;
111 unsigned char isacsx_cda11;
112 unsigned char isacsx_cda20;
113 unsigned char isacsx_cda21;
114 unsigned char isacsx_cda_tsdp10;
115 unsigned char isacsx_cda_tsdp11;
116 unsigned char isacsx_cda_tsdp20;
117 unsigned char isacsx_cda_tsdp21;
118 unsigned char dummy_48;
119 unsigned char dummy_49;
120 unsigned char dummy_4a;
121 unsigned char dummy_4b;
122 unsigned char isacsx_tr_tsdp_bc1;
123 unsigned char isacsx_tr_tsdp_bc2;
124 unsigned char isacsx_cda1_cr;
125 unsigned char isacsx_cda2_cr;
126 unsigned char isacsx_tr_cr;
127 unsigned char dummy_51;
128 unsigned char dummy_52;
129 unsigned char isacsx_dci_cr;
130 unsigned char isacsx_mon_cr;
131 unsigned char isacsx_sds_cr;
132 unsigned char dummy_56;
133 unsigned char isacsx_iom_cr;
134 unsigned char isacsx_sti;
135 unsigned char isacsx_msti;
136 unsigned char isacsx_sds_conf;
137 unsigned char isacsx_mcda;
138 unsigned char isacsx_mor;
139 unsigned char isacsx_mosr;
140 unsigned char isacsx_mocr;
141 unsigned char isacsx_msta;
142 unsigned char isacsx_ista;
143 unsigned char isacsx_auxi;
144 unsigned char isacsx_mode1;
145 unsigned char isacsx_mode2;
146 unsigned char isacsx_id;
147 unsigned char isacsx_timr2;
148 unsigned char dummy_66;
149 unsigned char dummy_67;
150 unsigned char dummy_68;
151 unsigned char dummy_69;
152 unsigned char dummy_6a;
153 unsigned char dummy_6b;
154 unsigned char dummy_6c;
155 unsigned char dummy_6d;
156 unsigned char dummy_6e;
157 unsigned char dummy_6f;
158 } isacsx_r;
159 struct {
160 unsigned char isacsx_maskd;
161 unsigned char isacsx_cmdrd;
162 unsigned char isacsx_moded;
163 unsigned char isacsx_exmd1;
164 unsigned char isacsx_timr1;
165 unsigned char isacsx_sap1;
166 unsigned char isacsx_sap2;
167 unsigned char isacsx_tei1;
168 unsigned char isacsx_tei2;
169 unsigned char isacsx_tmd;
170 unsigned char dummy_2a;
171 unsigned char dummy_2b;
172 unsigned char dummy_2c;
173 unsigned char dummy_2d;
174 unsigned char isacsx_cix0;
175 unsigned char isacsx_codx1;
176 unsigned char isacsx_tr_conf0;
177 unsigned char isacsx_tr_conf1;
178 unsigned char isacsx_tr_conf2;
179 unsigned char dummy_33;
180 unsigned char dummy_34;
181 unsigned char isacsx_sqrx1;
182 unsigned char dummy_36;
183 unsigned char dummy_37;
184 unsigned char dummy_38;
185 unsigned char isacsx_masktr;
186 unsigned char dummy_3a;
187 unsigned char dummy_3b;
188 unsigned char isacsx_acgf2;
189 unsigned char dummy_3d;
190 unsigned char dummy_3e;
191 unsigned char dummy_3f;
192 unsigned char isacsx_cda10;
193 unsigned char isacsx_cda11;
194 unsigned char isacsx_cda20;
195 unsigned char isacsx_cda21;
196 unsigned char isacsx_cda_tsdp10;
197 unsigned char isacsx_cda_tsdp11;
198 unsigned char isacsx_cda_tsdp20;
199 unsigned char isacsx_cda_tsdp21;
200 unsigned char dummy_48;
201 unsigned char dummy_49;
202 unsigned char dummy_4a;
203 unsigned char dummy_4b;
204 unsigned char isacsx_tr_tsdp_bc1;
205 unsigned char isacsx_tr_tsdp_bc2;
206 unsigned char isacsx_cda1_cr;
207 unsigned char isacsx_cda2_cr;
208 unsigned char isacsx_tr_cr;
209 unsigned char dummy_51;
210 unsigned char dummy_52;
211 unsigned char isacsx_dci_cr;
212 unsigned char isacsx_mon_cr;
213 unsigned char isacsx_sds_cr;
214 unsigned char dummy_56;
215 unsigned char isacsx_iom_cr;
216 unsigned char isacsx_asti;
217 unsigned char isacsx_msti;
218 unsigned char isacsx_sds_conf;
219 unsigned char dummy_5b;
220 unsigned char isacsx_mox;
221 unsigned char dummy_5d;
222 unsigned char isacsx_mocr;
223 unsigned char isacsx_mconf;
224 unsigned char isacsx_mask;
225 unsigned char isacsx_auxm;
226 unsigned char isacsx_mode1;
227 unsigned char isacsx_mode2;
228 unsigned char isacsx_sres;
229 unsigned char isacsx_timr2;
230 unsigned char dummy_66;
231 unsigned char dummy_67;
232 unsigned char dummy_68;
233 unsigned char dummy_69;
234 unsigned char dummy_6a;
235 unsigned char dummy_6b;
236 unsigned char dummy_6c;
237 unsigned char dummy_6d;
238 unsigned char dummy_6e;
239 unsigned char dummy_6f;
240 } isacsx_w;
241 } isacsx_rw;
242 } __packed isacsx_reg_t;
243
244 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
245
246 /* ISACSX read registers */
247
248 #define i_istad isacsx_rw.isacsx_r.isacsx_istad
249 #define I_ISTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istad)
250 #define i_stard isacsx_rw.isacsx_r.isacsx_stard
251 #define I_STARD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_stard)
252 #define i_rmoded isacsx_rw.isacsx_r.isacsx_moded
253 #define I_RMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_moded)
254 #define i_rexmd1 isacsx_rw.isacsx_r.isacsx_exmd1
255 #define I_REXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_exmd1)
256 #define i_rtimr1 isacsx_rw.isacsx_r.isacsx_timr1
257 #define I_RTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr1)
258 #define i_rbcld isacsx_rw.isacsx_r.isacsx_rbcld
259 #define I_RBCLD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbcld)
260 #define i_rbchd isacsx_rw.isacsx_r.isacsx_rbchd
261 #define I_RBCHD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rbchd)
262 #define i_rstad isacsx_rw.isacsx_r.isacsx_rstad
263 #define I_RSTAD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_rstad)
264 #define i_rtmd isacsx_rw.isacsx_r.isacsx_tmd
265 #define I_RTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tmd)
266 #define i_cir0 isacsx_rw.isacsx_r.isacsx_cir0
267 #define I_CIR0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cir0)
268 #define i_codr1 isacsx_rw.isacsx_r.isacsx_codr1
269 #define I_CODR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_codr1)
270 #define i_rtr_conf0 isacsx_rw.isacsx_r.isacsx_tr_conf0
271 #define I_RTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf0)
272 #define i_rtr_conf1 isacsx_rw.isacsx_r.isacsx_tr_conf1
273 #define I_RTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf1)
274 #define i_rtr_conf2 isacsx_rw.isacsx_r.isacsx_tr_conf2
275 #define I_RTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_conf2)
276 #define i_sta isacsx_rw.isacsx_r.isacsx_sta
277 #define I_STA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sta)
278 #define i_sqrr1 isacsx_rw.isacsx_r.isacsx_sqrr1
279 #define I_SQRR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr1)
280 #define i_sqrr2 isacsx_rw.isacsx_r.isacsx_sqrr2
281 #define I_SQRR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr2)
282 #define i_sqrr3 isacsx_rw.isacsx_r.isacsx_sqrr3
283 #define I_SQRR3 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sqrr3)
284 #define i_istatr isacsx_rw.isacsx_r.isacsx_istatr
285 #define I_ISTATR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_istatr)
286 #define i_rmasktr isacsx_rw.isacsx_r.isacsx_masktr
287 #define I_RMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_masktr)
288 #define i_racgf2 isacsx_rw.isacsx_r.isacsx_acgf2
289 #define I_RACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_acgf2)
290 #define i_rcda10 isacsx_rw.isacsx_r.isacsx_cda10
291 #define I_RCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda10)
292 #define i_rcda11 isacsx_rw.isacsx_r.isacsx_cda11
293 #define I_RCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
294 #define i_rcda20 isacsx_rw.isacsx_r.isacsx_cda20
295 #define I_RCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
296 #define i_rcda21 isacsx_rw.isacsx_r.isacsx_cda21
297 #define I_RCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
298 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
299 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
300 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
301 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
302 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
303 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
304 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
305 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
306 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
307 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
308 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
309 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
310 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
311 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
312 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
313 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
314 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
315 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
316 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
317 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
318 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
319 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
320 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
321 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
322 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
323 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
324 #define i_sti isacsx_rw.isacsx_r.isacsx_sti
325 #define I_STI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sti)
326 #define i_msti isacsx_rw.isacsx_r.isacsx_msti
327 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
328 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
329 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
330 #define i_mcda isacsx_rw.isacsx_r.isacsx_mcda
331 #define I_MCDA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mcda)
332 #define i_mor isacsx_rw.isacsx_r.isacsx_mor
333 #define I_MOR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mor)
334 #define i_mosr isacsx_rw.isacsx_r.isacsx_mosr
335 #define I_MOSR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mosr)
336 #define i_rmocr isacsx_rw.isacsx_r.isacsx_mocr
337 #define I_RMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mocr)
338 #define i_msta isacsx_rw.isacsx_r.isacsx_msta
339 #define I_MSTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msta)
340 #define i_ista isacsx_rw.isacsx_r.isacsx_ista
341 #define I_ISTA REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_ista)
342 #define i_auxi isacsx_rw.isacsx_r.isacsx_auxi
343 #define I_AUXI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_auxi)
344 #define i_rmode1 isacsx_rw.isacsx_r.isacsx_mode1
345 #define I_RMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode1)
346 #define i_rmode2 isacsx_rw.isacsx_r.isacsx_mode2
347 #define I_RMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mode2)
348 #define i_id isacsx_rw.isacsx_r.isacsx_id
349 #define I_ID REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_id)
350 #define i_rtimr2 isacsx_rw.isacsx_r.isacsx_timr2
351 #define I_RTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_timr2)
352
353 /* ISAC write registers - isacsx_mode, isacsx_timr, isacsx_star2, isacsx_spcr, */
354 /* isacsx_c1r, isacsx_c2r, isacsx_adf2 see read registers */
355
356 #define i_maskd isacsx_rw.isacsx_w.isacsx_maskd
357 #define I_MASKD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_maskd)
358 #define i_cmdrd isacsx_rw.isacsx_w.isacsx_cmdrd
359 #define I_CMDRD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cmdrd)
360 #define i_wmoded isacsx_rw.isacsx_w.isacsx_moded
361 #define I_WMODED REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_moded)
362 #define i_wexmd1 isacsx_rw.isacsx_w.isacsx_exmd1
363 #define I_WEXMD1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_exmd1)
364 #define i_wtimr1 isacsx_rw.isacsx_w.isacsx_timr1
365 #define I_WTIMR1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr1)
366 #define i_sap1 isacsx_rw.isacsx_w.isacsx_sap1
367 #define I_SAP1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap1)
368 #define i_sap2 isacsx_rw.isacsx_w.isacsx_sap2
369 #define I_SAP2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sap2)
370 #define i_tei1 isacsx_rw.isacsx_w.isacsx_tei1
371 #define i_tei2 isacsx_rw.isacsx_w.isacsx_tei2
372 #define i_wtmd isacsx_rw.isacsx_w.isacsx_tmd
373 #define I_WTMD REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tmd)
374 #define i_cix0 isacsx_rw.isacsx_w.isacsx_cix0
375 #define I_CIX0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cix0)
376 #define i_codx1 isacsx_rw.isacsx_w.isacsx_codx1
377 #define I_CODX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_codx1)
378 #define i_wtr_conf0 isacsx_rw.isacsx_w.isacsx_tr_conf0
379 #define I_WTR_CONF0 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf0)
380 #define i_wtr_conf1 isacsx_rw.isacsx_w.isacsx_tr_conf1
381 #define I_WTR_CONF1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf1)
382 #define i_wtr_conf2 isacsx_rw.isacsx_w.isacsx_tr_conf2
383 #define I_WTR_CONF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_tr_conf2)
384 #define i_sqrx1 isacsx_rw.isacsx_w.isacsx_sqrx1
385 #define I_SQRX1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sqrx1)
386 #define i_wmasktr isacsx_rw.isacsx_w.isacsx_masktr
387 #define I_WMASKTR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_masktr)
388 #define i_wacgf2 isacsx_rw.isacsx_w.isacsx_acgf2
389 #define I_WACGF2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_acgf2)
390 #define i_wcda10 isacsx_rw.isacsx_w.isacsx_cda10
391 #define I_WCDA10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_cda10)
392 #define i_wcda11 isacsx_rw.isacsx_r.isacsx_cda11
393 #define I_WCDA11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda11)
394 #define i_wcda20 isacsx_rw.isacsx_r.isacsx_cda20
395 #define I_WCDA20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda20)
396 #define i_wcda21 isacsx_rw.isacsx_r.isacsx_cda21
397 #define I_WCDA21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda21)
398 #define i_cda_tsdp10 isacsx_rw.isacsx_r.isacsx_cda_tsdp10
399 #define I_CDA_TSDP10 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp10)
400 #define i_cda_tsdp11 isacsx_rw.isacsx_r.isacsx_cda_tsdp11
401 #define I_CDA_TSDP11 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp11)
402 #define i_cda_tsdp20 isacsx_rw.isacsx_r.isacsx_cda_tsdp20
403 #define I_CDA_TSDP20 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp20)
404 #define i_cda_tsdp21 isacsx_rw.isacsx_r.isacsx_cda_tsdp21
405 #define I_CDA_TSDP21 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda_tsdp21)
406 #define i_tr_tsdp_bc1 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1
407 #define I_TR_TSDP_BC1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc1)
408 #define i_tr_tsdp_bc2 isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2
409 #define I_TR_TSDP_BC2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_tsdp_bc2)
410 #define i_cda1_cr isacsx_rw.isacsx_r.isacsx_cda1_cr
411 #define I_CDA1_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda1_cr)
412 #define i_cda2_cr isacsx_rw.isacsx_r.isacsx_cda2_cr
413 #define I_CDA2_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_cda2_cr)
414 #define i_tr_cr isacsx_rw.isacsx_r.isacsx_tr_cr
415 #define I_TR_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_tr_cr)
416 #define i_dci_cr isacsx_rw.isacsx_r.isacsx_dci_cr
417 #define I_DCI_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_dci_cr)
418 #define i_mon_cr isacsx_rw.isacsx_r.isacsx_mon_cr
419 #define I_MON_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_mon_cr)
420 #define i_sds_cr isacsx_rw.isacsx_r.isacsx_sds_cr
421 #define I_SDS_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_cr)
422 #define i_iom_cr isacsx_rw.isacsx_r.isacsx_iom_cr
423 #define I_IOM_CR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_iom_cr)
424 #define i_asti isacsx_rw.isacsx_r.isacsx_asti
425 #define I_ASTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_asti)
426 #define i_msti isacsx_rw.isacsx_r.isacsx_msti
427 #define I_MSTI REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_msti)
428 #define i_sds_conf isacsx_rw.isacsx_r.isacsx_sds_conf
429 #define I_SDS_CONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_r.isacsx_sds_conf)
430 #define i_mox isacsx_rw.isacsx_w.isacsx_mox
431 #define I_MOX REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mox)
432 #define i_wmocr isacsx_rw.isacsx_w.isacsx_mocr
433 #define I_WMOCR REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mocr)
434 #define i_mconf isacsx_rw.isacsx_w.isacsx_mconf
435 #define I_MCONF REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mconf)
436 #define i_mask isacsx_rw.isacsx_w.isacsx_mask
437 #define I_MASK REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mask)
438 #define i_auxm isacsx_rw.isacsx_w.isacsx_auxm
439 #define I_AUXM REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_auxm)
440 #define i_wmode1 isacsx_rw.isacsx_w.isacsx_mode1
441 #define I_WMODE1 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode1)
442 #define i_wmode2 isacsx_rw.isacsx_w.isacsx_mode2
443 #define I_WMODE2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_mode2)
444 #define i_sres isacsx_rw.isacsx_w.isacsx_sres
445 #define I_SRES REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_sres)
446 #define i_wtimr2 isacsx_rw.isacsx_w.isacsx_timr2
447 #define I_WTIMR2 REG_OFFSET(isacsx_reg_t, isacsx_rw.isacsx_w.isacsx_timr2)
448
449 #define ISACSX_ISTAD_RME 0x80
450 #define ISACSX_ISTAD_RPF 0x40
451 #define ISACSX_ISTAD_RFO 0x20
452 #define ISACSX_ISTAD_XPR 0x10
453 #define ISACSX_ISTAD_XMR 0x08
454 #define ISACSX_ISTAD_XDU 0x04
455
456 #define ISACSX_MASKD_RME 0x80
457 #define ISACSX_MASKD_RPF 0x40
458 #define ISACSX_MASKD_RFO 0x20
459 #define ISACSX_MASKD_XPR 0x10
460 #define ISACSX_MASKD_XMR 0x08
461 #define ISACSX_MASKD_XDU 0x04
462 /* these must always be set */
463 #define ISACSX_MASKD_LOW 0x03
464 #define ISACSX_MASKD_ALL 0xff
465
466 #define ISACSX_STARD_XDOV 0x80
467 #define ISACSX_STARD_XFW 0x40
468 #define ISACSX_STARD_RAC1 0x08
469 #define ISACSX_STARD_XAC1 0x02
470
471 #define ISACSX_CMDRD_RMC 0x80
472 #define ISACSX_CMDRD_RRES 0x40
473 #define ISACSX_CMDRD_STI 0x10
474 #define ISACSX_CMDRD_XTF 0x08
475 #define ISACSX_CMDRD_XME 0x02
476 #define ISACSX_CMDRD_XRES 0x01
477
478 #define ISACSX_MODED_MDS2 0x80
479 #define ISACSX_MODED_MDS1 0x40
480 #define ISACSX_MODED_MDS0 0x20
481 #define ISACSX_MODED_RAC 0x08
482 #define ISACSX_MODED_DIM2 0x04
483 #define ISACSX_MODED_DIM1 0x02
484 #define ISACSX_MODED_DIM0 0x01
485
486 /* default */
487 #define ISACSX_EXMD1_XFBS_32 0x00 /* XFIFO is 32 bytes */
488 #define ISACSX_EXMD1_XFBS_16 0x80 /* XFIFO is 16 bytes */
489 /* default */
490 #define ISACSX_EXMD1_RFBS_32 0x00 /* XFIFO is 32 bytes */
491 #define ISACSX_EXMD1_RFBS_16 0x20 /* XFIFO is 16 bytes */
492 #define ISACSX_EXMD1_RFBS_08 0x40 /* XFIFO is 8 bytes */
493 #define ISACSX_EXMD1_RFBS_04 0x60 /* XFIFO is 4 bytes */
494 #define ISACSX_EXMD1_SRA 0x10
495 #define ISACSX_EXMD1_XCRC 0x08
496 #define ISACSX_EXMD1_RCRC 0x04
497 #define ISACSX_EXMD1_ITF 0x01
498
499 #define ISACSX_RSTAD_VFR 0x80
500 #define ISACSX_RSTAD_RDO 0x40
501 #define ISACSX_RSTAD_CRC 0x20
502 #define ISACSX_RSTAD_RAB 0x10
503 #define ISACSX_RSTAD_SA1 0x08
504 #define ISACSX_RSTAD_SA0 0x04
505 #define ISACSX_RSTAD_CR 0x02
506 #define ISACSX_RSTAD_TA 0x01
507
508 #define ISACSX_RSTAD_MASK 0xf0 /* the interesting bits */
509
510 #define ISACSX_RBCHD_OV 0x10
511 /* the other 4 bits are the high bits of the receive byte count */
512
513 #define ISACSX_CIR0_CIC0 0x08
514 /* CODR0 >> 4 */
515 #define ISACSX_CIR0_IPU 0x07
516 #define ISACSX_CIR0_IDR 0x00
517 #define ISACSX_CIR0_ISD 0x02
518 #define ISACSX_CIR0_IDIS 0x03
519 #define ISACSX_CIR0_IEI 0x06
520 #define ISACSX_CIR0_IRSY 0x04
521 #define ISACSX_CIR0_IARD 0x08
522 #define ISACSX_CIR0_ITI 0x0a
523 #define ISACSX_CIR0_IATI 0x0b
524 #define ISACSX_CIR0_IAI8 0x0c
525 #define ISACSX_CIR0_IAI10 0x0d
526 #define ISACSX_CIR0_IDID 0x0f
527
528 #define ISACSX_IOM_CR_SPU 0x80
529 #define ISACSX_IOM_CR_CI_CS 0x20
530 #define ISACSX_IOM_CR_TIC_DIS 0x10
531 #define ISACSX_IOM_CR_EN_BCL 0x08
532 #define ISACSX_IOM_CR_CLKM 0x04
533 #define ISACSX_IOM_CR_DIS_OD 0x02
534 #define ISACSX_IOM_CR_DIS_IOM 0x01
535
536 #define ISACSX_CI_MASK 0x0f
537
538 #define ISACSX_CIX0_BAC 0x01
539 /* in IOM-2 mode the low bits are always 1 */
540 #define ISACSX_CIX0_LOW 0x0e
541 /* C/I codes from bits 7-4 (>> 4 & 0xf) */
542 /* the commands */
543 #define ISACSX_CIX0_CTIM 0
544 #define ISACSX_CIX0_CRS 0x01
545 /* test mode only */
546 #define ISACSX_CIX0_CSSSP 0x02
547 /* test mode only */
548 #define ISACSX_CIX0_CSSCP 0x03
549 #define ISACSX_CIX0_CAR8 0x08
550 #define ISACSX_CIX0_CAR10 0x09
551 #define ISACSX_CIX0_CARL 0x0a
552 #define ISACSX_CIX0_CDIU 0x0f
553
554 /* Interrupt, General Configuration Registers */
555
556 #define ISACSX_ISTA_ST 0x20
557 #define ISACSX_ISTA_CIC 0x10
558 #define ISACSX_ISTA_AUX 0x08
559 #define ISACSX_ISTA_TRAN 0x04
560 #define ISACSX_ISTA_MOS 0x02
561 #define ISACSX_ISTA_ICD 0x01
562
563 #define ISACSX_MASK_ST 0x20
564 #define ISACSX_MASK_CIC 0x10
565 #define ISACSX_MASK_AUX 0x08
566 #define ISACSX_MASK_TRAN 0x04
567 #define ISACSX_MASK_MOS 0x02
568 #define ISACSX_MASK_ICD 0x01
569
570 #define ISACSX_AUXI_EAW 0x20
571 #define ISACSX_AUXI_WOV 0x10
572 #define ISACSX_AUXI_TIN2 0x08
573 #define ISACSX_AUXI_TIN1 0x04
574
575 #define ISACSX_AUXM_EAW 0x20
576 #define ISACSX_AUXM_WOV 0x10
577 #define ISACSX_AUXM_TIN2 0x08
578 #define ISACSX_AUXM_TIN1 0x04
579
580 #define ISACSX_MODE1_WTC1 0x10
581 #define ISACSX_MODE1_WTC2 0x08
582 #define ISACSX_MODE1_CFS 0x04
583 #define ISACSX_MODE1_RSS2 0x02
584 #define ISACSX_MODE1_RSS1 0x01
585
586 #define ISACSX_MODE2_INT_POL 0x08
587 #define ISACSX_MODE2_PPSDX 0x01
588
589 #define ISACSX_ID_MASK 0x2F /* 0x01 = Version 1.3 */
590
591
592 extern unsigned char isacsx_imaskd;
593 extern unsigned char isacsx_imask;
594
595 #endif /* I4B_ISACSX_H_ */
NetBSD on the FriendlyARM MINI2440