sys/dev/ic/lemacreg.h

   1 /*      $NetBSD: lemacreg.h,v 1.2.22.4 2005/03/04 16:41:30 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 1994, 1995, 1997 Matt Thomas <matt@3am-software.com>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. The name of the author may not be used to endorse or promote products
  13  *    derived from this software without specific prior written permission
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  */
  26 #ifndef _LEMAC_H_
  27 #define _LEMAC_H_
  28
  29 #define LEMAC_IOBASE_LOW        0x200
  30 #define LEMAC_IOBASE_HIGH       0x400
  31
  32 /*
  33  * This is list of registers used on a DEC EtherWORKS III card.
  34  * Each board occupies a 32 byte register space.  This can be
  35  * in either EISA or ISA space.  Currently we only support ISA
  36  * space.
  37  */
  38
  39 #define LEMAC_REG_CS            0x00    /* Control and Status */
  40 #define LEMAC_REG_CTL           0x01    /* Control */
  41 #define LEMAC_REG_IC            0x02    /* Interrupt Control */
  42 #define LEMAC_REG_TS            0x03    /* Transmit Status */
  43 #define LEMAC_REG_RSVD1         0x04    /* Reserved (not used) */
  44 #define LEMAC_REG_RSVD2         0x05    /* Reserved (not used) */
  45 #define LEMAC_REG_FMQ           0x06    /* Free Memory Queue */
  46 #define LEMAC_REG_FMC           0x07    /* Free Memory Queue Count */
  47 #define LEMAC_REG_RQ            0x08    /* Receive Queue */
  48 #define LEMAC_REG_RQC           0x09    /* Receive Queue Count */
  49 #define LEMAC_REG_TQ            0x0A    /* Transmit Queue */
  50 #define LEMAC_REG_TQC           0x0B    /* Transmit Queue Count */
  51 #define LEMAC_REG_TDQ           0x0C    /* Transmit Done Queue */
  52 #define LEMAC_REG_TDC           0x0D    /* Transmit Done Queue Count */
  53 #define LEMAC_REG_PI1           0x0E    /* Page Index #1 */
  54 #define LEMAC_REG_PI2           0x0F    /* Page Index #2 */
  55 #define LEMAC_REG_DAT           0x10    /* Data */
  56 #define LEMAC_REG_IOP           0x11    /* I/O Page */
  57 #define LEMAC_REG_IOB           0x12    /* I/O Base */
  58 #define LEMAC_REG_MPN           0x13    /* Memory Page */
  59 #define LEMAC_REG_MBR           0x14    /* Memory Base */
  60 #define LEMAC_REG_APD           0x15    /* Address PROM */
  61 #define LEMAC_REG_EE1           0x16    /* EEPROM Data #1 */
  62 #define LEMAC_REG_EE2           0x17    /* EEPROM Data #2 */
  63 #define LEMAC_REG_PA0           0x18    /* Physical Address (Byte 0) */
  64 #define LEMAC_REG_PA1           0x19    /* Physical Address (Byte 1) */
  65 #define LEMAC_REG_PA2           0x1A    /* Physical Address (Byte 2) */
  66 #define LEMAC_REG_PA3           0x1B    /* Physical Address (Byte 3) */
  67 #define LEMAC_REG_PA4           0x1C    /* Physical Address (Byte 4) */
  68 #define LEMAC_REG_PA5           0x1D    /* Physical Address (Byte 5) */
  69 #define LEMAC_REG_CNF           0x1E    /* Configuration Management */
  70 #define LEMAC_IOSIZE            0x20    /* LEMAC uses 32 bytes of IOSPACE */
  71
  72
  73 #define LEMAC_REG_EID0          0x80    /* EISA Identification 0 */
  74 #define LEMAC_REG_EID1          0x81    /* EISA Identification 1 */
  75 #define LEMAC_REG_EID2          0x82    /* EISA Identification 2 */
  76 #define LEMAC_REG_EID3          0x83    /* EISA Identification 3 */
  77 #define LEMAC_REG_EIC           0x84    /* EISA Control */
  78
  79 /* Control Page (Page 0) Definitions */
  80
  81 #define LEMAC_MCTBL_BITS        9
  82 #define LEMAC_MCTBL_OFF         512
  83 #define LEMAC_MCTBL_SIZE        (1 << (LEMAC_MCTBL_BITS - 3))
  84 #define LEMAC_CRC32_POLY        0xEDB88320UL    /* CRC-32 Poly -- Little Endian) */
  85
  86 /* EEPROM Definitions */
  87
  88 #define LEMAC_EEP_CKSUM         0       /* The valid checksum is 0 */
  89 #define LEMAC_EEP_SIZE          32      /* EEPROM is 32 bytes */
  90 #define LEMAC_EEP_DELAY         2000    /* 2ms = 2000us */
  91 #define LEMAC_EEP_PRDNM         8       /* Product Name Offset */
  92 #define LEMAC_EEP_PRDNMSZ       8       /* Product Name Size */
  93 #define LEMAC_EEP_SWFLAGS       16      /* Software Options Offset */
  94 #define LEMAC_EEP_SETUP         23      /* Setup Options Offset */
  95
  96 #define LEMAC_EEP_SW_SQE        0x10    /* Enable TX_SQE on Transmits */
  97 #define LEMAC_EEP_SW_LAB        0x08    /* Enable TX_LAB on Transmits */
  98 #define LEMAC_EEP_ST_DRAM       0x02    /* Enable extra DRAM */
  99
 100 #define LEMAC_ADP_ROMSZ         32      /* Size of Address PROM */
 101
 102 /* Receive Status Definitions */
 103
 104 #define LEMAC_RX_PLL            0x01    /* Phase Lock Lost */
 105 #define LEMAC_RX_CRC            0x02    /* CRC Error */
 106 #define LEMAC_RX_DBE            0x04    /* Dribble Bit Error */
 107 #define LEMAC_RX_MCM            0x08    /* Multicast Match */
 108 #define LEMAC_RX_IAM            0x10    /* Individual Address Match */
 109 #define LEMAC_RX_OK             0x80    /* No Errors */
 110
 111 /* Transmit Status Definitions (not valid if TXD == 0) */
 112
 113 #define LEMAC_TS_RTRYMSK        0x0F    /* Retries of last TX PDU */
 114 #define LEMAC_TS_ECL            0x10    /* Excessive collision of ... */
 115 #define LEMAC_TS_LCL            0x20    /* Late collision of ... */
 116 #define LEMAC_TS_ID             0x40    /* Initially Deferred  ... */
 117 #define LEMAC_TS_NCL            0x08    /* No carrier loopback ... */
 118
 119 /* Transmit Control Definitions */
 120
 121 #define LEMAC_TX_ISA            0x01    /* Insert Source Address (no) */
 122 #define LEMAC_TX_IFC            0x02    /* Insert Frame Check (yes) */
 123 #define LEMAC_TX_PAD            0x04    /* Zero PAD to minimum length (yes) */
 124 #define LEMAC_TX_LAB            0x08    /* Less Agressive Backoff (no) */
 125 #define LEMAC_TX_QMD            0x10    /* Q-Mode (yes) */
 126 #define LEMAC_TX_STP            0x20    /* Stop on Error (no) */
 127 #define LEMAC_TX_SQE            0x40    /* SQE Enable (yes) */
 128
 129 #define LEMAC_TX_FLAGS          (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\
 130                                  LEMAC_TX_SQE)
 131 #define LEMAC_TX_HDRSZ          4       /* Size of TX header */
 132
 133 /* Transmit Done Queue Status Definitions */
 134
 135 #define LEMAC_TDQ_COL           0x03    /* Collision Mask */
 136 #define LEMAC_TDQ_NOCOL         0x00    /*   No Collisions */
 137 #define LEMAC_TDQ_ONECOL        0x01    /*   One Collision */
 138 #define LEMAC_TDQ_MULCOL        0x02    /*   Multiple Collisions */
 139 #define LEMAC_TDQ_EXCCOL        0x03    /*   Excessive Collisions */
 140 #define LEMAC_TDQ_ID            0x04    /* Initially Deferred */
 141 #define LEMAC_TDQ_LCL           0x08    /* Late Collision (will TX_STP) */
 142 #define LEMAC_TDQ_NCL           0x10    /* No carrier loopback */
 143 #define LEMAC_TDQ_SQE           0x20    /* SQE error */
 144
 145 /* Control / Status Definitions */
 146
 147 #define LEMAC_CS_RXD            0x01    /* Receiver Disabled */
 148 #define LEMAC_CS_TXD            0x02    /* Transmitter Disabled */
 149 #define LEMAC_CS_RNE            0x04    /* Receive Queue Not Empty */
 150 #define LEMAC_CS_TNE            0x08    /* Transmit Done Queue Not Empty */
 151 #define LEMAC_CS_MBZ4           0x10    /* MBZ */
 152 #define LEMAC_CS_MCE            0x20    /* Multicast Enable */
 153 #define LEMAC_CS_PME            0x40    /* Promiscuous Mode Enable */
 154 #define LEMAC_CS_RA             0x80    /* Runt Accept */
 155
 156 /* Control Definitions */
 157
 158 #define LEMAC_CTL_LED           0x02    /* LED state (inverted) */
 159 #define LEMAC_CTL_PSL           0x40    /* Port Select (1=AUI, 0=UTP) */
 160 #define LEMAC_CTL_APD           0x80    /* Auto Port Disable */
 161
 162 /* Interrupt Control Definitions */
 163
 164 #define LEMAC_IC_RXD            0x01    /* Enable RXD Interrupt */
 165 #define LEMAC_IC_TXD            0x02    /* Enable TXD Interrupt */
 166 #define LEMAC_IC_RNE            0x04    /* Enable RNE Interrupt */
 167 #define LEMAC_IC_TNE            0x08    /* Enable TNE Interrupt */
 168 #define LEMAC_IC_ALL            0x0F    /* Enable RXD,TXD,RNE,TNE */
 169 #define LEMAC_IC_IRQMSK         0x60    /* Interrupt Select */
 170 #define LEMAC_IC_IRQ5           0x00    /*   Select IRQ 5 */
 171 #define LEMAC_IC_IRQ10          0x20    /*   Select IRQ 10 */
 172 #define LEMAC_IC_IRQ11          0x40    /*   Select IRQ 11 */
 173 #define LEMAC_IC_IRQ15          0x60    /*   Select IRQ 15 */
 174 #define LEMAC_IC_IE             0x80    /* Interrupt Enable */
 175
 176 /* I/O Page Definitions */
 177
 178 #define LEMAC_IOP_EEINIT        0xC0    /* Perform a board init/reset */
 179 #define LEMAC_IOP_EEREAD        0xE0    /* Start a read from EEPROM */
 180
 181 /* Configuration / Management Definitions */
 182
 183 #define LEMAC_CNF_DRAM          0x02    /* Extra on-board DRAM is available */
 184 #define LEMAC_CNF_NOLINK        0x20    /* UTP port is UP */
 185
 186 #endif  /* _LEMAC_H_ */