sys/dev/ic/tcic2var.h

   1 /*      $NetBSD: tcic2var.h,v 1.11 2009/03/16 09:32:38 cegger Exp $     */
   2
   3 /*
   4  * Copyright (c) 1998, 1999 Christoph Badura.  All rights reserved.
   5  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Marc Horowitz.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef _TCIC2VAR_H
  34 #define _TCIC2VAR_H
  35
  36 #include <sys/device.h>
  37
  38 #include <dev/pcmcia/pcmciareg.h>
  39 #include <dev/pcmcia/pcmciachip.h>
  40
  41 #include <dev/ic/tcic2reg.h>
  42
  43 struct proc;
  44
  45 struct tcic_event {
  46         SIMPLEQ_ENTRY(tcic_event) pe_q;
  47         int pe_type;
  48 };
  49
  50 /* pe_type */
  51 #define TCIC_EVENT_INSERTION    0
  52 #define TCIC_EVENT_REMOVAL      1
  53
  54
  55 struct tcic_handle {
  56         struct tcic_softc *sc;
  57         int     sock;                           /* socket number */
  58         int     flags;
  59         int     sstat;                          /* last value of R_SSTAT */
  60         int     memalloc;
  61         int     memwins;
  62         struct {
  63                 bus_addr_t      addr;
  64                 bus_size_t      size;
  65                 int             size2;          /* size as 2^n scaled by 4K */
  66                 long            offset;
  67                 int             speed;          /* in ns */
  68                 int             kind;
  69         } mem[TCIC_MAX_MEM_WINS];
  70         int     ioalloc;
  71         struct {
  72                 bus_addr_t      addr;
  73                 bus_size_t      size;
  74                 int             width;
  75                 int             speed;          /* in ns */
  76         } io[TCIC_IO_WINS];
  77         int     ih_irq;
  78         device_t pcmcia;
  79
  80         int shutdown;
  81         struct lwp *event_thread;
  82         SIMPLEQ_HEAD(, tcic_event) events;
  83 };
  84
  85 #define TCIC_FLAG_SOCKETP       0x0001
  86 #define TCIC_FLAG_CARDP         0x0002
  87
  88 /*
  89  * This is sort of arbitrary.  It merely needs to be "enough". It can be
  90  * overridden in the conf file, anyway.
  91  */
  92
  93 #define TCIC_MEM_PAGES  4
  94 #define TCIC_MEMSIZE    TCIC_MEM_PAGES*TCIC_MEM_PAGESIZE
  95
  96 #define TCIC_NSLOTS     2
  97
  98 struct tcic_softc {
  99         struct device dev;
 100
 101         bus_space_tag_t memt;
 102         bus_space_handle_t memh;
 103         bus_space_tag_t iot;
 104         bus_space_handle_t ioh;
 105
 106         int     chipid;
 107         int     validirqs;
 108         int     pwrena;         /* holds TCIC_PWR_ENA on'084 and successors */
 109
 110         /* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */
 111         void    *intr_est;
 112
 113         pcmcia_chipset_tag_t pct;
 114
 115         /* this needs to be large enough to hold TCIC_MEM_PAGES bits */
 116         int     subregionmask;
 117
 118         /* used by memory window mapping functions */
 119         bus_addr_t membase;
 120         int     memsize2;               /* int(log2(memsize)) */
 121
 122         /*
 123          * used by io window mapping functions.  These can actually overlap
 124          * with another tcic, since the underlying extent mapper will deal
 125          * with individual allocations.  This is here to deal with the fact
 126          * that different busses have different real widths (different pc
 127          * hardware seems to use 10 or 12 bits for the I/O bus).
 128          */
 129         bus_addr_t iobase;
 130         bus_size_t iosize;
 131
 132         int     irq;
 133         void    *ih;
 134
 135         struct tcic_handle handle[TCIC_NSLOTS];
 136 };
 137
 138 int     tcic_log2(u_int);
 139 int     tcic_ns2wscnt(int);
 140
 141 int     tcic_check_reserved_bits(bus_space_tag_t, bus_space_handle_t);
 142 int     tcic_chipid(bus_space_tag_t, bus_space_handle_t);
 143 int     tcic_chipid_known(int);
 144 const char *tcic_chipid_to_string(int);
 145 int     tcic_validirqs(int);
 146
 147 void    tcic_attach(struct tcic_softc *);
 148 void    tcic_attach_sockets(struct tcic_softc *);
 149 int     tcic_intr(void *arg);
 150
 151 static __inline int tcic_read_1(struct tcic_handle *, int);
 152 static __inline int tcic_read_2(struct tcic_handle *, int);
 153 static __inline int tcic_read_4(struct tcic_handle *, int);
 154 static __inline void tcic_write_1(struct tcic_handle *, int, int);
 155 static __inline void tcic_write_2(struct tcic_handle *, int, int);
 156 static __inline void tcic_write_4(struct tcic_handle *, int, int);
 157 static __inline int tcic_read_ind_2(struct tcic_handle *, int);
 158 static __inline void tcic_write_ind_2(struct tcic_handle *, int, int);
 159 static __inline void tcic_sel_sock(struct tcic_handle *);
 160 static __inline void tcic_wait_ready(struct tcic_handle *);
 161 static __inline int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int);
 162 static __inline int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int);
 163 static __inline void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int);
 164 static __inline void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int);
 165
 166 int     tcic_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
 167             struct pcmcia_mem_handle *);
 168 void    tcic_chip_mem_free(pcmcia_chipset_handle_t,
 169             struct pcmcia_mem_handle *);
 170 int     tcic_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
 171             bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
 172 void    tcic_chip_mem_unmap(pcmcia_chipset_handle_t, int);
 173
 174 int     tcic_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
 175             bus_size_t, bus_size_t, struct pcmcia_io_handle *);
 176 void    tcic_chip_io_free(pcmcia_chipset_handle_t,
 177             struct pcmcia_io_handle *);
 178 int     tcic_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
 179             bus_size_t, struct pcmcia_io_handle *, int *);
 180 void    tcic_chip_io_unmap(pcmcia_chipset_handle_t, int);
 181
 182 void    tcic_chip_socket_enable(pcmcia_chipset_handle_t);
 183 void    tcic_chip_socket_disable(pcmcia_chipset_handle_t);
 184 void    tcic_chip_socket_settype(pcmcia_chipset_handle_t, int);
 185
 186 static __inline int tcic_read_1(struct tcic_handle *, int);
 187 static __inline int
 188 tcic_read_1(struct tcic_handle *h, int reg)
 189 {
 190         return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));
 191 }
 192
 193 static __inline int tcic_read_2(struct tcic_handle *, int);
 194 static __inline int
 195 tcic_read_2(struct tcic_handle *h, int reg)
 196 {
 197         return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));
 198 }
 199
 200 static __inline int tcic_read_4(struct tcic_handle *, int);
 201 static __inline int
 202 tcic_read_4(struct tcic_handle *h, int reg)
 203 {
 204         int val;
 205         val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
 206         val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
 207         return val;
 208 }
 209
 210 static __inline void tcic_write_1(struct tcic_handle *, int, int);
 211 static __inline void
 212 tcic_write_1(struct tcic_handle *h, int reg, int data)
 213 {
 214         bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data));
 215 }
 216
 217 static __inline void tcic_write_2(struct tcic_handle *, int, int);
 218 static __inline void
 219 tcic_write_2(struct tcic_handle *h, int reg, int data)
 220 {
 221         bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
 222 }
 223
 224 static __inline void tcic_write_4(struct tcic_handle *, int, int);
 225 static __inline void
 226 tcic_write_4(struct tcic_handle *h, int reg, int data)
 227 {
 228         bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data));
 229         bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16);
 230 }
 231
 232 static __inline int tcic_read_ind_2(struct tcic_handle *, int);
 233 static __inline int
 234 tcic_read_ind_2(struct tcic_handle *h, int reg)
 235 {
 236         int r_addr, val;
 237         r_addr = tcic_read_4(h, TCIC_R_ADDR);
 238         tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
 239         val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA);
 240         tcic_write_4(h, TCIC_R_ADDR, r_addr);
 241         return val;
 242 }
 243
 244 static __inline void tcic_write_ind_2(struct tcic_handle *, int, int);
 245 static __inline void
 246 tcic_write_ind_2(struct tcic_handle *h, int reg, int data)
 247 {
 248         int r_addr;
 249         r_addr = tcic_read_4(h, TCIC_R_ADDR);
 250         tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG);
 251         bus_space_write_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA, (data));
 252         tcic_write_4(h, TCIC_R_ADDR, r_addr);
 253 }
 254
 255 static __inline void tcic_sel_sock(struct tcic_handle *);
 256 static __inline void
 257 tcic_sel_sock(struct tcic_handle *h)
 258 {
 259         int r_addr;
 260         r_addr = tcic_read_2(h, TCIC_R_ADDR2);
 261         tcic_write_2(h, TCIC_R_ADDR2,
 262             (h->sock<<TCIC_ADDR2_SS_SHFT)|(r_addr & ~TCIC_ADDR2_SS_MASK));
 263 }
 264
 265 static __inline void tcic_wait_ready(struct tcic_handle *);
 266 static __inline void
 267 tcic_wait_ready(struct tcic_handle *h)
 268 {
 269         int i;
 270
 271         /* XXX appropriate socket must have been selected already. */
 272         for (i = 0; i < 10000; i++) {
 273                 if (tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_RDY)
 274                         return;
 275                 delay(500);
 276         }
 277
 278 #ifdef DIAGNOSTIC
 279         printf("tcic_wait_ready ready never happened\n");
 280 #endif
 281 }
 282
 283 static __inline int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int);
 284 static __inline int
 285 tcic_read_aux_1(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, int reg)
 286 {
 287         int mode, val;
 288         mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
 289         bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
 290         val = bus_space_read_1(iot, ioh, reg);
 291         return val;
 292 }
 293
 294 static __inline int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int);
 295 static __inline int
 296 tcic_read_aux_2(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg)
 297 {
 298         int mode, val;
 299         mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
 300         bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
 301         val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
 302         return val;
 303 }
 304
 305 static __inline void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int);
 306 static __inline void
 307 tcic_write_aux_1(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, int reg, int val)
 308 {
 309         int mode;
 310         mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
 311         bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
 312         bus_space_write_1(iot, ioh, reg, val);
 313 }
 314
 315 static __inline void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int);
 316 static __inline void
 317 tcic_write_aux_2(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, int val)
 318 {
 319         int mode;
 320         mode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
 321         bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg);
 322         bus_space_write_2(iot, ioh, TCIC_R_AUX, val);
 323 }
 324
 325 #endif  /* _TCIC2VAR_H */