sys/dev/ieee1394/fwohcireg.h

   1 /*      $NetBSD: fwohcireg.h,v 1.16 2007/03/04 06:02:07 christos Exp $  */
   2
   3 /*-
   4  * Copyright (c) 2003 Hidetoshi Shimokawa
   5  * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the acknowledgement as bellow:
  18  *
  19  *    This product includes software developed by K. Kobayashi and H. Shimokawa
  20  *
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  32  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  33  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * $FreeBSD: src/sys/dev/firewire/fwohcireg.h,v 1.23 2007/04/30 14:06:30 simokawa Exp $
  37  *
  38  */
  39 #define         PCI_CBMEM               PCIR_BAR(0)
  40
  41 #define         FW_VENDORID_NATSEMI     0x100B
  42 #define         FW_VENDORID_NEC         0x1033
  43 #define         FW_VENDORID_SIS         0x1039
  44 #define         FW_VENDORID_TI          0x104c
  45 #define         FW_VENDORID_SONY        0x104d
  46 #define         FW_VENDORID_VIA         0x1106
  47 #define         FW_VENDORID_RICOH       0x1180
  48 #define         FW_VENDORID_APPLE       0x106b
  49 #define         FW_VENDORID_LUCENT      0x11c1
  50 #define         FW_VENDORID_INTEL       0x8086
  51 #define         FW_VENDORID_ADAPTEC     0x9004
  52 #define         FW_VENDORID_SUN         0x108e
  53
  54 #define         FW_DEVICE_CS4210        (0x000f << 16)
  55 #define         FW_DEVICE_UPD861        (0x0063 << 16)
  56 #define         FW_DEVICE_UPD871        (0x00ce << 16)
  57 #define         FW_DEVICE_UPD72870      (0x00cd << 16)
  58 #define         FW_DEVICE_UPD72873      (0x00e7 << 16)
  59 #define         FW_DEVICE_UPD72874      (0x00f2 << 16)
  60 #define         FW_DEVICE_TITSB22       (0x8009 << 16)
  61 #define         FW_DEVICE_TITSB23       (0x8019 << 16)
  62 #define         FW_DEVICE_TITSB26       (0x8020 << 16)
  63 #define         FW_DEVICE_TITSB43       (0x8021 << 16)
  64 #define         FW_DEVICE_TITSB43A      (0x8023 << 16)
  65 #define         FW_DEVICE_TITSB43AB23   (0x8024 << 16)
  66 #define         FW_DEVICE_TITSB82AA2    (0x8025 << 16)
  67 #define         FW_DEVICE_TITSB43AB21   (0x8026 << 16)
  68 #define         FW_DEVICE_TIPCI4410A    (0x8017 << 16)
  69 #define         FW_DEVICE_TIPCI4450     (0x8011 << 16)
  70 #define         FW_DEVICE_TIPCI4451     (0x8027 << 16)
  71 #define         FW_DEVICE_CXD1947       (0x8009 << 16)
  72 #define         FW_DEVICE_CXD3222       (0x8039 << 16)
  73 #define         FW_DEVICE_VT6306        (0x3044 << 16)
  74 #define         FW_DEVICE_R5C551        (0x0551 << 16)
  75 #define         FW_DEVICE_R5C552        (0x0552 << 16)
  76 #define         FW_DEVICE_PANGEA        (0x0030 << 16)
  77 #define         FW_DEVICE_UNINORTH      (0x0031 << 16)
  78 #define         FW_DEVICE_AIC5800       (0x5800 << 16)
  79 #define         FW_DEVICE_FW322         (0x5811 << 16)
  80 #define         FW_DEVICE_7007          (0x7007 << 16)
  81 #define         FW_DEVICE_82372FB       (0x7605 << 16)
  82 #define         FW_DEVICE_PCIO2FW       (0x1102 << 16)
  83
  84 #define PCI_INTERFACE_OHCI      0x10
  85
  86 #if defined(__FreeBSD__)
  87 #define FW_OHCI_BASE_REG        0x10
  88 #elif defined(__NetBSD__)
  89 #define PCI_OHCI_MAP_REGISTER   0x10
  90 #endif
  91
  92 #define         OHCI_DMA_ITCH           0x20
  93 #define         OHCI_DMA_IRCH           0x20
  94
  95 #define         OHCI_MAX_DMA_CH         (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
  96
  97
  98 typedef uint32_t        fwohcireg_t;
  99
 100 /* for PCI */
 101 #if BYTE_ORDER == BIG_ENDIAN
 102 #define FWOHCI_DMA_WRITE(x, y)  ((x) = htole32(y))
 103 #define FWOHCI_DMA_READ(x)      le32toh(x)
 104 #define FWOHCI_DMA_SET(x, y)    ((x) |= htole32(y))
 105 #define FWOHCI_DMA_CLEAR(x, y)  ((x) &= htole32(~(y)))
 106 #else
 107 #define FWOHCI_DMA_WRITE(x, y)  ((x) = (y))
 108 #define FWOHCI_DMA_READ(x)      (x)
 109 #define FWOHCI_DMA_SET(x, y)    ((x) |= (y))
 110 #define FWOHCI_DMA_CLEAR(x, y)  ((x) &= ~(y))
 111 #endif
 112
 113 struct fwohcidb {
 114         union {
 115                 struct {
 116                         uint32_t cmd;
 117                         uint32_t addr;
 118                         uint32_t depend;
 119                         uint32_t res;
 120                 } desc;
 121                 uint32_t immed[4];
 122         } db;
 123 #define OHCI_STATUS_SHIFT       16
 124 #define OHCI_COUNT_MASK         0xffff
 125 #define OHCI_OUTPUT_MORE        (0 << 28)
 126 #define OHCI_OUTPUT_LAST        (1 << 28)
 127 #define OHCI_INPUT_MORE         (2 << 28)
 128 #define OHCI_INPUT_LAST         (3 << 28)
 129 #define OHCI_STORE_QUAD         (4 << 28)
 130 #define OHCI_LOAD_QUAD          (5 << 28)
 131 #define OHCI_NOP                (6 << 28)
 132 #define OHCI_STOP               (7 << 28)
 133 #define OHCI_STORE              (8 << 28)
 134 #define OHCI_CMD_MASK           (0xf << 28)
 135
 136 #define OHCI_UPDATE             (1 << 27)
 137
 138 #define OHCI_KEY_ST0            (0 << 24)
 139 #define OHCI_KEY_ST1            (1 << 24)
 140 #define OHCI_KEY_ST2            (2 << 24)
 141 #define OHCI_KEY_ST3            (3 << 24)
 142 #define OHCI_KEY_REGS           (5 << 24)
 143 #define OHCI_KEY_SYS            (6 << 24)
 144 #define OHCI_KEY_DEVICE         (7 << 24)
 145 #define OHCI_KEY_MASK           (7 << 24)
 146
 147 #define OHCI_INTERRUPT_NEVER    (0 << 20)
 148 #define OHCI_INTERRUPT_TRUE     (1 << 20)
 149 #define OHCI_INTERRUPT_FALSE    (2 << 20)
 150 #define OHCI_INTERRUPT_ALWAYS   (3 << 20)
 151
 152 #define OHCI_BRANCH_NEVER       (0 << 18)
 153 #define OHCI_BRANCH_TRUE        (1 << 18)
 154 #define OHCI_BRANCH_FALSE       (2 << 18)
 155 #define OHCI_BRANCH_ALWAYS      (3 << 18)
 156 #define OHCI_BRANCH_MASK        (3 << 18)
 157
 158 #define OHCI_WAIT_NEVER         (0 << 16)
 159 #define OHCI_WAIT_TRUE          (1 << 16)
 160 #define OHCI_WAIT_FALSE         (2 << 16)
 161 #define OHCI_WAIT_ALWAYS        (3 << 16)
 162 };
 163
 164 #define OHCI_SPD_S100 0x4
 165 #define OHCI_SPD_S200 0x1
 166 #define OHCI_SPD_S400 0x2
 167
 168
 169 #define FWOHCIEV_NOSTAT 0
 170 #define FWOHCIEV_LONGP 2
 171 #define FWOHCIEV_MISSACK 3
 172 #define FWOHCIEV_UNDRRUN 4
 173 #define FWOHCIEV_OVRRUN 5
 174 #define FWOHCIEV_DESCERR 6
 175 #define FWOHCIEV_DTRDERR 7
 176 #define FWOHCIEV_DTWRERR 8
 177 #define FWOHCIEV_BUSRST 9
 178 #define FWOHCIEV_TIMEOUT 0xa
 179 #define FWOHCIEV_TCODERR 0xb
 180 #define FWOHCIEV_UNKNOWN 0xe
 181 #define FWOHCIEV_FLUSHED 0xf
 182 #define FWOHCIEV_ACKCOMPL 0x11
 183 #define FWOHCIEV_ACKPEND 0x12
 184 #define FWOHCIEV_ACKBSX 0x14
 185 #define FWOHCIEV_ACKBSA 0x15
 186 #define FWOHCIEV_ACKBSB 0x16
 187 #define FWOHCIEV_ACKTARD 0x1b
 188 #define FWOHCIEV_ACKDERR 0x1d
 189 #define FWOHCIEV_ACKTERR 0x1e
 190
 191 #define FWOHCIEV_MASK 0x1f
 192
 193 struct ohci_dma{
 194         fwohcireg_t     cntl;
 195
 196 #define OHCI_CNTL_CYCMATCH_S    (0x1 << 31)
 197
 198 #define OHCI_CNTL_BUFFIL        (0x1 << 31)
 199 #define OHCI_CNTL_ISOHDR        (0x1 << 30)
 200 #define OHCI_CNTL_CYCMATCH_R    (0x1 << 29)
 201 #define OHCI_CNTL_MULTICH       (0x1 << 28)
 202
 203 #define OHCI_CNTL_DMA_RUN       (0x1 << 15)
 204 #define OHCI_CNTL_DMA_WAKE      (0x1 << 12)
 205 #define OHCI_CNTL_DMA_DEAD      (0x1 << 11)
 206 #define OHCI_CNTL_DMA_ACTIVE    (0x1 << 10)
 207 #define OHCI_CNTL_DMA_BT        (0x1 << 8)
 208 #define OHCI_CNTL_DMA_BAD       (0x1 << 7)
 209 #define OHCI_CNTL_DMA_STAT      (0xff)
 210
 211         fwohcireg_t     cntl_clr;
 212         fwohcireg_t     dummy0;
 213         fwohcireg_t     cmd;
 214         fwohcireg_t     match;
 215         fwohcireg_t     dummy1;
 216         fwohcireg_t     dummy2;
 217         fwohcireg_t     dummy3;
 218 };
 219
 220 struct ohci_itdma{
 221         fwohcireg_t     cntl;
 222         fwohcireg_t     cntl_clr;
 223         fwohcireg_t     dummy0;
 224         fwohcireg_t     cmd;
 225 };
 226
 227 struct ohci_registers {
 228         fwohcireg_t     ver;            /* Version No. 0x0 */
 229         fwohcireg_t     guid;           /* GUID_ROM No. 0x4 */
 230         fwohcireg_t     retry;          /* AT retries 0x8 */
 231 #define FWOHCI_RETRY    0x8
 232         fwohcireg_t     csr_data;       /* CSR data   0xc */
 233         fwohcireg_t     csr_cmp;        /* CSR compare 0x10 */
 234         fwohcireg_t     csr_cntl;       /* CSR compare 0x14 */
 235         fwohcireg_t     rom_hdr;        /* config ROM ptr. 0x18 */
 236         fwohcireg_t     bus_id;         /* BUS_ID 0x1c */
 237         fwohcireg_t     bus_opt;        /* BUS option 0x20 */
 238 #define FWOHCIGUID_H    0x24
 239 #define FWOHCIGUID_L    0x28
 240         fwohcireg_t     guid_hi;        /* GUID hi 0x24 */
 241         fwohcireg_t     guid_lo;        /* GUID lo 0x28 */
 242         fwohcireg_t     dummy0[2];      /* dummy 0x2c-0x30 */
 243         fwohcireg_t     config_rom;     /* config ROM map 0x34 */
 244         fwohcireg_t     post_wr_lo;     /* post write addr lo 0x38 */
 245         fwohcireg_t     post_wr_hi;     /* post write addr hi 0x3c */
 246         fwohcireg_t     vender;         /* vender ID 0x40 */
 247         fwohcireg_t     dummy1[3];      /* dummy 0x44-0x4c */
 248         fwohcireg_t     hcc_cntl_set;   /* HCC control set 0x50 */
 249         fwohcireg_t     hcc_cntl_clr;   /* HCC control clr 0x54 */
 250 #define OHCI_HCC_BIBIV  (1 << 31)       /* BIBimage Valid */
 251 #define OHCI_HCC_BIGEND (1 << 30)       /* noByteSwapData */
 252 #define OHCI_HCC_PRPHY  (1 << 23)       /* programPhyEnable */
 253 #define OHCI_HCC_PHYEN  (1 << 22)       /* aPhyEnhanceEnable */
 254 #define OHCI_HCC_LPS    (1 << 19)       /* LPS */
 255 #define OHCI_HCC_POSTWR (1 << 18)       /* postedWriteEnable */
 256 #define OHCI_HCC_LINKEN (1 << 17)       /* linkEnable */
 257 #define OHCI_HCC_RESET  (1 << 16)       /* softReset */
 258         fwohcireg_t     dummy2[2];      /* dummy 0x58-0x5c */
 259         fwohcireg_t     dummy3[1];      /* dummy 0x60 */
 260         fwohcireg_t     sid_buf;        /* self id buffer 0x64 */
 261         fwohcireg_t     sid_cnt;        /* self id count 0x68 */
 262         fwohcireg_t     dummy4[1];      /* dummy 0x6c */
 263         fwohcireg_t     ir_mask_hi_set; /* ir mask hi set 0x70 */
 264         fwohcireg_t     ir_mask_hi_clr; /* ir mask hi set 0x74 */
 265         fwohcireg_t     ir_mask_lo_set; /* ir mask hi set 0x78 */
 266         fwohcireg_t     ir_mask_lo_clr; /* ir mask hi set 0x7c */
 267 #define FWOHCI_INTSTAT          0x80
 268 #define FWOHCI_INTSTATCLR       0x84
 269 #define FWOHCI_INTMASK          0x88
 270 #define FWOHCI_INTMASKCLR       0x8c
 271         fwohcireg_t     int_stat;   /*       0x80 */
 272         fwohcireg_t     int_clear;  /*       0x84 */
 273         fwohcireg_t     int_mask;   /*       0x88 */
 274         fwohcireg_t     int_mask_clear;   /*       0x8c */
 275         fwohcireg_t     it_int_stat;   /*       0x90 */
 276         fwohcireg_t     it_int_clear;  /*       0x94 */
 277         fwohcireg_t     it_int_mask;   /*       0x98 */
 278         fwohcireg_t     it_mask_clear;   /*       0x9c */
 279         fwohcireg_t     ir_int_stat;   /*       0xa0 */
 280         fwohcireg_t     ir_int_clear;  /*       0xa4 */
 281         fwohcireg_t     ir_int_mask;   /*       0xa8 */
 282         fwohcireg_t     ir_mask_clear;   /*       0xac */
 283         fwohcireg_t     dummy5[11];     /* dummy 0xb0-d8 */
 284         fwohcireg_t     fairness;   /* fairness control      0xdc */
 285         fwohcireg_t     link_cntl;              /* Chip control 0xe0*/
 286         fwohcireg_t     link_cntl_clr;  /* Chip control clear 0xe4*/
 287 #define FWOHCI_NODEID   0xe8
 288         fwohcireg_t     node;           /* Node ID 0xe8 */
 289 #define OHCI_NODE_VALID (1 << 31)
 290 #define OHCI_NODE_ROOT  (1 << 30)
 291
 292 #define OHCI_ASYSRCBUS  1
 293
 294         fwohcireg_t     phy_access;     /* PHY cntl 0xec */
 295 #define PHYDEV_RDDONE           (1<<31)
 296 #define PHYDEV_RDCMD            (1<<15)
 297 #define PHYDEV_WRCMD            (1<<14)
 298 #define PHYDEV_REGADDR          8
 299 #define PHYDEV_WRDATA           0
 300 #define PHYDEV_RDADDR           24
 301 #define PHYDEV_RDDATA           16
 302
 303         fwohcireg_t     cycle_timer;    /* Cycle Timer 0xf0 */
 304         fwohcireg_t     dummy6[3];      /* dummy 0xf4-fc */
 305         fwohcireg_t     areq_hi;        /* Async req. filter hi 0x100 */
 306         fwohcireg_t     areq_hi_clr;    /* Async req. filter hi 0x104 */
 307         fwohcireg_t     areq_lo;        /* Async req. filter lo 0x108 */
 308         fwohcireg_t     areq_lo_clr;    /* Async req. filter lo 0x10c */
 309         fwohcireg_t     preq_hi;        /* Async req. filter hi 0x110 */
 310         fwohcireg_t     preq_hi_clr;    /* Async req. filter hi 0x114 */
 311         fwohcireg_t     preq_lo;        /* Async req. filter lo 0x118 */
 312         fwohcireg_t     preq_lo_clr;    /* Async req. filter lo 0x11c */
 313
 314         fwohcireg_t     pys_upper;      /* Physical Upper bound 0x120 */
 315
 316         fwohcireg_t     dummy7[23];     /* dummy 0x124-0x17c */
 317
 318         /*       0x180, 0x184, 0x188, 0x18c */
 319         /*       0x190, 0x194, 0x198, 0x19c */
 320         /*       0x1a0, 0x1a4, 0x1a8, 0x1ac */
 321         /*       0x1b0, 0x1b4, 0x1b8, 0x1bc */
 322         /*       0x1c0, 0x1c4, 0x1c8, 0x1cc */
 323         /*       0x1d0, 0x1d4, 0x1d8, 0x1dc */
 324         /*       0x1e0, 0x1e4, 0x1e8, 0x1ec */
 325         /*       0x1f0, 0x1f4, 0x1f8, 0x1fc */
 326         struct ohci_dma dma_ch[0x4];
 327
 328         /*       0x200, 0x204, 0x208, 0x20c */
 329         /*       0x210, 0x204, 0x208, 0x20c */
 330         struct ohci_itdma dma_itch[0x20];
 331
 332         /*       0x400, 0x404, 0x408, 0x40c */
 333         /*       0x410, 0x404, 0x408, 0x40c */
 334         struct ohci_dma dma_irch[0x20];
 335 };
 336
 337 struct fwohcidb_tr{
 338         STAILQ_ENTRY(fwohcidb_tr) link;
 339         struct fw_xfer *xfer;
 340         struct fwohcidb *db;
 341         bus_dmamap_t dma_map;
 342         void *buf;
 343         bus_addr_t bus_addr;
 344         int dbcnt;
 345 };
 346
 347 /*
 348  * OHCI info structure.
 349  */
 350 struct fwohci_txpkthdr{
 351         union{
 352                 uint32_t ld[4];
 353                 struct {
 354 #if BYTE_ORDER == BIG_ENDIAN
 355                         uint32_t spd:16, /* XXX include reserved field */
 356                                  :8,
 357                                  tcode:4,
 358                                  :4;
 359 #else
 360                         uint32_t :4,
 361                                  tcode:4,
 362                                  :8,
 363                                  spd:16; /* XXX include reserved fields */
 364 #endif
 365                 }common;
 366                 struct {
 367 #if BYTE_ORDER == BIG_ENDIAN
 368                         uint32_t :8,
 369                                  srcbus:1,
 370                                  :4,
 371                                  spd:3,
 372                                  tlrt:8,
 373                                  tcode:4,
 374                                  :4;
 375 #else
 376                         uint32_t :4,
 377                                  tcode:4,
 378                                  tlrt:8,
 379                                  spd:3,
 380                                  :4,
 381                                  srcbus:1,
 382                                  :8;
 383 #endif
 384                         BIT16x2(dst, );
 385                 }asycomm;
 386                 struct {
 387 #if BYTE_ORDER == BIG_ENDIAN
 388                         uint32_t :13,
 389                                  spd:3,
 390                                  chtag:8,
 391                                  tcode:4,
 392                                  sy:4;
 393 #else
 394                         uint32_t sy:4,
 395                                  tcode:4,
 396                                  chtag:8,
 397                                  spd:3,
 398                                  :13;
 399 #endif
 400                         BIT16x2(len, );
 401                 }stream;
 402         }mode;
 403 };
 404 struct fwohci_trailer{
 405 #if BYTE_ORDER == BIG_ENDIAN
 406         uint32_t stat:16,
 407                   time:16;
 408 #else
 409         uint32_t time:16,
 410                   stat:16;
 411 #endif
 412 };
 413
 414 #define OHCI_CNTL_CYCSRC        (0x1 << 22)
 415 #define OHCI_CNTL_CYCMTR        (0x1 << 21)
 416 #define OHCI_CNTL_CYCTIMER      (0x1 << 20)
 417 #define OHCI_CNTL_PHYPKT        (0x1 << 10)
 418 #define OHCI_CNTL_SID           (0x1 << 9)
 419
 420 #define OHCI_INT_DMA_ATRQ       (0x1 << 0)
 421 #define OHCI_INT_DMA_ATRS       (0x1 << 1)
 422 #define OHCI_INT_DMA_ARRQ       (0x1 << 2)
 423 #define OHCI_INT_DMA_ARRS       (0x1 << 3)
 424 #define OHCI_INT_DMA_PRRQ       (0x1 << 4)
 425 #define OHCI_INT_DMA_PRRS       (0x1 << 5)
 426 #define OHCI_INT_DMA_IT (0x1 << 6)
 427 #define OHCI_INT_DMA_IR (0x1 << 7)
 428 #define OHCI_INT_PW_ERR (0x1 << 8)
 429 #define OHCI_INT_LR_ERR (0x1 << 9)
 430
 431 #define OHCI_INT_PHY_SID        (0x1 << 16)
 432 #define OHCI_INT_PHY_BUS_R      (0x1 << 17)
 433
 434 #define OHCI_INT_REG_FAIL       (0x1 << 18)
 435
 436 #define OHCI_INT_PHY_INT        (0x1 << 19)
 437 #define OHCI_INT_CYC_START      (0x1 << 20)
 438 #define OHCI_INT_CYC_64SECOND   (0x1 << 21)
 439 #define OHCI_INT_CYC_LOST       (0x1 << 22)
 440 #define OHCI_INT_CYC_ERR        (0x1 << 23)
 441
 442 #define OHCI_INT_ERR            (0x1 << 24)
 443 #define OHCI_INT_CYC_LONG       (0x1 << 25)
 444 #define OHCI_INT_PHY_REG        (0x1 << 26)
 445
 446 #define OHCI_INT_EN             (0x1 << 31)
 447
 448 #define IP_CHANNELS             0x0234
 449 #define FWOHCI_MAXREC           2048
 450
 451 #define OHCI_ISORA              0x02
 452 #define OHCI_ISORB              0x04
 453
 454 #define FWOHCITCODE_PHY         0xe