sys/dev/ieee1394/fwphyreg.h

   1 /*      $NetBSD: fwphyreg.h,v 1.1.6.1 2005/11/10 14:05:22 skrll Exp $   */
   2 /*-
   3  * Copyright (C) 2003
   4  *      Hidetoshi Shimokawa. All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *
  17  *      This product includes software developed by Hidetoshi Shimokawa.
  18  *
  19  * 4. Neither the name of the author nor the names of its contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  27  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  29  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwphyreg.h,v 1.3 2005/01/06 01:42:41 imp Exp $
  36  */
  37
  38 struct phyreg_base {
  39 #if BYTE_ORDER == BIG_ENDIAN
  40         uint8_t phy_id:6,
  41                 r:1,
  42                 cps:1;
  43         uint8_t rhb:1,
  44                 ibr:1,
  45                 gap_count:6;
  46         uint8_t extended:3,
  47                 num_ports:5;
  48         uint8_t phy_speed:3,
  49                 :1,
  50                 delay:4;
  51         uint8_t lctrl:1,
  52                 c:1,
  53                 jitter:3,
  54                 pwr_class:3;
  55         uint8_t wdie:1,
  56                 isbr:1,
  57                 ctoi:1,
  58                 cpsi:1,
  59                 stoi:1,
  60                 pei:1,
  61                 eaa:1,
  62                 emc:1;
  63         uint8_t legacy_spd:3,
  64                 blink:1,
  65                 bridge:2,
  66                 :2;
  67         uint8_t page_select:3,
  68                 :1,
  69                 port_select:4;
  70 #else
  71         uint8_t cps:1,
  72                 r:1,
  73                 phy_id:6;
  74         uint8_t gap_count:6,
  75                 ibr:1,
  76                 rhb:1;
  77         uint8_t num_ports:5,
  78                 extended:3;
  79         uint8_t delay:4,
  80                 :1,
  81                 phy_speed:3;
  82         uint8_t pwr_class:3,
  83                 jitter:3,
  84                 c:1,
  85                 lctrl:1;
  86         uint8_t emc:1,
  87                 eaa:1,
  88                 pei:1,
  89                 stoi:1,
  90                 cpsi:1,
  91                 ctoi:1,
  92                 isbr:1,
  93                 wdie:1;
  94         uint8_t :2,
  95                 bridge:2,
  96                 blink:1,
  97                 legacy_spd:3;
  98         uint8_t port_select:4,
  99                 :1,
 100                 page_select:3;
 101 #endif
 102 };
 103
 104 struct phyreg_page0 {
 105 #if BYTE_ORDER == BIG_ENDIAN
 106         uint8_t astat:2,
 107                 bstat:2,
 108                 ch:1,
 109                 con:1,
 110                 rxok:1,
 111                 dis:1;
 112         uint8_t negotiated_speed:3,
 113                 pie:1,
 114                 fault:1,
 115                 stanby_fault:1,
 116                 disscrm:1,
 117                 b_only:1;
 118         uint8_t dc_connected:1,
 119                 max_port_speed:3,
 120                 lpp:1,
 121                 cable_speed:3;
 122         uint8_t connection_unreliable:1,
 123                 :3,
 124                 beta_mode:1,
 125                 :3;
 126         uint8_t port_error;
 127         uint8_t :5,
 128                 loop_disable:1,
 129                 in_standby:1,
 130                 hard_disable:1;
 131         uint8_t :8;
 132         uint8_t :8;
 133 #else
 134         uint8_t dis:1,
 135                 rxok:1,
 136                 con:1,
 137                 ch:1,
 138                 bstat:2,
 139                 astat:2;
 140         uint8_t b_only:1,
 141                 disscrm:1,
 142                 stanby_fault:1,
 143                 fault:1,
 144                 pie:1,
 145                 negotiated_speed:3;
 146         uint8_t cable_speed:3,
 147                 lpp:1,
 148                 max_port_speed:3,
 149                 dc_connected:1;
 150         uint8_t :3,
 151                 beta_mode:1,
 152                 :3,
 153                 connection_unreliable:1;
 154         uint8_t port_error;
 155         uint8_t hard_disable:1,
 156                 in_standby:1,
 157                 loop_disable:1,
 158                 :5;
 159         uint8_t :8;
 160         uint8_t :8;
 161 #endif
 162 };
 163
 164 struct phyreg_page1 {
 165         uint8_t compliance;
 166         uint8_t :8;
 167         uint8_t vendor_id[3];
 168         uint8_t product_id[3];
 169 };