sys/dev/marvell/gtidmareg.h

   1 /*      $NetBSD: gtidmareg.h,v 1.5 2006/02/16 20:17:19 perry Exp $      */
   2
   3 /*
   4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed for the NetBSD Project by
  18  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
  19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
  20  *    or promote products derived from this software without specific prior
  21  *    written permission.
  22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
  23  *    or promote products derived from this software without specific prior
  24  *    written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
  27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * idmareg.h - register & descriptor definitions for GT-64260 IDMA
  42  *
  43  * creation     Wed Aug 15 08:58:37 PDT 2001    cliff
  44  */
  45
  46 #ifndef _IDMAREG_H
  47 #define _IDMAREG_H
  48
  49 #define NIDMA_CHANS     8
  50 #define IDMA_BOUNDARY   1024*1024         /* boundary for bus_dmamap_create */
  51
  52 #define IDMA_BIT(bitno)   (1U << (bitno))
  53 #define IDMA_BITS(hi, lo) ((unsigned int)(~((~0ULL)<<((hi)+1)))&((~0)<<(lo)))
  54
  55 #define IDMA_WORD_SHIFT         2       /* log2(sizeof(u_int32_t) */
  56
  57
  58 static volatile __inline unsigned int
  59 idma_desc_read(u_int32_t *ip)
  60 {
  61         u_int32_t rv;
  62
  63         __asm volatile ("lwbrx %0,0,%1; eieio;"
  64                 : "=r"(rv) : "r"(ip));
  65         return rv;
  66 }
  67
  68 static volatile __inline void
  69 idma_desc_write(u_int32_t *ip, u_int32_t val)
  70 {
  71         __asm volatile ("stwbrx %0,0,%1; eieio;"
  72                 :: "r"(val), "r"(ip));
  73 }
  74
  75 typedef struct idma_desc {
  76         u_int32_t idd_ctl;
  77         u_int32_t idd_src_addr;
  78         u_int32_t idd_dst_addr;
  79         u_int32_t idd_next;
  80         u_int32_t idd_pad[4];   /* pad to CACHELINESIZE */
  81 } idma_desc_t __aligned(CACHELINESIZE);
  82
  83 #define IDMA_DESC_CTL_CNT       IDMA_BITS(23,0)
  84 #define IDMA_DESC_CTL_RES       IDMA_BITS(29,24)
  85 #define IDMA_DESC_CTL_TERM      IDMA_BIT(30)
  86 #define IDMA_DESC_CTL_OWN       IDMA_BIT(31)
  87
  88
  89 #define IDMA_CH0_REG_OFF                0
  90 #define IDMA_CH4_REG_OFF                0x100
  91 #define IDMA_REG(chan, base) \
  92                 ((chan < 4) ? \
  93                         ((base) + ((chan) << IDMA_WORD_SHIFT)) : \
  94                         (((base) + IDMA_CH4_REG_OFF) \
  95                                  + (((chan) - 4) << IDMA_WORD_SHIFT)))
  96
  97 #define IDMA_2X4_REG(chan, base) \
  98                 (((chan) < 4) ?  \
  99                         (base) : \
 100                         ((base) + IDMA_CH4_REG_OFF))
 101
 102 /*
 103  * IDMA Descriptor Registers
 104  */
 105 #define IDMA_CNT_REG_BASE       0x800
 106 #define IDMA_CNT_REG(chan)      IDMA_REG(chan, IDMA_CNT_REG_BASE)
 107 #define IDMA_SRC_REG_BASE       0x810
 108 #define IDMA_SRC_REG(chan)      IDMA_REG(chan, IDMA_SRC_REG_BASE)
 109 #define IDMA_DST_REG_BASE       0x820
 110 #define IDMA_DST_REG(chan)      IDMA_REG(chan, IDMA_DST_REG_BASE)
 111 #define IDMA_NXT_REG_BASE       0x830
 112 #define IDMA_NXT_REG(chan)      IDMA_REG(chan, IDMA_NXT_REG_BASE)
 113 #define IDMA_CUR_REG_BASE       0x870
 114 #define IDMA_CUR_REG(chan)      IDMA_REG(chan, IDMA_CUR_REG_BASE)
 115 #define IDMA_SRC_HIPCI_REG_BASE 0x890
 116 #define IDMA_SRC_HIPCI_REG(chan) \
 117                                 IDMA_REG(chan, IDMA_SRC_HIPCI_REG_BASE)
 118 #define IDMA_DST_HIPCI_REG_BASE 0x8a0
 119 #define IDMA_DST_HIPCI_REG(chan) \
 120                                 IDMA_REG(chan, IDMA_DST_HIPCI_REG_BASE)
 121 #define IDMA_NXT_HIPCI_REG_BASE 0x8b0
 122 #define IDMA_NXT_HIPCI_REG(chan) \
 123                                 IDMA_REG(chan, IDMA_NXT_HIPCI_REG_BASE)
 124
 125 /*
 126  * IDMA Control Registers
 127  */
 128 #define IDMA_CTLLO_REG_BASE     0x840
 129 #define IDMA_CTLLO_REG(chan)    IDMA_REG(chan, IDMA_CTLLO_REG_BASE)
 130 #define IDMA_CTLHI_REG_BASE     0x880
 131 #define IDMA_CTLHI_REG(chan)    IDMA_REG(chan, IDMA_CTLHI_REG_BASE)
 132 #define IDMA_ARB_REG_BASE       0x860
 133 #define IDMA_ARB_REG(chan)      IDMA_2X4_REG(chan, IDMA_ARB_REG_BASE)
 134 #define IDMA_XTO_REG_BASE       0x8d0
 135 #define IDMA_XTO_REG(chan)      IDMA_2X4_REG(chan, IDMA_XTO_REG_BASE)
 136 #define IDMA_CAUSE_REG_BASE     0x8c0
 137 #define IDMA_CAUSE_REG(chan)    IDMA_2X4_REG(chan, IDMA_CAUSE_REG_BASE)
 138 #define IDMA_MASK_REG_BASE      0x8c4
 139 #define IDMA_MASK_REG(chan)     IDMA_2X4_REG(chan, IDMA_MASK_REG_BASE)
 140 #define IDMA_EADDR_REG_BASE     0x8c8
 141 #define IDMA_EADDR_REG(chan)    IDMA_2X4_REG(chan, IDMA_EADDR_REG_BASE)
 142 #define IDMA_ESEL_REG_BASE      0x8cc
 143 #define IDMA_ESEL_REG(chan)     IDMA_2X4_REG(chan, IDMA_ESEL_REG_BASE)
 144
 145 /*
 146  * IDMA Channel Control Lo bits
 147  */
 148 #define IDMA_CTLLO_RESA         IDMA_BITS(2,0)
 149 #define IDMA_CTLLO_SRCHOLD      IDMA_BIT(3)
 150 #define IDMA_CTLLO_RESB         IDMA_BIT(4)
 151 #define IDMA_CTLLO_DSTHOLD      IDMA_BIT(5)
 152 #define IDMA_CTLLO_BURSTLIM     IDMA_BITS(8,6)
 153 #define IDMA_CTLLO_BURST16      IDMA_BIT(6)
 154 #define IDMA_CTLLO_BURST32      IDMA_BITS(7,6)
 155 #define IDMA_CTLLO_BURST64      IDMA_BITS(8,6)
 156 #define IDMA_CTLLO_NOCHAIN      IDMA_BIT(9)
 157 #define IDMA_CTLLO_INTR         IDMA_BIT(10)
 158 #define IDMA_CTLLO_BLKMODE      IDMA_BIT(11)
 159 #define IDMA_CTLLO_ENB          IDMA_BIT(12)
 160 #define IDMA_CTLLO_FETCHND      IDMA_BIT(13)
 161 #define IDMA_CTLLO_ACTIVE       IDMA_BIT(14)
 162 #define IDMA_CTLLO_REQDIR       IDMA_BIT(15)
 163 #define IDMA_CTLLO_REQMODE      IDMA_BIT(16)
 164 #define IDMA_CTLLO_CDEN         IDMA_BIT(17)
 165 #define IDMA_CTLLO_EOTEN        IDMA_BIT(18)
 166 #define IDMA_CTLLO_EOTMODE      IDMA_BIT(19)
 167 #define IDMA_CTLLO_ABORT        IDMA_BIT(20)
 168 #define IDMA_CTLLO_SADDROVR     IDMA_BITS(22,21)
 169 #define IDMA_CTLLO_DADDROVR     IDMA_BITS(24,23)
 170 #define IDMA_CTLLO_NADDROVR     IDMA_BITS(26,25)
 171 #define IDMA_CTLLO_ACKMODE      IDMA_BIT(27)
 172 #define IDMA_CTLLO_TREQ         IDMA_BIT(28)
 173 #define IDMA_CTLLO_ACKDIR       IDMA_BITS(30,29)
 174 #define IDMA_CTLLO_DESCMODE     IDMA_BIT(31)
 175 #define IDMA_CTLLO_RES \
 176                 (IDMA_CTLHI_RESA|IDMA_CHN_CTLHI_RESB)
 177
 178 #define IDMA_CTLL0_BURSTCODE(sz) (((sz) == 64) ? IDMA_CTLLO_BURST64 \
 179                                : (((sz) == 32) ? IDMA_CTLLO_BURST32 \
 180                                : (((sz) == 16) ? IDMA_CTLLO_BURST16 \
 181                                : ~0)))
 182
 183 /*
 184  * IDMA Channel Control Hi bits
 185  */
 186 #define IDMA_CTLHI_RESA                 IDMA_BITS(3,0)
 187 #define IDMA_CTLHI_SRCPCISWAP           IDMA_BITS(5,4)
 188 #define IDMA_CTLHI_SRCPCISWAP_NONE      IDMA_BIT(4)
 189 #define IDMA_CTLHI_SRCSNOOP             IDMA_BIT(6)
 190 #define IDMA_CTLHI_SRCPCI64             IDMA_BIT(7)
 191 #define IDMA_CTLHI_RESB                 IDMA_BITS(11,8)
 192 #define IDMA_CTLHI_DSTPCISWAP           IDMA_BITS(13,12)
 193 #define IDMA_CTLHI_DSTPCISWAP_NONE      IDMA_BIT(12)
 194 #define IDMA_CTLHI_DSTSNOOP             IDMA_BIT(14)
 195 #define IDMA_CTLHI_DSTPCI64             IDMA_BIT(15)
 196 #define IDMA_CTLHI_RESC                 IDMA_BITS(19,16)
 197 #define IDMA_CTLHI_NXTPCISWAP           IDMA_BITS(21,20)
 198 #define IDMA_CTLHI_NXTPCISWAP_NONE      IDMA_BIT(20)
 199 #define IDMA_CTLHI_NXTSNOOP             IDMA_BIT(22)
 200 #define IDMA_CTLHI_NXTPCI64             IDMA_BIT(23)
 201 #define IDMA_CTLHI_RESD                 IDMA_BITS(31,24)
 202 #define IDMA_CTLHI_RES \
 203                 (IDMA_CTLHI_RESA|IDMA_CHN_CTLHI_RESB \
 204                 |IDMA_CTLHI_RESC|IDMA_CHN_CTLHI_RESD)
 205
 206
 207 /*
 208  * IDMA Channel Arbiter Control bits
 209  */
 210 #define IDMA_ARB_ARB_SHIFT      2
 211 #define IDMA_ARB_ARB_MASK(arb) \
 212                 (BITS(1,0) << ((arb) << IDMA_ARB_ARB_SHIFT))
 213
 214
 215 /*
 216  * common IDMA Interrupt Register bits
 217  */
 218 #define IDMA_INTR_COMP          IDMA_BIT(0)     /* completion */
 219 #define IDMA_INTR_MISS          IDMA_BIT(1)     /* failed addr decode */
 220 #define IDMA_INTR_ACCESS        IDMA_BIT(2)     /* access violation */
 221 #define IDMA_INTR_WPROT         IDMA_BIT(3)     /* write protect */
 222 #define IDMA_INTR_OWN           IDMA_BIT(4)     /* desc owner violation */
 223 #define IDMA_INTR_EOT           IDMA_BIT(5)     /* end of xfer */
 224 #define IDMA_INTR_RESX          IDMA_BITS(7,6)
 225
 226 #define IDMA_INTR_SHIFT 8
 227 #define IDMA_MASK_BITS  IDMA_BITS(7,0)
 228 #define IDMA_INTR_BITS  IDMA_BITS(5,0)
 229 #define IDMA_INTR_ERRS  IDMA_BITS(5,1)
 230 #define IDMA_INTR_ALL_ERRS      (IDMA_INTR_ERRS \
 231                                 |(IDMA_INTR_ERRS <<  IDMA_INTR_SHIFT) \
 232                                 |(IDMA_INTR_ERRS << (IDMA_INTR_SHIFT*2)) \
 233                                 |(IDMA_INTR_ERRS << (IDMA_INTR_SHIFT*3)))
 234
 235 /*
 236  * IDMA Interrupt Cause Register bits
 237  */
 238 #define IDMA_CAUSE_RES  ( IDMA_INTR_RESX \
 239                         |(IDMA_INTR_RESX << IDMA_INTR_SHIFT) \
 240                         |(IDMA_INTR_RESX << (IDMA_INTR_SHIFT * 2)) \
 241                         |(IDMA_INTR_RESX << (IDMA_INTR_SHIFT * 3)))
 242
 243 /*
 244  * IDMA Interrupt Mask Register bits
 245  */
 246 #define IDMA_MASK_SHIFT(chan) \
 247                 (IDMA_INTR_SHIFT * ((chan < 4) ? chan : (chan - 4)))
 248 #define IDMA_MASK(chan, mask) \
 249                 (((mask) & IDMA_MASK_BITS) << IDMA_MASK_SHIFT(chan))
 250
 251
 252 #define IDMA_MASK_RES   (IDMA_MASK_RESX(0) \
 253                         |IDMA_MASK_RESX(1) \
 254                         |IDMA_MASK_RESX(2) \
 255                         |IDMA_MASK_RESX(3))
 256
 257 /*
 258  * IDMA Error Select Register bits
 259  */
 260 #define IDMA_ESEL_MASK  IDMA_BITS(4,0)
 261 #define IDMA_ESEL_RES   IDMA_BITS(31,5)
 262
 263
 264 /*
 265  * IDMA Debug Registers
 266  */
 267 #define IDMA_DBG_XADDR_REG_BASE 0x8e0
 268 #define IDMA_DBG_XADDR(xno)     IDMA_2X4_REG(xno, IDMA_DBG_XADDR_REG_BASE)
 269 #define IDMA_DBG_XCMD_REG_BASE  0x8e4
 270 #define IDMA_DBG_XCMD(xno)      IDMA_2X4_REG(xno, IDMA_DBG_XCMD_REG_BASE)
 271 #define IDMA_DBG_WDATLO_REG_BASE        0x8e8
 272 #define IDMA_DBG_WDATLO(xno)    IDMA_2X4_REG(xno, IDMA_DBG_WDATLO_REG_BASE)
 273 #define IDMA_DBG_WDATHI_REG_BASE        0x8ec
 274 #define IDMA_DBG_WDATHI(xno)    IDMA_2X4_REG(xno, IDMA_DBG_WDATHI_REG_BASE)
 275 #define IDMA_DBG_RDATLO_REG_BASE        0x8f0
 276 #define IDMA_DBG_RDATLO(xno)    IDMA_2X4_REG(xno, IDMA_DBG_RDATLO_REG_BASE)
 277 #define IDMA_DBG_RDATHI_REG_BASE        0x8f4
 278 #define IDMA_DBG_RDATHI(xno)    IDMA_2X4_REG(xno, IDMA_DBG_RDATHI_REG_BASE)
 279 #define IDMA_DBG_RID_REG_BASE   0x8fc
 280 #define IDMA_DBG_RID(xno)       IDMA_2X4_REG(xno, IDMA_DBG_RID_REG_BASE)
 281
 282
 283 #endif  /* _IDMAREG_H */