sys/dev/marvell/gtpci.c

   1 /*      $NetBSD: gtpci.c,v 1.20 2009/05/12 12:18:45 cegger Exp $        */
   2
   3 /*
   4  * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed for the NetBSD Project by
  18  *      Allegro Networks, Inc., and Wasabi Systems, Inc.
  19  * 4. The name of Allegro Networks, Inc. may not be used to endorse
  20  *    or promote products derived from this software without specific prior
  21  *    written permission.
  22  * 5. The name of Wasabi Systems, Inc. may not be used to endorse
  23  *    or promote products derived from this software without specific prior
  24  *    written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
  27  * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
  29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30  * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 #include <sys/cdefs.h>
  41 __KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.20 2009/05/12 12:18:45 cegger Exp $");
  42
  43 #include "opt_marvell.h"
  44 #include <sys/param.h>
  45 #include <sys/device.h>
  46 #include <sys/extent.h>
  47 #include <sys/malloc.h>
  48 #include <lib/libkern/libkern.h>
  49
  50 #define _BUS_SPACE_PRIVATE
  51 #define _BUS_DMA_PRIVATE
  52 #include <sys/bus.h>
  53 #include <sys/intr.h>
  54
  55 #include <dev/pci/pcireg.h>
  56 #include <dev/pci/pcivar.h>
  57 #include <dev/pci/pciconf.h>
  58 #include <dev/marvell/gtreg.h>
  59 #include <dev/marvell/gtvar.h>
  60 #include <dev/marvell/gtintrreg.h>
  61 #include <dev/marvell/gtpcireg.h>
  62 #include <dev/marvell/gtpcivar.h>
  63
  64 static int      gtpci_error_intr(void *);
  65
  66 static void     gtpci_bus_init(struct gtpci_chipset *);
  67
  68 static void     gtpci_bus_attach_hook(device_t, device_t,
  69                     struct pcibus_attach_args *);
  70 static int      gtpci_bus_maxdevs(pci_chipset_tag_t, int);
  71
  72 static const char *
  73                 gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
  74 static const struct evcnt *
  75                 gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
  76 static void     *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
  77                     int, int (*)(void *), void *);
  78 static void     gtpci_intr_disestablish(pci_chipset_tag_t, void *);
  79
  80 #ifdef DEBUG
  81 int gtpci_debug = 0;
  82 #endif
  83
  84 struct gtpci_softc {
  85         struct device gtpci_dev;
  86         struct gtpci_chipset gtpci_gtpc;
  87 };
  88
  89 static int gtpci_cfprint(void *, const char *);
  90 static int gtpci_match(device_t, cfdata_t, void *);
  91 static void gtpci_attach(device_t, device_t, void *);
  92
  93 CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc),
  94     gtpci_match, gtpci_attach, NULL, NULL);
  95
  96 extern struct cfdriver gtpci_cd;
  97
  98 const struct pci_chipset_functions gtpci_functions = {
  99         gtpci_bus_attach_hook,
 100         gtpci_bus_maxdevs,
 101         gtpci_md_bus_devorder,
 102
 103         gtpci_make_tag,
 104         gtpci_decompose_tag,
 105
 106         gtpci_conf_read,
 107         gtpci_conf_write,
 108         gtpci_md_conf_hook,
 109         gtpci_md_conf_interrupt,
 110
 111         gtpci_md_intr_map,
 112         gtpci_intr_string,
 113         gtpci_intr_evcnt,
 114         gtpci_intr_establish,
 115         gtpci_intr_disestablish
 116 };
 117
 118 static const int pci_irqs[2][3] = {
 119     { IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 },
 120     { IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 },
 121 };
 122
 123 static const struct pci_init {
 124         int bar_regno;
 125         u_int32_t bar_enable;
 126         bus_addr_t low_decode;
 127         bus_addr_t high_decode;
 128         bus_addr_t barsize;
 129         bus_addr_t accctl_high;
 130         bus_addr_t accctl_low;
 131         bus_addr_t accctl_top;
 132 } pci_initinfo[2][4] = {
 133         {
 134                 {
 135                         0x10,                   PCI_BARE_SCS0En,
 136                         GT_SCS0_Low_Decode,     GT_SCS0_High_Decode,
 137                         PCI_SCS0_BAR_SIZE(0),
 138                         PCI_ACCESS_CONTROL_BASE_HIGH(0, 0),
 139                         PCI_ACCESS_CONTROL_BASE_LOW(0, 0),
 140                         PCI_ACCESS_CONTROL_TOP(0, 0),
 141                 }, {
 142                         0x14,                   PCI_BARE_SCS1En,
 143                         GT_SCS1_Low_Decode,     GT_SCS1_High_Decode,
 144                         PCI_SCS1_BAR_SIZE(0),
 145                         PCI_ACCESS_CONTROL_BASE_HIGH(0, 1),
 146                         PCI_ACCESS_CONTROL_BASE_LOW(0, 1),
 147                         PCI_ACCESS_CONTROL_TOP(0, 1),
 148                 }, {
 149                         0x18,                   PCI_BARE_SCS2En,
 150                         GT_SCS2_Low_Decode,     GT_SCS2_High_Decode,
 151                         PCI_SCS2_BAR_SIZE(0),
 152                         PCI_ACCESS_CONTROL_BASE_HIGH(0, 2),
 153                         PCI_ACCESS_CONTROL_BASE_LOW(0, 2),
 154                         PCI_ACCESS_CONTROL_TOP(0, 2),
 155                 }, {
 156                         0x1c,                   PCI_BARE_SCS3En,
 157                         GT_SCS3_Low_Decode,     GT_SCS3_High_Decode,
 158                         PCI_SCS3_BAR_SIZE(0),
 159                         PCI_ACCESS_CONTROL_BASE_HIGH(0, 3),
 160                         PCI_ACCESS_CONTROL_BASE_LOW(0, 3),
 161                         PCI_ACCESS_CONTROL_TOP(0, 3),
 162                 },
 163         }, {
 164                 {
 165                         0x10,                   PCI_BARE_SCS0En,
 166                         GT_SCS0_Low_Decode,     GT_SCS0_High_Decode,
 167                         PCI_SCS0_BAR_SIZE(1),
 168                         PCI_ACCESS_CONTROL_BASE_HIGH(1, 0),
 169                         PCI_ACCESS_CONTROL_BASE_LOW(1, 0),
 170                         PCI_ACCESS_CONTROL_TOP(1, 0),
 171                 }, {
 172                         0x14,                   PCI_BARE_SCS1En,
 173                         GT_SCS1_Low_Decode,     GT_SCS1_High_Decode,
 174                         PCI_SCS1_BAR_SIZE(1),
 175                         PCI_ACCESS_CONTROL_BASE_HIGH(1, 1),
 176                         PCI_ACCESS_CONTROL_BASE_LOW(1, 1),
 177                         PCI_ACCESS_CONTROL_TOP(1, 1),
 178                 }, {
 179                         0x18,                   PCI_BARE_SCS2En,
 180                         GT_SCS2_Low_Decode,     GT_SCS2_High_Decode,
 181                         PCI_SCS2_BAR_SIZE(1),
 182                         PCI_ACCESS_CONTROL_BASE_HIGH(1, 2),
 183                         PCI_ACCESS_CONTROL_BASE_LOW(1, 2),
 184                         PCI_ACCESS_CONTROL_TOP(1, 2),
 185                 }, {
 186                         0x1c,                   PCI_BARE_SCS3En,
 187                         GT_SCS3_Low_Decode,     GT_SCS3_High_Decode,
 188                         PCI_SCS3_BAR_SIZE(1),
 189                         PCI_ACCESS_CONTROL_BASE_HIGH(1, 3),
 190                         PCI_ACCESS_CONTROL_BASE_LOW(1, 3),
 191                         PCI_ACCESS_CONTROL_TOP(1, 3),
 192                 },
 193         }
 194 };
 195
 196 int
 197 gtpci_match(device_t parent, cfdata_t self, void *aux)
 198 {
 199         struct gt_softc * const gt = device_private(parent);
 200         struct gt_attach_args * const ga = aux;
 201
 202         return GT_PCIOK(gt, ga, &gtpci_cd);
 203 }
 204
 205 int
 206 gtpci_cfprint(void *aux, const char *pnp)
 207 {
 208         struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux;
 209
 210         if (pnp)
 211                 aprint_normal("pci at %s", pnp);
 212
 213         aprint_normal(" bus %d", pba->pba_bus);
 214
 215         return (UNCONF);
 216 }
 217
 218 void
 219 gtpci_attach(device_t parent, device_t self, void *aux)
 220 {
 221         struct pcibus_attach_args pba;
 222         struct gt_attach_args * const ga = aux;
 223         struct gt_softc * const gt = device_private(parent);
 224         struct gtpci_softc * const gtp = device_private(self);
 225         struct gtpci_chipset * const gtpc = &gtp->gtpci_gtpc;
 226         struct pci_chipset * const pc = &gtpc->gtpc_pc;
 227         const int busno = ga->ga_unit;
 228         uint32_t data;
 229
 230         GT_PCIFOUND(gt, ga);
 231
 232         pc->pc_funcs = &gtpci_functions;
 233         pc->pc_parent = self;
 234
 235         gtpc->gtpc_busno = busno;
 236         gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno);
 237         gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno);
 238         gtpc->gtpc_syncreg = PCI_SYNC_REG(busno);
 239         gtpc->gtpc_gt_memt = ga->ga_memt;
 240         gtpc->gtpc_gt_memh = ga->ga_memh;
 241
 242         /*
 243          * Let's find out where we are located.
 244          */
 245         data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno));
 246         gtpc->gtpc_self = gtpci_make_tag(&gtpc->gtpc_pc,
 247                 PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0);
 248
 249
 250         switch (busno) {
 251         case 0:
 252                 gtpc->gtpc_io_bs = gt->gt_pci0_iot;
 253                 gtpc->gtpc_mem_bs = gt->gt_pci0_memt;
 254                 gtpc->gtpc_host = gt->gt_pci0_host;
 255                 break;
 256         case 1:
 257                 gtpc->gtpc_io_bs = gt->gt_pci1_iot;
 258                 gtpc->gtpc_mem_bs = gt->gt_pci1_memt;
 259                 gtpc->gtpc_host = gt->gt_pci1_host;
 260                 break;
 261         default:
 262                 break;
 263         }
 264
 265         /*
 266          * If no bus_spaces exist, then it's been disabled.
 267          */
 268         if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) {
 269                 aprint_normal(": disabled\n");
 270                 return;
 271         }
 272
 273         aprint_normal("\n");
 274
 275         /*
 276          * clear any pre-existing error interrupt(s)
 277          * clear latched pci error registers
 278          * establish ISRs for PCI errors
 279          * enable PCI error interrupts
 280          */
 281         gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0);
 282         gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0);
 283         (void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
 284         (void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
 285         (void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
 286         (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
 287         (void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
 288         if (gtpc->gtpc_host) {
 289                 intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL,
 290                     IPL_VM, gtpci_error_intr, pc);
 291                 intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL,
 292                     IPL_VM, gtpci_error_intr, pc);
 293                 intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL,
 294                     IPL_VM, gtpci_error_intr, pc);
 295                 aprint_normal_dev(pc->pc_parent, "%s%d error interrupts at irqs %s, %s, %s\n",
 296                     "pci", busno,
 297                     intr_string(pci_irqs[gtpc->gtpc_busno][0]),
 298                     intr_string(pci_irqs[gtpc->gtpc_busno][1]),
 299                     intr_string(pci_irqs[gtpc->gtpc_busno][2]));
 300                 gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno),
 301                     PCI_SERRMSK_ALL_ERRS);
 302         }
 303
 304         /*
 305          * Fill in the pci_bus_attach_args
 306          */
 307         pba.pba_pc = pc;
 308         pba.pba_bus = 0;
 309         pba.pba_iot = gtpc->gtpc_io_bs;
 310         pba.pba_memt = gtpc->gtpc_mem_bs;
 311         pba.pba_dmat = gt->gt_dmat;
 312         pba.pba_flags = 0;
 313         if (pba.pba_iot != NULL)
 314                 pba.pba_flags |= PCI_FLAGS_IO_ENABLED;
 315         if (pba.pba_memt != NULL)
 316                 pba.pba_flags |= PCI_FLAGS_MEM_ENABLED;
 317
 318         data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
 319         if (data & PCI_CMD_MRdMul)
 320                 pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
 321         if (data & PCI_CMD_MRdLine)
 322                 pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
 323         pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
 324
 325         gt_watchdog_service();
 326         /*
 327          * Configure the pci bus.
 328          */
 329         config_found_ia(self, "pcibus", &pba, gtpci_cfprint);
 330
 331         gt_watchdog_service();
 332
 333 }
 334
 335 void
 336 gtpci_bus_init(struct gtpci_chipset *gtpc)
 337 {
 338         const struct pci_init *pi;
 339         uint32_t data, datal, datah;
 340         pcireg_t pcidata;
 341         int i;
 342
 343         /*
 344          * disable all BARs to start.
 345          */
 346         gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
 347             0xffffffff);
 348
 349 #ifndef GT_PCI0_EXT_ARBITER
 350 #define GT_PCI0_EXT_ARBITER 0
 351 #endif
 352 #ifndef GT_PCI1_EXT_ARBITER
 353 #define GT_PCI1_EXT_ARBITER 0
 354 #endif
 355
 356         if (gtpc->gtpc_host &&
 357             ((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) ||
 358              (!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) {
 359                 /*
 360                  * Enable internal arbiter
 361                  */
 362                 data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
 363                 data |= PCI_ARBCTL_EN;
 364                 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
 365         } else {
 366                 /*
 367                  * Make sure the internal arbiter is disabled
 368                  */
 369                 gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0);
 370         }
 371
 372         /*
 373          * Make the GT reflects reality.
 374          * We always enable internal memory.
 375          */
 376         if (gtpc->gtpc_host) {
 377                 pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
 378                     0x20) & 0xfff;
 379                 gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20,
 380                     GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) |
 381                     pcidata);
 382         }
 383         data = PCI_BARE_IntMemEn;
 384
 385         for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++)
 386                 gtpci_write(gtpc, pi->barsize, 0);
 387
 388         if (gtpc->gtpc_host) {
 389                 /*
 390                  * Enable bus master access (needed for config access).
 391                  */
 392                 pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
 393                     PCI_COMMAND_STATUS_REG);
 394                 pcidata |= PCI_COMMAND_MASTER_ENABLE;
 395                 gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
 396                     PCI_COMMAND_STATUS_REG, pcidata);
 397         }
 398
 399         /*
 400          * Map each SCS BAR to correspond to each SDRAM decode register.
 401          */
 402         for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) {
 403                 datal = gtpci_read(gtpc, pi->low_decode);
 404                 datah = gtpci_read(gtpc, pi->high_decode);
 405                 pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
 406                     pi->bar_regno);
 407                 gtpci_write(gtpc, pi->accctl_high, 0);
 408                 if (datal < datah) {
 409                         datal &= 0xfff;
 410                         pcidata &= 0xfff;
 411                         pcidata |= datal << 20;
 412                         data |= pi->bar_enable;
 413                         datah -= datal;
 414                         datal |= PCI_ACCCTLBASEL_PrefetchEn|
 415                             PCI_ACCCTLBASEL_RdPrefetch|
 416                             PCI_ACCCTLBASEL_RdLinePrefetch|
 417                             PCI_ACCCTLBASEL_RdMulPrefetch|
 418                             PCI_ACCCTLBASEL_WBurst_8_QW|
 419                             PCI_ACCCTLBASEL_PCISwap_NoSwap;
 420                         gtpci_write(gtpc, pi->accctl_low, datal);
 421                 } else {
 422                         pcidata &= 0xfff;
 423                         datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
 424                         datah = 0;
 425                 }
 426                 gtpci_write(gtpc, pi->barsize,
 427                     datah ? ((datah << 20) | 0xff000) : 0);
 428                 if (gtpc->gtpc_host) {
 429                         gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
 430                             pi->bar_regno, pcidata);
 431                 }
 432                 gtpci_write(gtpc, pi->accctl_low, datal);
 433                 gtpci_write(gtpc, pi->accctl_top, datah);
 434         }
 435
 436         /*
 437          * Now re-enable those BARs that are real.
 438          */
 439         gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
 440             ~data);
 441
 442         if (gtpc->gtpc_host) {
 443                 /*
 444                  * Enable I/O and memory (bus master is already enabled) access.
 445                  */
 446                 pcidata = gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self,
 447                     PCI_COMMAND_STATUS_REG);
 448                 pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
 449                 gtpci_conf_write(&gtpc->gtpc_pc, gtpc->gtpc_self,
 450                     PCI_COMMAND_STATUS_REG, pcidata);
 451         }
 452 }
 453
 454 void
 455 gtpci_bus_attach_hook(device_t parent, device_t self,
 456         struct pcibus_attach_args *pba)
 457 {
 458         struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc;
 459         uint32_t data;
 460 #if defined(DEBUG)
 461         pcitag_t tag;
 462         int bus, dev;
 463         int i;
 464 #endif
 465
 466         if (gtpc->gtpc_pc.pc_parent != parent)
 467                 return;
 468
 469         data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
 470         aprint_normal(": id %d%s%s%s%s%s%s%s%s",
 471                 PCI_MODE_PciID_GET(data),
 472                 (data & PCI_MODE_Pci64) ? ", 64bit" : "",
 473                 (data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "",
 474                 (data & PCI_MODE_VPD) ? ", VPD" : "",
 475                 (data & PCI_MODE_MSI) ? ", MSI" : "",
 476                 (data & PCI_MODE_PMG) ? ", PMG" : "",
 477                 (data & PCI_MODE_HotSwap) ? ", HotSwap" : "",
 478                 (data & PCI_MODE_BIST) ? ", BIST" : "",
 479                 (data & PCI_MODE_PRst) ? "" : ", PRst");
 480
 481 #if 0
 482         while ((data & PCI_MODE_PRst) == 0) {
 483                 DELAY(10);
 484                 data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
 485                 aprint_normal(".");
 486         }
 487 #endif
 488
 489         gtpci_bus_init(gtpc);
 490         gtpci_bus_configure(gtpc);
 491
 492         data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
 493         if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) {
 494                 aprint_normal("\n");
 495                 aprint_normal_dev(self, "");
 496                 if (data & PCI_CMD_MSwapEn) {
 497                         switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) {
 498                         case PCI_CMD_MWordSwap:
 499                                 aprint_normal(" mswap=w"); break;
 500                         case PCI_CMD_MByteSwap:
 501                                 aprint_normal(" mswap=b"); break;
 502                         case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap:
 503                                 aprint_normal(" mswap=b+w"); break;
 504                         case 0:
 505                                 aprint_normal(" mswap=none"); break;
 506                         }
 507                 }
 508
 509                 if (data & PCI_CMD_SSwapEn) {
 510                         switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) {
 511                         case PCI_CMD_SWordSwap:
 512                                 aprint_normal(" sswap=w"); break;
 513                         case PCI_CMD_SByteSwap:
 514                                 aprint_normal(" sswap=b"); break;
 515                         case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap:
 516                                 aprint_normal(" sswap=b+w"); break;
 517                         case 0:
 518                                 aprint_normal(" sswap=none"); break;
 519                         }
 520                 }
 521         }
 522
 523 #if defined(DEBUG)
 524         if (gtpci_debug == 0)
 525                 return;
 526
 527         data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno));
 528         aprint_normal("\n");
 529         aprint_normal_dev(self, "BARs enabled: %#x", data);
 530
 531         aprint_normal("\n");
 532         aprint_normal_dev(self, "0:0:0\n");
 533         aprint_normal("   %sSCS0=%#010x",
 534                 (data & 1) ? "-" : "+",
 535                 gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x10));
 536         aprint_normal("/%#010x", gtpci_read(gtpc,
 537                 PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno)));
 538         aprint_normal("  remap %#010x\n",
 539                 gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 540
 541         aprint_normal("   %sSCS1=%#010x",
 542                 (data & 2) ? "-" : "+",
 543                 gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x14));
 544         aprint_normal("/%#010x",
 545                 gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno)));
 546         aprint_normal("  remap %#010x\n",
 547                 gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 548
 549         aprint_normal("   %sSCS2=%#010x",
 550                 (data & 4) ? "-" : "+",
 551                 gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x18));
 552         aprint_normal("/%#010x",
 553                 gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno)));
 554         aprint_normal("  remap %#010x\n",
 555                 gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 556
 557         aprint_normal("   %sSCS3=%#010x",
 558                 (data & 8) ? "-" : "+",
 559                 gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x1c));
 560         aprint_normal("/%#010x",
 561                 gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno)));
 562         aprint_normal("  remap %#010x\n",
 563                 gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 564
 565         aprint_normal("   %sIMem=%#010x",
 566                 (data & PCI_BARE_IntMemEn) ? "-" : "+",
 567                 gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x20));
 568         aprint_normal("\n");
 569         aprint_normal("    %sIIO=%#010x",
 570                 (data & PCI_BARE_IntIOEn) ? "-" : "+",
 571                 gtpci_conf_read(&gtpc->gtpc_pc, gtpc->gtpc_self, 0x24));
 572         aprint_normal("\n");
 573
 574         gtpci_decompose_tag(&gtpc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL);
 575         tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, dev, 1);
 576         aprint_normal("    %sCS0=%#010x",
 577                 (data & PCI_BARE_CS0En) ? "-" : "+",
 578                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
 579         aprint_normal("/%#010x",
 580                 gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno)));
 581         aprint_normal("  remap %#010x\n",
 582                 gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 583
 584         aprint_normal("    %sCS1=%#010x",
 585                 (data & PCI_BARE_CS1En) ? "-" : "+",
 586                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
 587         aprint_normal("/%#010x",
 588                 gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno)));
 589         aprint_normal("  remap %#010x\n",
 590                 gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 591
 592         aprint_normal("    %sCS2=%#010x",
 593                 (data & PCI_BARE_CS2En) ? "-" : "+",
 594                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
 595         aprint_normal("/%#010x",
 596                 gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno)));
 597         aprint_normal("  remap %#010x\n",
 598                 gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 599
 600         aprint_normal("    %sCS3=%#010x",
 601                 (data & PCI_BARE_CS3En) ? "-" : "+",
 602                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
 603         aprint_normal("/%#010x",
 604                 gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno)));
 605         aprint_normal("  remap %#010x\n",
 606                 gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 607
 608         aprint_normal(" %sBootCS=%#010x",
 609                 (data & PCI_BARE_BootCSEn) ? "-" : "+",
 610                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x20));
 611         aprint_normal("/%#010x",
 612                 gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno)));
 613         aprint_normal("  remap %#010x\n",
 614                 gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno)));
 615
 616         tag = gtpci_make_tag(&gtpc->gtpc_pc, bus, tag, 2);
 617         aprint_normal("  %sP2PM0=%#010x",
 618                 (data & PCI_BARE_P2PMem0En) ? "-" : "+",
 619                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x10));
 620         aprint_normal("/%#010x",
 621                 gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno)));
 622         aprint_normal("  remap %#010x.%#010x\n",
 623                 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
 624                 gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
 625
 626         aprint_normal("  %sP2PM1=%#010x",
 627                 (data & PCI_BARE_P2PMem1En) ? "-" : "+",
 628                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x14));
 629         aprint_normal("/%#010x",
 630                 gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno)));
 631         aprint_normal("  remap %#010x.%#010x\n",
 632                 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
 633                 gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
 634
 635         aprint_normal("  %sP2PIO=%#010x",
 636                 (data & PCI_BARE_P2PIOEn) ? "-" : "+",
 637                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x18));
 638         aprint_normal("/%#010x",
 639                 gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno)));
 640         aprint_normal("  remap %#010x\n",
 641                 gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 642
 643         aprint_normal("    %sCPU=%#010x",
 644                 (data & PCI_BARE_CPUEn) ? "-" : "+",
 645                 gtpci_conf_read(&gtpc->gtpc_pc, tag, 0x1c));
 646         aprint_normal("/%#010x",
 647                 gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno)));
 648         aprint_normal("  remap %#010x\n",
 649                 gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
 650
 651         for (i = 0; i < 8; i++) {
 652                 aprint_normal("\n");
 653                 aprint_normal_dev("Access Control %d: ", device_xname(self), i);
 654                 data = gtpci_read(gtpc,
 655                     PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i));
 656                 if (data)
 657                         aprint_normal("base=0x%08x.", data);
 658                 else
 659                         aprint_normal("base=0x");
 660                 data = gtpci_read(gtpc,
 661                         PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i));
 662                 printf("%08x cfg=0x%08x", data << 20, data & ~0xfff);
 663                 aprint_normal(" top=0x%03x00000",
 664                     gtpci_read(gtpc,
 665                         PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i)));
 666         }
 667 #endif
 668 }
 669
 670 static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings;
 671
 672 int
 673 gtpci_error_intr(void *arg)
 674 {
 675         pci_chipset_tag_t pc = arg;
 676         struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
 677         uint32_t cause, mask, errmask;
 678         u_int32_t alo, ahi, dlo, dhi, cmd;
 679         int i;
 680
 681         cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno));
 682         errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno));
 683         cause &= errmask | 0xf8000000;
 684         gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause);
 685         printf("%s: pci%d error: cause=%#x mask=%#x",
 686                 device_xname(pc->pc_parent), gtpc->gtpc_busno, cause, errmask);
 687         if ((cause & 0xf8000000) == 0) {
 688                 printf(" ?\n");
 689                 return 0;
 690         }
 691
 692         for (i = 0, mask = 1; i <= 26; i++, mask += mask)
 693                 if (mask & cause)
 694                         printf(" %s", gtpci_error_strings[i]);
 695
 696         /*
 697          * "no new data is latched until the PCI Error Low Address
 698          * register is read.  This means that PCI Error Low Address
 699          * register must be the last register read by the interrupt
 700          * handler."
 701          */
 702         dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
 703         dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
 704         cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
 705         ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
 706         alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
 707         printf("\n%s: pci%d error: %s cmd=%#x",
 708                 device_xname(pc->pc_parent), gtpc->gtpc_busno,
 709                 gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd);
 710         if (dhi == 0)
 711                 printf(" data=%08x", dlo);
 712         else
 713                 printf(" data=%08x.%08x", dhi, dlo);
 714         if (ahi == 0)
 715                 printf(" address=%08x\n", alo);
 716         else
 717                 printf(" address=%08x.%08x\n", ahi, alo);
 718
 719 #if defined(DEBUG) && defined(DDB)
 720         if (gtpci_debug > 1)
 721                 Debugger();
 722 #endif
 723         return 1;
 724 }
 725
 726
 727 #if 0
 728 void
 729 gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
 730         struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
 731 {
 732         /* See how I/O space is configured.  Read the base and top
 733          * registers.
 734          */
 735         paddr_t pbasel, pbaseh;
 736         uint32_t datal, datah;
 737
 738         datal = gtpci_read(gtpc, lo);
 739         datah = gtpci_read(gtpc, hi);
 740         pbasel = GT_LowAddr_GET(datal);
 741         pbaseh = GT_HighAddr_GET(datah);
 742         /*
 743          * If the start is greater than the end, ignore the region.
 744          */
 745         if (pbaseh < pbasel)
 746                 return;
 747         if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
 748             && (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
 749                 bs->bs_regions[bs->bs_nregion].br_vbase =
 750                         gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
 751         }
 752         bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
 753         if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
 754                 bs->bs_regions[bs->bs_nregion].br_start = 0;
 755                 bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
 756         } else {
 757                 bs->bs_regions[bs->bs_nregion].br_start = pbasel;
 758                 bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
 759         }
 760         bs->bs_nregion++;
 761 }
 762 #endif
 763
 764 /*
 765  * Internal functions.
 766  */
 767 int
 768 gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
 769 {
 770         return 32;
 771 }
 772
 773 pcitag_t
 774 gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno)
 775 {
 776         return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0);
 777 }
 778
 779 void
 780 gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
 781                     int *bp, int *dp, int *fp)
 782 {
 783         if (bp != NULL)
 784                 *bp = PCI_CFG_GET_BUSNO(tag);
 785         if (dp != NULL)
 786                 *dp = PCI_CFG_GET_DEVNO(tag);
 787         if (fp != NULL)
 788                 *fp = PCI_CFG_GET_FUNCNO(tag);
 789 }
 790
 791 pcireg_t
 792 gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno)
 793 {
 794         struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
 795 #ifdef DIAGNOSTIC
 796         if ((regno & 3) || (regno & ~0xff))
 797                 panic("gtpci_conf_read: bad regno %#x\n", regno);
 798 #endif
 799         gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
 800         return gtpci_read(gtpc, gtpc->gtpc_cfgdata);
 801 }
 802
 803 void
 804 gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data)
 805 {
 806         struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
 807 #ifdef DIAGNOSTIC
 808         if ((regno & 3) || (regno & ~0xff))
 809                 panic("gtpci_conf_write: bad regno %#x\n", regno);
 810 #endif
 811         gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
 812         gtpci_write(gtpc, gtpc->gtpc_cfgdata, data);
 813 }
 814
 815 const char *
 816 gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih)
 817 {
 818         return intr_string(pih);
 819 }
 820
 821 const struct evcnt *
 822 gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih)
 823 {
 824         return intr_evcnt(pih);
 825 }
 826
 827 void *
 828 gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih,
 829     int ipl, int (*handler)(void *), void *arg)
 830 {
 831         return intr_establish(pih, IST_LEVEL, ipl, handler, arg);
 832 }
 833
 834 void
 835 gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
 836 {
 837         intr_disestablish(cookie);
 838 }