?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Sync usage with man page.
[netbsd-mini2440.git] / sys / dev / marvell / gtreg.h
blob8625b2735b3cca746ad81e842c602a2bfc0ded42
1 /* $NetBSD: gtreg.h,v 1.1.2.1 2005/03/04 16:43:40 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Allegro Networks, Inc., and Wasabi Systems, Inc.
19 * 4. The name of Allegro Networks, Inc. may not be used to endorse
20 * or promote products derived from this software without specific prior
21 * written permission.
22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
24 * written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 #ifndef _DISCOVERY_DEV_GTREG_H_
41 #define _DISCOVERY_DEV_GTREG_H_
42
43 #define GT__BIT(bit) (1U << (bit))
44 #define GT__MASK(bit) (GT__BIT(bit) - 1)
45 #define GT__EXT(data, bit, len) (((data) >> (bit)) & GT__MASK(len))
46 #define GT__CLR(data, bit, len) ((data) &= ~(GT__MASK(len) << (bit)))
47 #define GT__INS(new, bit) ((new) << (bit))
48
49
50 /*
51 * Table 30: CPU Address Decode Register Map
52 */
53 #define GT_SCS0_Low_Decode 0x0008
54 #define GT_SCS0_High_Decode 0x0010
55 #define GT_SCS1_Low_Decode 0x0208
56 #define GT_SCS1_High_Decode 0x0210
57 #define GT_SCS2_Low_Decode 0x0018
58 #define GT_SCS2_High_Decode 0x0020
59 #define GT_SCS3_Low_Decode 0x0218
60 #define GT_SCS3_High_Decode 0x0220
61 #define GT_CS0_Low_Decode 0x0028
62 #define GT_CS0_High_Decode 0x0030
63 #define GT_CS1_Low_Decode 0x0228
64 #define GT_CS1_High_Decode 0x0230
65 #define GT_CS2_Low_Decode 0x0248
66 #define GT_CS2_High_Decode 0x0250
67 #define GT_CS3_Low_Decode 0x0038
68 #define GT_CS3_High_Decode 0x0040
69 #define GT_BootCS_Low_Decode 0x0238
70 #define GT_BootCS_High_Decode 0x0240
71 #define GT_PCI0_IO_Low_Decode 0x0048
72 #define GT_PCI0_IO_High_Decode 0x0050
73 #define GT_PCI0_Mem0_Low_Decode 0x0058
74 #define GT_PCI0_Mem0_High_Decode 0x0060
75 #define GT_PCI0_Mem1_Low_Decode 0x0080
76 #define GT_PCI0_Mem1_High_Decode 0x0088
77 #define GT_PCI0_Mem2_Low_Decode 0x0258
78 #define GT_PCI0_Mem2_High_Decode 0x0260
79 #define GT_PCI0_Mem3_Low_Decode 0x0280
80 #define GT_PCI0_Mem3_High_Decode 0x0288
81 #define GT_PCI1_IO_Low_Decode 0x0090
82 #define GT_PCI1_IO_High_Decode 0x0098
83 #define GT_PCI1_Mem0_Low_Decode 0x00a0
84 #define GT_PCI1_Mem0_High_Decode 0x00a8
85 #define GT_PCI1_Mem1_Low_Decode 0x00b0
86 #define GT_PCI1_Mem1_High_Decode 0x00b8
87 #define GT_PCI1_Mem2_Low_Decode 0x02a0
88 #define GT_PCI1_Mem2_High_Decode 0x02a8
89 #define GT_PCI1_Mem3_Low_Decode 0x02b0
90 #define GT_PCI1_Mem3_High_Decode 0x02b8
91 #define GT_Internal_Decode 0x0068
92 #define GT_CPU0_Low_Decode 0x0290
93 #define GT_CPU0_High_Decode 0x0298
94 #define GT_CPU1_Low_Decode 0x02c0
95 #define GT_CPU1_High_Decode 0x02c8
96 #define GT_PCI0_IO_Remap 0x00f0
97 #define GT_PCI0_Mem0_Remap_Low 0x00f8
98 #define GT_PCI0_Mem0_Remap_High 0x0320
99 #define GT_PCI0_Mem1_Remap_Low 0x0100
100 #define GT_PCI0_Mem1_Remap_High 0x0328
101 #define GT_PCI0_Mem2_Remap_Low 0x02f8
102 #define GT_PCI0_Mem2_Remap_High 0x0330
103 #define GT_PCI0_Mem3_Remap_Low 0x0300
104 #define GT_PCI0_Mem3_Remap_High 0x0338
105 #define GT_PCI1_IO_Remap 0x0108
106 #define GT_PCI1_Mem0_Remap_Low 0x0110
107 #define GT_PCI1_Mem0_Remap_High 0x0340
108 #define GT_PCI1_Mem1_Remap_Low 0x0118
109 #define GT_PCI1_Mem1_Remap_High 0x0348
110 #define GT_PCI1_Mem2_Remap_Low 0x0310
111 #define GT_PCI1_Mem2_Remap_High 0x0350
112 #define GT_PCI1_Mem3_Remap_Low 0x0318
113 #define GT_PCI1_Mem3_Remap_High 0x0358
114
115
116 /*
117 * Table 31: CPU Control Register Map
118 */
119 #define GT_CPU_Cfg 0x0000
120 #define GT_CPU_Mode 0x0120
121 #define GT_CPU_Master_Ctl 0x0160
122 #define GT_CPU_If_Xbar_Ctl_Low 0x0150
123 #define GT_CPU_If_Xbar_Ctl_High 0x0158
124 #define GT_CPU_If_Xbar_Timeout 0x0168
125 #define GT_CPU_Rd_Rsp_Xbar_Ctl_Low 0x0170
126 #define GT_CPU_Rd_Rsp_Xbar_Ctl_High 0x0178
127
128 /*
129 * Table 32: CPU Sync Barrier Register Map
130 */
131 #define GT_PCI_Sync_Barrier(bus) (0x00c0 | ((bus) << 3))
132 #define GT_PCI0_Sync_Barrier 0x00c0
133 #define GT_PCI1_Sync_Barrier 0x00c8
134
135 /*
136 * Table 33: CPU Access Protection Register Map
137 */
138 #define GT_Protect_Low_0 0x0180
139 #define GT_Protect_High_0 0x0188
140 #define GT_Protect_Low_1 0x0190
141 #define GT_Protect_High_1 0x0198
142 #define GT_Protect_Low_2 0x01a0
143 #define GT_Protect_High_2 0x01a8
144 #define GT_Protect_Low_3 0x01b0
145 #define GT_Protect_High_3 0x01b8
146 #define GT_Protect_Low_4 0x01c0
147 #define GT_Protect_High_4 0x01c8
148 #define GT_Protect_Low_5 0x01d0
149 #define GT_Protect_High_5 0x01d8
150 #define GT_Protect_Low_6 0x01e0
151 #define GT_Protect_High_6 0x01e8
152 #define GT_Protect_Low_7 0x01f0
153 #define GT_Protect_High_7 0x01f8
154
155 /*
156 * Table 34: Snoop Control Register Map
157 */
158 #define GT_Snoop_Base_0 0x0380
159 #define GT_Snoop_Top_0 0x0388
160 #define GT_Snoop_Base_1 0x0390
161 #define GT_Snoop_Top_1 0x0398
162 #define GT_Snoop_Base_2 0x03a0
163 #define GT_Snoop_Top_2 0x03a8
164 #define GT_Snoop_Base_3 0x03b0
165 #define GT_Snoop_Top_3 0x03b8
166
167 /*
168 * Table 35: CPU Error Report Register Map
169 */
170 #define GT_CPU_Error_Address_Low 0x0070
171 #define GT_CPU_Error_Address_High 0x0078
172 #define GT_CPU_Error_Data_Low 0x0128
173 #define GT_CPU_Error_Data_High 0x0130
174 #define GT_CPU_Error_Parity 0x0138
175 #define GT_CPU_Error_Cause 0x0140
176 #define GT_CPU_Error_Mask 0x0148
177
178 #define GT_DecodeAddr_SET(g, r, v) \
179 do { \
180 gt_read((g), GT_Internal_Decode); \
181 gt_write((g), (r), ((v) & 0xfff00000) >> 20); \
182 while ((gt_read((g), (r)) & 0xfff) != ((v) >> 20)); \
183 } while (0)
184
185 #define GT_LowAddr_GET(v) (GT__EXT((v), 0, 12) << 20)
186 #define GT_HighAddr_GET(v) ((GT__EXT((v), 0, 12) << 20) | 0xfffff)
187
188 #define GT_MPP_Control0 0xf000
189 #define GT_MPP_Control1 0xf004
190 #define GT_MPP_Control2 0xf008
191 #define GT_MPP_Control3 0xf00c
192
193 #define GT_GPP_IO_Control 0xf100
194 #define GT_GPP_Level_Control 0xf110
195 #define GT_GPP_Value 0xf104
196 #define GT_GPP_Interrupt_Cause 0xf108
197 #define GT_GPP_Interrupt_Mask 0xf10c
198 /*
199 * Table 36: SCS[0]* Low Decode Address, Offset: 0x008
200 * Table 38: SCS[1]* Low Decode Address, Offset: 0x208
201 * Table 40: SCS[2]* Low Decode Address, Offset: 0x018
202 * Table 42: SCS[3]* Low Decode Address, Offset: 0x218
203 * Table 44: CS[0]* Low Decode Address, Offset: 0x028
204 * Table 46: CS[1]* Low Decode Address, Offset: 0x228
205 * Table 48: CS[2]* Low Decode Address, Offset: 0x248
206 * Table 50: CS[3]* Low Decode Address, Offset: 0x038
207 * Table 52: BootCS* Low Decode Address, Offset: 0x238
208 * Table 75: CPU 0 Low Decode Address, Offset: 0x290
209 * Table 77: CPU 1 Low Decode Address, Offset: 0x2c0
210 *
211 * 11:00 LowAddr SCS[0] Base Address
212 * 31:12 Reserved Must be 0.
213 */
214
215 /*
216 * Table 37: SCS[0]* High Decode Address, Offset: 0x010
217 * Table 39: SCS[1]* High Decode Address, Offset: 0x210
218 * Table 41: SCS[2]* High Decode Address, Offset: 0x020
219 * Table 43: SCS[3]* High Decode Address, Offset: 0x220
220 * Table 45: CS[0]* High Decode Address, Offset: 0x030
221 * Table 47: CS[1]* High Decode Address, Offset: 0x230
222 * Table 49: CS[2]* High Decode Address, Offset: 0x250
223 * Table 51: CS[3]* High Decode Address, Offset: 0x040
224 * Table 53: BootCS* High Decode Address, Offset: 0x240
225 * Table 76: CPU 0 High Decode Address, Offset: 0x298
226 * Table 78: CPU 1 High Decode Address, Offset: 0x2c8
227 *
228 * 11:00 HighAddr SCS[0] Top Address
229 * 31:12 Reserved
230 */
231
232 /*
233 * Table 54: PCI_0 I/O Low Decode Address, Offset: 0x048
234 * Table 56: PCI_0 Memory 0 Low Decode Address, Offset: 0x058
235 * Table 58: PCI_0 Memory 1 Low Decode Address, Offset: 0x080
236 * Table 60: PCI_0 Memory 2 Low Decode Address, Offset: 0x258
237 * Table 62: PCI_0 Memory 3 Low Decode Address, Offset: 0x280
238 * Table 64: PCI_1 I/O Low Decode Address, Offset: 0x090
239 * Table 66: PCI_1 Memory 0 Low Decode Address, Offset: 0x0a0
240 * Table 68: PCI_1 Memory 1 Low Decode Address, Offset: 0x0b0
241 * Table 70: PCI_1 Memory 2 Low Decode Address, Offset: 0x2a0
242 * Table 72: PCI_1 Memory 3 Low Decode Address, Offset: 0x2b0
243 *
244 * 11:00 LowAddr PCI IO/Memory Space Base Address
245 * 23:12 Reserved
246 * 26:24 PCISwap PCI Master Data Swap Control (0: Byte Swap;
247 * 1: No swapping; 2: Both byte and word swap;
248 * 3: Word swap; 4..7: Reserved)
249 * 27:27 PCIReq64 PCI master REQ64* policy (Relevant only when
250 * configured to 64-bit PCI bus and not I/O)
251 * 0: Assert s REQ64* only when transaction
252 * is longer than 64-bits.
253 * 1: Always assert REQ64*.
254 * 31:28 Reserved
255 */
256 #define GT_PCISwap_GET(v) GT__EXT((v), 24, 3)
257 #define GT_PCISwap_ByteSwap 0
258 #define GT_PCISwap_NoSwap 1
259 #define GT_PCISwap_ByteWordSwap 2
260 #define GT_PCISwap_WordSwap 3
261 #define GT_PCI_LowDecode_PCIReq64 GT__BIT(27)
262
263 /*
264 * Table 55: PCI_0 I/O High Decode Address, Offset: 0x050
265 * Table 57: PCI_0 Memory 0 High Decode Address, Offset: 0x060
266 * Table 59: PCI_0 Memory 1 High Decode Address, Offset: 0x088
267 * Table 61: PCI_0 Memory 2 High Decode Address, Offset: 0x260
268 * Table 63: PCI_0 Memory 3 High Decode Address, Offset: 0x288
269 * Table 65: PCI_1 I/O High Decode Address, Offset: 0x098
270 * Table 67: PCI_1 Memory 0 High Decode Address, Offset: 0x0a8
271 * Table 69: PCI_1 Memory 1 High Decode Address, Offset: 0x0b8
272 * Table 71: PCI_1 Memory 2 High Decode Address, Offset: 0x2a8
273 * Table 73: PCI_1 Memory 3 High Decode Address, Offset: 0x2b8
274 *
275 * 11:00 HighAddr PCI_0 I/O Space Top Address
276 * 31:12 Reserved
277 */
278
279 /*
280 * Table 74: Internal Space Decode, Offset: 0x068
281 * 15:00 IntDecode GT64260 Internal Space Base Address
282 * 23:16 Reserved
283 * 26:24 PCISwap Same as PCI_0 Memory 0 Low Decode Address.
284 * NOTE: Reserved for Galileo Technology usage.
285 * Relevant only for PCI master configuration
286 * transactions on the PCI bus.
287 * 31:27 Reserved
288 */
289
290 /*
291 * Table 79: PCI_0 I/O Address Remap, Offset: 0x0f0
292 * Table 80: PCI_0 Memory 0 Address Remap Low, Offset: 0x0f8
293 * Table 82: PCI_0 Memory 1 Address Remap Low, Offset: 0x100
294 * Table 84: PCI_0 Memory 2 Address Remap Low, Offset: 0x2f8
295 * Table 86: PCI_0 Memory 3 Address Remap Low, Offset: 0x300
296 * Table 88: PCI_1 I/O Address Remap, Offset: 0x108
297 * Table 89: PCI_1 Memory 0 Address Remap Low, Offset: 0x110
298 * Table 91: PCI_1 Memory 1 Address Remap Low, Offset: 0x118
299 * Table 93: PCI_1 Memory 2 Address Remap Low, Offset: 0x310
300 * Table 95: PCI_1 Memory 3 Address Remap Low, Offset: 0x318
301 *
302 * 11:00 Remap PCI IO/Memory Space Address Remap (31:20)
303 * 31:12 Reserved
304 */
305
306 /*
307 * Table 81: PCI_0 Memory 0 Address Remap High, Offset: 0x320
308 * Table 83: PCI_0 Memory 1 Address Remap High, Offset: 0x328
309 * Table 85: PCI_0 Memory 2 Address Remap High, Offset: 0x330
310 * Table 87: PCI_0 Memory 3 Address Remap High, Offset: 0x338
311 * Table 90: PCI_1 Memory 0 Address Remap High, Offset: 0x340
312 * Table 92: PCI_1 Memory 1 Address Remap High, Offset: 0x348
313 * Table 94: PCI_1 Memory 2 Address Remap High, Offset: 0x350
314 * Table 96: PCI_1 Memory 3 Address Remap High, Offset: 0x358
315 *
316 * 31:00 Remap PCI Memory Address Remap (high 32 bits)
317 */
318
319 /*
320 * Table 97: CPU Configuration, Offset: 0x000
321 * 07:00 NoMatchCnt CPU Address Miss Counter
322 * 08:08 NoMatchCntEn CPU Address Miss Counter Enable
323 * NOTE: Relevant only if multi-GT is enabled.
324 * (0: Disabled; 1: Enabled)
325 * 09:09 NoMatchCntExt CPU address miss counter MSB
326 * 10:10 Reserved
327 * 11:11 AACKDelay Address Acknowledge Delay
328 * 0: AACK* is asserted one cycle after TS*.
329 * 1: AACK* is asserted two cycles after TS*.
330 * 12:12 Endianess Must be 0
331 * NOTE: The GT64260 does not support the PowerPC
332 * Little Endian convention
333 * 13:13 Pipeline Pipeline Enable
334 * 0: Disabled. The GT64260 will not respond with
335 * AACK* to a new CPU transaction, before the
336 * previous transaction data phase completes.
337 * 1: Enabled.
338 * 14:14 Reserved
339 * 15:15 TADelay Transfer Acknowledge Delay
340 * 0: TA* is asserted one cycle after AACK*
341 * 1: TA* is asserted two cycles after AACK*
342 * 16:16 RdOOO Read Out of Order Completion
343 * 0: Not Supported, Data is always returned in
344 * order (DTI[0-2] is always driven
345 * 1: Supported
346 * 17:17 StopRetry Relevant only if PCI Retry is enabled
347 * 0: Keep Retry all PCI transactions targeted
348 * to the GT64260.
349 * 1: Stop Retry of PCI transactions.
350 * 18:18 MultiGTDec Multi-GT Address Decode
351 * 0: Normal address decoding
352 * 1: Multi-GT address decoding
353 * 19:19 DPValid CPU DP[0-7] Connection. CPU write parity ...
354 * 0: is not checked. (Not connected)
355 * 1: is checked (Connected)
356 * 21:20 Reserved
357 * 22:22 PErrProp Parity Error Propagation
358 * 0: GT64260 always drives good parity on
359 * DP[0-7] during CPU reads.
360 * 1: GT64260 drives bad parity on DP[0-7] in case
361 * the read response from the target interface
362 * comes with erroneous data indication
363 * (e.g. ECC error from SDRAM interface).
364 * 25:23 Reserved
365 * 26:26 APValid CPU AP[0-3] Connection. CPU address parity ...
366 * 0: is not checked. (Not connected)
367 * 1: is checked (Connected)
368 * 27:27 RemapWrDis Address Remap Registers Write Control
369 * 0: Write to Low Address decode register.
370 * Results in writing of the corresponding
371 * Remap register.
372 * 1: Write to Low Address decode register. No
373 * affect on the corresponding Remap register.
374 * 28:28 ConfSBDis Configuration Read Sync Barrier Disable
375 * 0: enabled; 1: disabled
376 * 29:29 IOSBDis I/O Read Sync Barrier Disable
377 * 0: enabled; 1: disabled
378 * 30:30 ClkSync Clocks Synchronization
379 * 0: The CPU interface is running with SysClk,
380 * which is asynchronous to TClk.
381 * 1: The CPU interface is running with TClk.
382 * 31:31 Reserved
383 */
384 #define GT_CPUCfg_NoMatchCnt_GET(v) GT__EXT((v), 0, 8)
385 #define GT_CPUCfg_NoMatchCntEn GT__BIT( 9)
386 #define GT_CPUCfg_NoMatchCntExt GT__BIT(10)
387 #define GT_CPUCfg_AACKDelay GT__BIT(11)
388 #define GT_CPUCfg_Endianess GT__BIT(12)
389 #define GT_CPUCfg_Pipeline GT__BIT(13)
390 #define GT_CPUCfg_TADelay GT__BIT(15)
391 #define GT_CPUCfg_RdOOO GT__BIT(16)
392 #define GT_CPUCfg_StopRetry GT__BIT(17)
393 #define GT_CPUCfg_MultiGTDec GT__BIT(18)
394 #define GT_CPUCfg_DPValid GT__BIT(19)
395 #define GT_CPUCfg_PErrProp GT__BIT(22)
396 #define GT_CPUCfg_APValid GT__BIT(26)
397 #define GT_CPUCfg_RemapWrDis GT__BIT(27)
398 #define GT_CPUCfg_ConfSBDis GT__BIT(28)
399 #define GT_CPUCfg_IOSBDis GT__BIT(29)
400 #define GT_CPUCfg_ClkSync GT__BIT(30)
401
402 /*
403 * Table 98: CPU Mode, Offset: 0x120, Read only
404 * 01:00 MultiGTID Multi-GT ID
405 * Represents the ID to which the GT64260 responds
406 * to during a multi-GT address decoding period.
407 * 02:02 MultiGT (0: Single; 1: Multiple) GT configuration
408 * 03:03 RetryEn (0: Don't; 1: Do) Retry PCI transactions
409 * 07:04 CPUType
410 * 0x0-0x3: Reserved
411 * 0x4: 64-bit PowerPC CPU, 60x bus
412 * 0x5: 64-bit PowerPC CPU, MPX bus
413 * 0x6-0xf: Reserved
414 * 31:08 Reserved
415 */
416 #define GT_CPUMode_MultiGTID_GET(v) GT__EXT(v, 0, 2)
417 #define GT_CPUMode_MultiGT GT__BIT(2)
418 #define GT_CPUMode_RetryEn GT__BIT(3)
419 #define GT_CPUMode_CPUType_GET(v) GT__EXT(v, 4, 4)
420
421 /*
422 * Table 99: CPU Master Control, Offset: 0x160
423 * 07:00 Reserved
424 * 08:08 IntArb CPU Bus Internal Arbiter Enable
425 * NOTE: Only relevant to 60x bus mode. When
426 * running MPX bus, the GT64260 internal
427 * arbiter must be used.
428 * 0: Disabled. External arbiter is required.
429 * 1: Enabled. Use the GT64260 CPU bus arbiter.
430 * 09:09 IntBusCtl CPU Interface Unit Internal Bus Control
431 * NOTE: This bit must be set to 1. It is reserved
432 * for Galileo Technology usage.
433 * 0: Enable internal bus sharing between master
434 * and slave interfaces.
435 * 1: Disable internal bus sharing between master
436 * and slave interfaces.
437 * 10:10 MWrTrig Master Write Transaction Trigger
438 * 0: With first valid write data
439 * 1: With last valid write data
440 * 11:11 MRdTrig Master Read Response Trigger
441 * 0: With first valid read data
442 * 1: With last valid read data
443 * 12:12 CleanBlock Clean Block Snoop Transaction Support
444 * 0: CPU does not support clean block (603e,750)
445 * 1: CPU supports clean block (604e,G4)
446 * 13:13 FlushBlock Flush Block Snoop Transaction Support
447 * 0: CPU does not support flush block (603e,750)
448 * 1: CPU supports flush block (604e,G4)
449 * 31:14 Reserved
450 */
451 #define GT_CPUMstrCtl_IntArb GT__BIT(8)
452 #define GT_CPUMstrCtl_IntBusCtl GT__BIT(9)
453 #define GT_CPUMstrCtl_MWrTrig GT__BIT(10)
454 #define GT_CPUMstrCtl_MRdTrig GT__BIT(11)
455 #define GT_CPUMstrCtl_CleanBlock GT__BIT(12)
456 #define GT_CPUMstrCtl_FlushBlock GT__BIT(13)
457
458 #define GT_ArbSlice_SDRAM 0x0 /* SDRAM interface snoop request */
459 #define GT_ArbSlice_DEVICE 0x1 /* Device request */
460 #define GT_ArbSlice_NULL 0x2 /* NULL request */
461 #define GT_ArbSlice_PCI0 0x3 /* PCI_0 access */
462 #define GT_ArbSlice_PCI1 0x4 /* PCI_1 access */
463 #define GT_ArbSlice_COMM 0x5 /* Comm unit access */
464 #define GT_ArbSlice_IDMA0123 0x6 /* IDMA channels 0/1/2/3 access */
465 #define GT_ArbSlice_IDMA4567 0x7 /* IDMA channels 4/5/6/7 access */
466 /* 0x8-0xf: Reserved */
467
468 /* Pass in the slice number (from 0..16) as 'n'
469 */
470 #define GT_XbarCtl_GET_ArbSlice(v, n) GT__EXT((v), (((n) & 7)*4, 4)
471
472 /*
473 * Table 100: CPU Interface Crossbar Control Low, Offset: 0x150
474 * 03:00 Arb0 Slice 0 of CPU Master pizza Arbiter
475 * 07:04 Arb1 Slice 1 of CPU Master pizza Arbiter
476 * 11:08 Arb2 Slice 2 of CPU Master pizza Arbiter
477 * 15:12 Arb3 Slice 3 of CPU Master pizza Arbiter
478 * 19:16 Arb4 Slice 4 of CPU Master pizza Arbiter
479 * 23:20 Arb5 Slice 5 of CPU Master pizza Arbiter
480 * 27:24 Arb6 Slice 6 of CPU Master pizza Arbiter
481 * 31:28 Arb7 Slice 7 of CPU Master pizza Arbiter
482 */
483
484 /*
485 * Table 101: CPU Interface Crossbar Control High, Offset: 0x158
486 * 03:00 Arb8 Slice 8 of CPU Master pizza Arbiter
487 * 07:04 Arb9 Slice 9 of CPU Master pizza Arbiter
488 * 11:08 Arb10 Slice 10 of CPU Master pizza Arbiter
489 * 15:12 Arb11 Slice 11 of CPU Master pizza Arbiter
490 * 19:16 Arb12 Slice 12 of CPU Master pizza Arbiter
491 * 23:20 Arb13 Slice 13 of CPU Master pizza Arbiter
492 * 27:24 Arb14 Slice 14 of CPU Master pizza Arbiter
493 * 31:28 Arb15 Slice 15 of CPU Master pizza Arbiter
494 */
495
496 /*
497 * Table 102: CPU Interface Crossbar Timeout, Offset: 0x168
498 * NOTE: Reserved for Galileo Technology usage.
499 * 07:00 Timeout Crossbar Arbiter Timeout Preset Value
500 * 15:08 Reserved
501 * 16:16 TimeoutEn Crossbar Arbiter Timer Enable
502 * (0: Enable; 1: Disable)
503 * 31:17 Reserved
504 */
505
506 /*
507 * Table 103: CPU Read Response Crossbar Control Low, Offset: 0x170
508 * 03:00 Arb0 Slice 0 of CPU Slave pizza Arbiter
509 * 07:04 Arb1 Slice 1 of CPU Slave pizza Arbiter
510 * 11:08 Arb2 Slice 2 of CPU Slave pizza Arbiter
511 * 15:12 Arb3 Slice 3 of CPU Slave pizza Arbiter
512 * 19:16 Arb4 Slice 4 of CPU Slave pizza Arbiter
513 * 23:20 Arb5 Slice 5 of CPU Slave pizza Arbiter
514 * 27:24 Arb6 Slice 6 of CPU Slave pizza Arbiter
515 * 31:28 Arb7 Slice 7 of CPU Slave pizza Arbiter
516 */
517 /*
518 * Table 104: CPU Read Response Crossbar Control High, Offset: 0x178
519 * 03:00 Arb8 Slice 8 of CPU Slave pizza Arbiter
520 * 07:04 Arb9 Slice 9 of CPU Slave pizza Arbiter
521 * 11:08 Arb10 Slice 10 of CPU Slave pizza Arbiter
522 * 15:12 Arb11 Slice 11 of CPU Slave pizza Arbiter
523 * 19:16 Arb12 Slice 12 of CPU Slave pizza Arbiter
524 * 23:20 Arb13 Slice 13 of CPU Slave pizza Arbiter
525 * 27:24 Arb14 Slice 14 of CPU Slave pizza Arbiter
526 * 31:28 Arb15 Slice 15 of CPU Slave pizza Arbiter
527 */
528
529 /*
530 * Table 105: PCI_0 Sync Barrier Virtual Register, Offset: 0x0c0
531 * Table 106: PCI_1 Sync Barrier Virtual Register, Offset: 0x0c8
532 * NOTE: The read data is random and should be ignored.
533 * 31:00 SyncBarrier A CPU read from this register creates a
534 * synchronization barrier cycle.
535 */
536
537 /*
538 * Table 107: CPU Protect Address 0 Low, Offset: 0x180
539 * Table 109: CPU Protect Address 1 Low, Offset: 0x190
540 * Table 111: CPU Protect Address 2 Low, Offset: 0x1a0
541 * Table 113: CPU Protect Address 3 Low, Offset: 0x1b0
542 * Table 115: CPU Protect Address 4 Low, Offset: 0x1c0
543 * Table 117: CPU Protect Address 5 Low, Offset: 0x1d0
544 * Table 119: CPU Protect Address 6 Low, Offset: 0x1e0
545 * Table 121: CPU Protect Address 7 Low, Offset: 0x1f0
546 *
547 * 11:00 LowAddr CPU Protect Region Base Address
548 * Corresponds to address bits[31:20].
549 * 15:12 Reserved. Must be 0
550 * 16:16 AccProtect CPU Access Protect
551 * Access is (0: allowed; 1: forbidden)
552 * 17:17 WrProtect CPU Write Protect
553 * Writes are (0: allowed; 1: forbidden)
554 * 18:18 CacheProtect CPU caching protect. Caching (block read)
555 * is (0: allowed; 1: forbidden)
556 * 31:19 Reserved
557 */
558 #define GT_CPU_AccProtect GT__BIT(16)
559 #define GT_CPU_WrProtect GT__BIT(17)
560 #define GT_CPU_CacheProtect GT__BIT(18)
561
562 /*
563 * Table 108: CPU Protect Address 0 High, Offset: 0x188
564 * Table 110: CPU Protect Address 1 High, Offset: 0x198
565 * Table 112: CPU Protect Address 2 High, Offset: 0x1a8
566 * Table 114: CPU Protect Address 3 High, Offset: 0x1b8
567 * Table 116: CPU Protect Address 4 High, Offset: 0x1c8
568 * Table 118: CPU Protect Address 5 High, Offset: 0x1d8
569 * Table 120: CPU Protect Address 6 High, Offset: 0x1e8
570 * Table 122: CPU Protect Address 7 High, Offset: 0x1f8
571 *
572 * 11:00 HighAddr CPU Protect Region Top Address
573 * Corresponds to address bits[31:20]
574 * 31:12 Reserved
575 */
576
577 /*
578 * Table 123: Snoop Base Address 0, Offset: 0x380
579 * Table 125: Snoop Base Address 1, Offset: 0x390
580 * Table 127: Snoop Base Address 2, Offset: 0x3a0
581 * Table 129: Snoop Base Address 3, Offset: 0x3b0
582 *
583 * 11:00 LowAddr Snoop Region Base Address [31:20]
584 * 15:12 Reserved Must be 0.
585 * 17:16 Snoop Snoop Type
586 * 0x0: No Snoop
587 * 0x1: Snoop to WT region
588 * 0x2: Snoop to WB region
589 * 0x3: Reserved
590 * 31:18 Reserved
591 */
592 #define GT_Snoop_GET(v) GT__EXT((v), 16, 2)
593 #define GT_Snoop_INS(v) GT__INS((v), 16)
594 #define GT_Snoop_None 0
595 #define GT_Snoop_WT 1
596 #define GT_Snoop_WB 2
597
598
599 /*
600 * Table 124: Snoop Top Address 0, Offset: 0x388
601 * Table 126: Snoop Top Address 1, Offset: 0x398
602 * Table 128: Snoop Top Address 2, Offset: 0x3a8
603 * Table 130: Snoop Top Address 3, Offset: 0x3b8
604 * 11:00 HighAddr Snoop Region Top Address [31:20]
605 * 31:12 Reserved
606 */
607
608
609 /*
610 * Table 131: CPU Error Address Low, Offset: 0x070, Read Only.
611 * In case of multiple errors, only the first one is latched. New error
612 * report latching is enabled only after the CPU Error Address Low register
613 * is being read.
614 * 31:00 ErrAddr Latched address bits [31:0] of a CPU
615 * transaction in case of:
616 * o illegal address (failed address decoding)
617 * o access protection violation
618 * o bad data parity
619 * o bad address parity
620 * Upon address latch, no new address are
621 * registered (due to additional error condition),
622 * until the register is being read.
623 */
624
625 /*
626 * Table 132: CPU Error Address High, Offset: 0x078, Read Only.
627 * Once data is latched, no new data can be registered (due to additional
628 * error condition), until CPU Error Low Address is being read (which
629 * implies, it should be the last being read by the interrupt handler).
630 * 03:00 Reserved
631 * 07:04 ErrPar Latched address parity bits in case
632 * of bad CPU address parity detection.
633 * 31:08 Reserved
634 */
635 #define GT_CPUErrorAddrHigh_ErrPar_GET(v) GT__EXT((v), 4, 4)
636
637 /*
638 * Table 133: CPU Error Data Low, Offset: 0x128, Read only.
639 * 31:00 PErrData Latched data bits [31:0] in case of bad data
640 * parity sampled on write transactions or on
641 * master read transactions.
642 */
643
644 /*
645 * Table 134: CPU Error Data High, Offset: 0x130, Read only.
646 * 31:00 PErrData Latched data bits [63:32] in case of bad data
647 * parity sampled on write transactions or on
648 * master read transactions.
649 */
650
651 /*
652 * Table 135: CPU Error Parity, Offset: 0x138, Read only.
653 * 07:00 PErrPar Latched data parity bus in case of bad data
654 * parity sampled on write transactions or on
655 * master read transactions.
656 * 31:10 Reserved
657 */
658 #define GT_CPUErrorParity_PErrPar_GET(v) GT__EXT((v), 0, 8)
659
660 /*
661 * Table 136: CPU Error Cause, Offset: 0x140
662 * Bits[7:0] are clear only. A cause bit is set upon an error condition
663 * occurrence. Write a 0 value to clear the bit. Writing a 1 value has
664 * no affect.
665 * 00:00 AddrOut CPU Address Out of Range
666 * 01:01 AddrPErr Bad Address Parity Detected
667 * 02:02 TTErr Transfer Type Violation.
668 * The CPU attempts to burst (read or write) to an
669 * internal register.
670 * 03:03 AccErr Access to a Protected Region
671 * 04:04 WrErr Write to a Write Protected Region
672 * 05:05 CacheErr Read from a Caching protected region
673 * 06:06 WrDataPErr Bad Write Data Parity Detected
674 * 07:07 RdDataPErr Bad Read Data Parity Detected
675 * 26:08 Reserved
676 * 31:27 Sel Specifies the error event currently being
677 * reported in Error Address, Error Data, and
678 * Error Parity registers.
679 * 0x0: AddrOut
680 * 0x1: AddrPErr
681 * 0x2: TTErr
682 * 0x3: AccErr
683 * 0x4: WrErr
684 * 0x5: CacheErr
685 * 0x6: WrDataPErr
686 * 0x7: RdDataPErr
687 * 0x8-0x1f: Reserved
688 */
689 #define GT_CPUError_AddrOut GT__BIT(GT_CPUError_Sel_AddrOut)
690 #define GT_CPUError_AddrPErr GT__BIT(GT_CPUError_Sel_AddrPErr)
691 #define GT_CPUError_TTErr GT__BIT(GT_CPUError_Sel_TTErr)
692 #define GT_CPUError_AccErr GT__BIT(GT_CPUError_Sel_AccErr)
693 #define GT_CPUError_WrErr GT__BIT(GT_CPUError_Sel_WrPErr)
694 #define GT_CPUError_CacheErr GT__BIT(GT_CPUError_Sel_CachePErr)
695 #define GT_CPUError_WrDataPErr GT__BIT(GT_CPUError_Sel_WrDataPErr)
696 #define GT_CPUError_RdDataPErr GT__BIT(GT_CPUError_Sel_RdDataPErr)
697
698 #define GT_CPUError_Sel_AddrOut 0
699 #define GT_CPUError_Sel_AddrPErr 1
700 #define GT_CPUError_Sel_TTErr 2
701 #define GT_CPUError_Sel_AccErr 3
702 #define GT_CPUError_Sel_WrErr 4
703 #define GT_CPUError_Sel_CacheErr 5
704 #define GT_CPUError_Sel_WrDataPErr 6
705 #define GT_CPUError_Sel_RdDataPErr 7
706
707 #define GT_CPUError_Sel_GET(v) GT__EXT((v), 27, 5)
708
709 /*
710 * Table 137: CPU Error Mask, Offset: 0x148
711 * 00:00 AddrOut If set to 1, enables AddrOut interrupt.
712 * 01:01 AddrPErr If set to 1, enables AddrPErr interrupt.
713 * 02:02 TTErr If set to 1, enables TTErr interrupt.
714 * 03:03 AccErr If set to 1, enables AccErr interrupt.
715 * 04:04 WrErr If set to 1, enables WrErr interrupt.
716 * 05:05 CacheErr If set to 1, enables CacheErr interrupt.
717 * 06:06 WrDataPErr If set to 1, enables WrDataPErr interrupt.
718 * 07:07 RdDataPErr If set to 1, enables RdDataPErr interrupt.
719 * 31:08 Reserved
720 */
721
722 /*
723 * Comm Unit Interrupt registers
724 */
725 #define GT_CommUnitIntr_Cause 0xf310
726 #define GT_CommUnitIntr_Mask 0xf314
727 #define GT_CommUnitIntr_ErrAddr 0xf318
728
729 #define GT_CommUnitIntr_E0 0x00000007
730 #define GT_CommUnitIntr_E1 0x00000070
731 #define GT_CommUnitIntr_E2 0x00000700
732 #define GT_CommUnitIntr_S0 0x00070000
733 #define GT_CommUnitIntr_S1 0x00700000
734 #define GT_CommUnitIntr_Sel 0x70000000
735
736 /*
737 * SDRAM Error Report (ECC) Registers
738 */
739 #define GT_ECC_Data_Lo 0x484 /* latched Error Data (low) */
740 #define GT_ECC_Data_Hi 0x480 /* latched Error Data (high) */
741 #define GT_ECC_Addr 0x490 /* latched Error Address */
742 #define GT_ECC_Rec 0x488 /* latched ECC code from SDRAM */
743 #define GT_ECC_Calc 0x48c /* latched ECC code from SDRAM */
744 #define GT_ECC_Ctl 0x494 /* ECC Control */
745 #define GT_ECC_Count 0x498 /* ECC 1-bit error count */
746
747 /*
748 * Watchdog Registers
749 */
750 #define GT_WDOG_Config 0xb410
751 #define GT_WDOG_Value 0xb414
752 #define GT_WDOG_Value_NMI GT__MASK(24)
753 #define GT_WDOG_Config_Preset GT__MASK(24)
754 #define GT_WDOG_Config_Ctl1a GT__BIT(24)
755 #define GT_WDOG_Config_Ctl1b GT__BIT(25)
756 #define GT_WDOG_Config_Ctl2a GT__BIT(26)
757 #define GT_WDOG_Config_Ctl2b GT__BIT(27)
758 #define GT_WDOG_Config_Enb GT__BIT(31)
759
760 #define GT_WDOG_NMI_DFLT (GT__MASK(24) & GT_WDOG_Value_NMI)
761 #define GT_WDOG_Preset_DFLT (GT__MASK(22) & GT_WDOG_Config_Preset)
762
763 /*
764 * Device Bus Interrupts
765 */
766 #define GT_DEVBUS_ICAUSE 0x4d0 /* Device Interrupt Cause */
767 #define GT_DEVBUS_IMASK 0x4d4 /* Device Interrupt Mask */
768 #define GT_DEVBUS_ERR_ADDR 0x4d8 /* Device Error Address */
769
770 /*
771 * bit defines for GT_DEVBUS_ICAUSE, GT_DEVBUS_IMASK
772 */
773 #define GT_DEVBUS_DBurstErr GT__BIT(0)
774 #define GT_DEVBUS_DRdyErr GT__BIT(1)
775 #define GT_DEVBUS_Sel GT__BIT(27)
776 #define GT_DEVBUS_RES ~(GT_DEVBUS_DBurstErr|GT_DEVBUS_DRdyErr|GT_DEVBUS_Sel)
777
778
779 #endif /* !_DISCOVERY_DEV_GTREG_H */
NetBSD on the FriendlyARM MINI2440