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[netbsd-mini2440.git] / sys / dev / mii / ciphy.c
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1 /* $NetBSD: ciphy.c,v 1.18 2009/05/12 13:16:02 cegger Exp $ */
3 /*-
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.18 2009/05/12 13:16:02 cegger Exp $");
41 * Driver for the Cicada CS8201 10/100/1000 copper PHY.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/device.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/bus.h>
51 #include <net/if.h>
52 #include <net/if_arp.h>
53 #include <net/if_media.h>
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
57 #include <dev/mii/miidevs.h>
59 #include <dev/mii/ciphyreg.h>
61 static int ciphymatch(device_t, cfdata_t, void *);
62 static void ciphyattach(device_t, device_t, void *);
64 CFATTACH_DECL_NEW(ciphy, sizeof(struct mii_softc),
65 ciphymatch, ciphyattach, mii_phy_detach, mii_phy_activate);
67 static int ciphy_service(struct mii_softc *, struct mii_data *, int);
68 static void ciphy_status(struct mii_softc *);
69 static void ciphy_reset(struct mii_softc *);
70 static void ciphy_fixup(struct mii_softc *);
72 static const struct mii_phy_funcs ciphy_funcs = {
73 ciphy_service, ciphy_status, mii_phy_reset,
76 static const struct mii_phydesc ciphys[] = {
77 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201,
78 MII_STR_CICADA_CS8201 },
80 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201A,
81 MII_STR_CICADA_CS8201A },
83 { MII_OUI_CICADA, MII_MODEL_CICADA_CS8201B,
84 MII_STR_CICADA_CS8201B },
86 { MII_OUI_xxCICADA, MII_MODEL_CICADA_CS8201,
87 MII_STR_CICADA_CS8201 },
89 { MII_OUI_xxCICADA, MII_MODEL_CICADA_CS8201A,
90 MII_STR_CICADA_CS8201A },
92 { MII_OUI_xxCICADA, MII_MODEL_xxCICADA_CS8201B,
93 MII_STR_xxCICADA_CS8201B },
95 { 0, 0,
96 NULL },
99 static int
100 ciphymatch(device_t parent, cfdata_t match,
101 void *aux)
103 struct mii_attach_args *ma = aux;
105 if (mii_phy_match(ma, ciphys) != NULL)
106 return (10);
108 return (0);
111 static void
112 ciphyattach(device_t parent, device_t self, void *aux)
114 struct mii_softc *sc = device_private(self);
115 struct mii_attach_args *ma = aux;
116 struct mii_data *mii = ma->mii_data;
117 const struct mii_phydesc *mpd;
119 mpd = mii_phy_match(ma, ciphys);
120 aprint_naive(": Media interface\n");
121 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
123 sc->mii_dev = self;
124 sc->mii_inst = mii->mii_instance;
125 sc->mii_phy = ma->mii_phyno;
126 sc->mii_funcs = &ciphy_funcs;
127 sc->mii_pdata = mii;
128 sc->mii_flags = ma->mii_flags;
129 sc->mii_anegticks = MII_ANEGTICKS;
131 sc->mii_flags |= MIIF_NOISOLATE;
133 ciphy_reset(sc);
135 sc->mii_capabilities =
136 PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
137 if (sc->mii_capabilities & BMSR_EXTSTAT)
138 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
139 aprint_normal_dev(self, "");
140 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0)
141 aprint_error("no media present");
142 else
143 mii_phy_add_media(sc);
144 aprint_normal("\n");
147 static int
148 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
150 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
151 int reg, speed, gig;
153 switch (cmd) {
154 case MII_POLLSTAT:
156 * If we're not polling our PHY instance, just return.
158 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
159 return (0);
160 break;
162 case MII_MEDIACHG:
164 * If the media indicates a different PHY instance,
165 * isolate ourselves.
167 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
168 reg = PHY_READ(sc, MII_BMCR);
169 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
170 return (0);
174 * If the interface is not up, don't do anything.
176 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
177 break;
179 ciphy_fixup(sc); /* XXX hardware bug work-around */
181 switch (IFM_SUBTYPE(ife->ifm_media)) {
182 case IFM_AUTO:
183 #ifdef foo
185 * If we're already in auto mode, just return.
187 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
188 return (0);
189 #endif
190 (void) mii_phy_auto(sc, 0);
191 break;
192 case IFM_1000_T:
193 speed = CIPHY_S1000;
194 goto setit;
195 case IFM_100_TX:
196 speed = CIPHY_S100;
197 goto setit;
198 case IFM_10_T:
199 speed = CIPHY_S10;
200 setit:
201 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
202 speed |= CIPHY_BMCR_FDX;
203 gig = CIPHY_1000CTL_AFD;
204 } else {
205 gig = CIPHY_1000CTL_AHD;
208 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
209 PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
210 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
212 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
213 break;
215 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
216 PHY_WRITE(sc, CIPHY_MII_BMCR,
217 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
220 * When setting the link manually, one side must
221 * be the master and the other the slave. However
222 * ifmedia doesn't give us a good way to specify
223 * this, so we fake it by using one of the LINK
224 * flags. If LINK0 is set, we program the PHY to
225 * be a master, otherwise it's a slave.
227 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
228 PHY_WRITE(sc, CIPHY_MII_1000CTL,
229 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
230 } else {
231 PHY_WRITE(sc, CIPHY_MII_1000CTL,
232 gig|CIPHY_1000CTL_MSE);
234 break;
235 case IFM_NONE:
236 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
237 break;
238 case IFM_100_T4:
239 default:
240 return (EINVAL);
242 break;
244 case MII_TICK:
246 * If we're not currently selected, just return.
248 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
249 return (0);
252 * Is the interface even up?
254 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
255 return (0);
258 * Only used for autonegotiation.
260 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
261 break;
264 * Check to see if we have link. If we do, we don't
265 * need to restart the autonegotiation process. Read
266 * the BMSR twice in case it's latched.
268 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
269 if (reg & BMSR_LINK)
270 break;
273 * Only retry autonegotiation every 5 seconds.
275 if (++sc->mii_ticks <= MII_ANEGTICKS)
276 break;
278 sc->mii_ticks = 0;
279 mii_phy_auto(sc, 0);
280 return (0);
283 /* Update the media status. */
284 ciphy_status(sc);
287 * Callback if something changed. Note that we need to poke
288 * apply fixups for certain PHY revs.
290 if (sc->mii_media_active != mii->mii_media_active ||
291 sc->mii_media_status != mii->mii_media_status ||
292 cmd == MII_MEDIACHG) {
293 ciphy_fixup(sc);
295 mii_phy_update(sc, cmd);
296 return (0);
299 static void
300 ciphy_status(struct mii_softc *sc)
302 struct mii_data *mii = sc->mii_pdata;
303 int bmsr, bmcr;
305 mii->mii_media_status = IFM_AVALID;
306 mii->mii_media_active = IFM_ETHER;
308 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
310 if (bmsr & BMSR_LINK)
311 mii->mii_media_status |= IFM_ACTIVE;
313 bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
315 if (bmcr & CIPHY_BMCR_LOOP)
316 mii->mii_media_active |= IFM_LOOP;
318 if (bmcr & CIPHY_BMCR_AUTOEN) {
319 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
320 /* Erg, still trying, I guess... */
321 mii->mii_media_active |= IFM_NONE;
322 return;
326 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
327 switch (bmsr & CIPHY_AUXCSR_SPEED) {
328 case CIPHY_SPEED10:
329 mii->mii_media_active |= IFM_10_T;
330 break;
331 case CIPHY_SPEED100:
332 mii->mii_media_active |= IFM_100_TX;
333 break;
334 case CIPHY_SPEED1000:
335 mii->mii_media_active |= IFM_1000_T;
336 break;
337 default:
338 aprint_error_dev(sc->mii_dev, "unknown PHY speed %x\n",
339 bmsr & CIPHY_AUXCSR_SPEED);
340 break;
343 if (bmsr & CIPHY_AUXCSR_FDX)
344 mii->mii_media_active |= IFM_FDX;
346 return;
349 static void
350 ciphy_reset(struct mii_softc *sc)
352 mii_phy_reset(sc);
353 DELAY(1000);
355 return;
358 #define PHY_SETBIT(x, y, z) \
359 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
360 #define PHY_CLRBIT(x, y, z) \
361 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
363 static void
364 ciphy_fixup(struct mii_softc *sc)
366 uint16_t model;
367 uint16_t status, speed;
369 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
370 status = PHY_READ(sc, CIPHY_MII_AUXCSR);
371 speed = status & CIPHY_AUXCSR_SPEED;
373 if (device_is_a(device_parent(sc->mii_dev), "nfe")) {
374 /* need to set for 2.5V RGMII for NVIDIA adapters */
375 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
376 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
379 switch (model) {
380 case MII_MODEL_CICADA_CS8201:
382 /* Turn off "aux mode" (whatever that means) */
383 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
386 * Work around speed polling bug in VT3119/VT3216
387 * when using MII in full duplex mode.
389 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
390 (status & CIPHY_AUXCSR_FDX)) {
391 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
392 } else {
393 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
396 /* Enable link/activity LED blink. */
397 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK);
399 break;
401 case MII_MODEL_CICADA_CS8201A:
402 case MII_MODEL_CICADA_CS8201B:
405 * Work around speed polling bug in VT3119/VT3216
406 * when using MII in full duplex mode.
408 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
409 (status & CIPHY_AUXCSR_FDX)) {
410 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
411 } else {
412 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
415 break;
416 default:
417 aprint_error_dev(sc->mii_dev, "unknown CICADA PHY model %x\n",
418 model);
419 break;
422 return;