sys/dev/mii/rgephy.c

   1 /*      $NetBSD: rgephy.c,v 1.27 2009/04/28 13:25:17 tsutsui Exp $      */
   2
   3 /*
   4  * Copyright (c) 2003
   5  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #include <sys/cdefs.h>
  36 __KERNEL_RCSID(0, "$NetBSD: rgephy.c,v 1.27 2009/04/28 13:25:17 tsutsui Exp $");
  37
  38
  39 /*
  40  * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/device.h>
  47 #include <sys/socket.h>
  48
  49
  50 #include <net/if.h>
  51 #include <net/if_media.h>
  52
  53 #include <dev/mii/mii.h>
  54 #include <dev/mii/miivar.h>
  55 #include <dev/mii/miidevs.h>
  56
  57 #include <dev/mii/rgephyreg.h>
  58
  59 #include <dev/ic/rtl81x9reg.h>
  60
  61 static int      rgephy_match(device_t, cfdata_t, void *);
  62 static void     rgephy_attach(device_t, device_t, void *);
  63
  64 struct rgephy_softc {
  65         struct mii_softc mii_sc;
  66         int mii_revision;
  67 };
  68
  69 CFATTACH_DECL_NEW(rgephy, sizeof(struct rgephy_softc),
  70     rgephy_match, rgephy_attach, mii_phy_detach, mii_phy_activate);
  71
  72
  73 static int      rgephy_service(struct mii_softc *, struct mii_data *, int);
  74 static void     rgephy_status(struct mii_softc *);
  75 static int      rgephy_mii_phy_auto(struct mii_softc *);
  76 static void     rgephy_reset(struct mii_softc *);
  77 static void     rgephy_loop(struct mii_softc *);
  78 static void     rgephy_load_dspcode(struct mii_softc *);
  79
  80 static const struct mii_phy_funcs rgephy_funcs = {
  81         rgephy_service, rgephy_status, rgephy_reset,
  82 };
  83
  84 static const struct mii_phydesc rgephys[] = {
  85         { MII_OUI_xxREALTEK,            MII_MODEL_xxREALTEK_RTL8169S,
  86           MII_STR_xxREALTEK_RTL8169S },
  87
  88         { MII_OUI_REALTEK,              MII_MODEL_REALTEK_RTL8169S,
  89           MII_STR_REALTEK_RTL8169S },
  90
  91         { 0,                            0,
  92           NULL }
  93 };
  94
  95 static int
  96 rgephy_match(device_t parent, cfdata_t match, void *aux)
  97 {
  98         struct mii_attach_args *ma = aux;
  99
 100         if (mii_phy_match(ma, rgephys) != NULL)
 101                 return 10;
 102
 103         return 0;
 104 }
 105
 106 static void
 107 rgephy_attach(device_t parent, device_t self, void *aux)
 108 {
 109         struct rgephy_softc *rsc = device_private(self);
 110         struct mii_softc *sc = &rsc->mii_sc;
 111         struct mii_attach_args *ma = aux;
 112         struct mii_data *mii = ma->mii_data;
 113         const struct mii_phydesc *mpd;
 114         int rev;
 115         const char *sep = "";
 116
 117         ma = aux;
 118         mii = ma->mii_data;
 119
 120         rev = MII_REV(ma->mii_id2);
 121         mpd = mii_phy_match(ma, rgephys);
 122         aprint_naive(": Media interface\n");
 123         aprint_normal(": %s, rev. %d\n", mpd->mpd_name, rev);
 124
 125         rsc->mii_revision = rev;
 126
 127         sc->mii_dev = self;
 128         sc->mii_inst = mii->mii_instance;
 129         sc->mii_phy = ma->mii_phyno;
 130         sc->mii_pdata = mii;
 131         sc->mii_flags = mii->mii_flags;
 132         sc->mii_anegticks = MII_ANEGTICKS_GIGE;
 133
 134         sc->mii_funcs = &rgephy_funcs;
 135
 136 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
 137 #define PRINT(n)        aprint_normal("%s%s", sep, (n)); sep = ", "
 138
 139 #ifdef __FreeBSD__
 140         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
 141             BMCR_LOOP|BMCR_S100);
 142 #endif
 143
 144         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 145         sc->mii_capabilities &= ~BMSR_ANEG;
 146
 147         /*
 148          * FreeBSD does not check EXSTAT, but instead adds gigabit
 149          * media explicitly. Why?
 150          */
 151         aprint_normal_dev(self, "");
 152         if (sc->mii_capabilities & BMSR_EXTSTAT) {
 153                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 154         }
 155         mii_phy_add_media(sc);
 156
 157         /* rtl8169S does not report auto-sense; add manually.  */
 158         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), MII_NMEDIA);
 159         sep =", ";
 160         PRINT("auto");
 161
 162 #undef  ADD
 163 #undef  PRINT
 164
 165         rgephy_reset(sc);
 166         aprint_normal("\n");
 167 }
 168
 169 static int
 170 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
 171 {
 172         struct rgephy_softc *rsc;
 173         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 174         int reg, speed, gig, anar;
 175
 176         rsc = (struct rgephy_softc *)sc;
 177
 178         switch (cmd) {
 179         case MII_POLLSTAT:
 180                 /*
 181                  * If we're not polling our PHY instance, just return.
 182                  */
 183                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 184                         return 0;
 185                 break;
 186
 187         case MII_MEDIACHG:
 188                 /*
 189                  * If the media indicates a different PHY instance,
 190                  * isolate ourselves.
 191                  */
 192                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 193                         reg = PHY_READ(sc, MII_BMCR);
 194                         PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
 195                         return 0;
 196                 }
 197
 198                 /*
 199                  * If the interface is not up, don't do anything.
 200                  */
 201                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 202                         break;
 203
 204                 rgephy_reset(sc);       /* XXX hardware bug work-around */
 205
 206                 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
 207                 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
 208                     RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
 209
 210                 switch (IFM_SUBTYPE(ife->ifm_media)) {
 211                 case IFM_AUTO:
 212 #ifdef foo
 213                         /*
 214                          * If we're already in auto mode, just return.
 215                          */
 216                         if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
 217                                 return 0;
 218 #endif
 219                         (void)rgephy_mii_phy_auto(sc);
 220                         break;
 221                 case IFM_1000_T:
 222                         speed = RGEPHY_S1000;
 223                         goto setit;
 224                 case IFM_100_TX:
 225                         speed = RGEPHY_S100;
 226                         anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
 227                         goto setit;
 228                 case IFM_10_T:
 229                         speed = RGEPHY_S10;
 230                         anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
 231  setit:
 232                         rgephy_loop(sc);
 233                         if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
 234                                 speed |= RGEPHY_BMCR_FDX;
 235                                 gig = RGEPHY_1000CTL_AFD;
 236                                 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
 237                         } else {
 238                                 gig = RGEPHY_1000CTL_AHD;
 239                                 anar &=
 240                                     ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
 241                         }
 242
 243                         if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
 244                                 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
 245                                 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
 246                                 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
 247                                     RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
 248                                 break;
 249                         }
 250
 251                         /*
 252                          * When setting the link manually, one side must
 253                          * be the master and the other the slave. However
 254                          * ifmedia doesn't give us a good way to specify
 255                          * this, so we fake it by using one of the LINK
 256                          * flags. If LINK0 is set, we program the PHY to
 257                          * be a master, otherwise it's a slave.
 258                          */
 259                         if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
 260                                 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 261                                     gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
 262                         } else {
 263                                 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 264                                     gig|RGEPHY_1000CTL_MSE);
 265                         }
 266                         PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
 267                             RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
 268                         break;
 269                 case IFM_NONE:
 270                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
 271                         break;
 272                 case IFM_100_T4:
 273                 default:
 274                         return EINVAL;
 275                 }
 276                 break;
 277
 278         case MII_TICK:
 279                 /*
 280                  * If we're not currently selected, just return.
 281                  */
 282                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
 283                         return 0;
 284
 285                 /*
 286                  * Is the interface even up?
 287                  */
 288                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 289                         return 0;
 290
 291                 /*
 292                  * Only used for autonegotiation.
 293                  */
 294                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
 295                         break;
 296
 297                 /*
 298                  * Check to see if we have link.  If we do, we don't
 299                  * need to restart the autonegotiation process.  Read
 300                  * the BMSR twice in case it's latched.
 301                  */
 302                 if (rsc->mii_revision >= 2) {
 303                         /* RTL8211B(L) */
 304                         reg = PHY_READ(sc, RGEPHY_MII_SSR);
 305                         if (reg & RGEPHY_SSR_LINK) {
 306                                 sc->mii_ticks = 0;
 307                                 break;
 308                         }
 309                 } else {
 310                         reg = PHY_READ(sc, RTK_GMEDIASTAT);
 311                         if ((reg & RTK_GMEDIASTAT_LINK) != 0) {
 312                                 sc->mii_ticks = 0;
 313                                 break;
 314                         }
 315                 }
 316
 317                 /* Announce link loss right after it happens. */
 318                 if (sc->mii_ticks++ == 0)
 319                         break;
 320
 321                 /* Only retry autonegotiation every mii_anegticks seconds. */
 322                 if (sc->mii_ticks <= sc->mii_anegticks)
 323                         return 0;
 324
 325                 sc->mii_ticks = 0;
 326                 rgephy_mii_phy_auto(sc);
 327                 break;
 328         }
 329
 330         /* Update the media status. */
 331         rgephy_status(sc);
 332
 333         /*
 334          * Callback if something changed. Note that we need to poke
 335          * the DSP on the RealTek PHYs if the media changes.
 336          *
 337          */
 338         if (sc->mii_media_active != mii->mii_media_active ||
 339             sc->mii_media_status != mii->mii_media_status ||
 340             cmd == MII_MEDIACHG) {
 341                 rgephy_load_dspcode(sc);
 342         }
 343         mii_phy_update(sc, cmd);
 344         return 0;
 345 }
 346
 347 static void
 348 rgephy_status(struct mii_softc *sc)
 349 {
 350         struct rgephy_softc *rsc;
 351         struct mii_data *mii = sc->mii_pdata;
 352         int gstat, bmsr, bmcr;
 353         uint16_t ssr;
 354
 355         mii->mii_media_status = IFM_AVALID;
 356         mii->mii_media_active = IFM_ETHER;
 357
 358         rsc = (struct rgephy_softc *)sc;
 359         if (rsc->mii_revision >= 2) {
 360                 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
 361                 if (ssr & RGEPHY_SSR_LINK)
 362                         mii->mii_media_status |= IFM_ACTIVE;
 363         } else {
 364                 gstat = PHY_READ(sc, RTK_GMEDIASTAT);
 365                 if ((gstat & RTK_GMEDIASTAT_LINK) != 0)
 366                         mii->mii_media_status |= IFM_ACTIVE;
 367         }
 368
 369         bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
 370         bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
 371
 372         if ((bmcr & RGEPHY_BMCR_ISO) != 0) {
 373                 mii->mii_media_active |= IFM_NONE;
 374                 mii->mii_media_status = 0;
 375                 return;
 376         }
 377
 378         if ((bmcr & RGEPHY_BMCR_LOOP) != 0)
 379                 mii->mii_media_active |= IFM_LOOP;
 380
 381         if ((bmcr & RGEPHY_BMCR_AUTOEN) != 0) {
 382                 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
 383                         /* Erg, still trying, I guess... */
 384                         mii->mii_media_active |= IFM_NONE;
 385                         return;
 386                 }
 387         }
 388
 389         if (rsc->mii_revision >= 2) {
 390                 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
 391                 switch (ssr & RGEPHY_SSR_SPD_MASK) {
 392                 case RGEPHY_SSR_S1000:
 393                         mii->mii_media_active |= IFM_1000_T;
 394                         break;
 395                 case RGEPHY_SSR_S100:
 396                         mii->mii_media_active |= IFM_100_TX;
 397                         break;
 398                 case RGEPHY_SSR_S10:
 399                         mii->mii_media_active |= IFM_10_T;
 400                         break;
 401                 default:
 402                         mii->mii_media_active |= IFM_NONE;
 403                         break;
 404                 }
 405                 if (ssr & RGEPHY_SSR_FDX)
 406                         mii->mii_media_active |= mii_phy_flowstatus(sc) |
 407                             IFM_FDX;
 408                 else
 409                         mii->mii_media_active |= IFM_HDX;
 410         } else {
 411                 gstat = PHY_READ(sc, RTK_GMEDIASTAT);
 412                 if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0)
 413                         mii->mii_media_active |= IFM_1000_T;
 414                 else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0)
 415                         mii->mii_media_active |= IFM_100_TX;
 416                 else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0)
 417                         mii->mii_media_active |= IFM_10_T;
 418                 else
 419                         mii->mii_media_active |= IFM_NONE;
 420                 if ((gstat & RTK_GMEDIASTAT_FDX) != 0)
 421                         mii->mii_media_active |= mii_phy_flowstatus(sc) |
 422                             IFM_FDX;
 423                 else
 424                         mii->mii_media_active |= IFM_HDX;
 425         }
 426 }
 427
 428
 429 static int
 430 rgephy_mii_phy_auto(struct mii_softc *mii)
 431 {
 432         int anar;
 433
 434         rgephy_loop(mii);
 435         rgephy_reset(mii);
 436
 437         anar = BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA;
 438         if (mii->mii_flags & MIIF_DOPAUSE)
 439                 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
 440
 441         PHY_WRITE(mii, RGEPHY_MII_ANAR, anar);
 442         DELAY(1000);
 443         PHY_WRITE(mii, RGEPHY_MII_1000CTL,
 444             RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
 445         DELAY(1000);
 446         PHY_WRITE(mii, RGEPHY_MII_BMCR,
 447             RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
 448         DELAY(100);
 449
 450         return EJUSTRETURN;
 451 }
 452
 453 static void
 454 rgephy_loop(struct mii_softc *sc)
 455 {
 456         struct rgephy_softc *rsc;
 457         uint32_t bmsr;
 458         int i;
 459
 460         rsc = (struct rgephy_softc *)sc;
 461         if (rsc->mii_revision < 2) {
 462                 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
 463                 DELAY(1000);
 464         }
 465
 466         for (i = 0; i < 15000; i++) {
 467                 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
 468                 if ((bmsr & RGEPHY_BMSR_LINK) == 0) {
 469 #if 0
 470                         device_printf(sc->mii_dev, "looped %d\n", i);
 471 #endif
 472                         break;
 473                 }
 474                 DELAY(10);
 475         }
 476 }
 477
 478 #define PHY_SETBIT(x, y, z) \
 479         PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
 480 #define PHY_CLRBIT(x, y, z) \
 481         PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
 482
 483 /*
 484  * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
 485  * existing revisions of the 8169S/8110S chips need to be tuned in
 486  * order to reliably negotiate a 1000Mbps link. This is only needed
 487  * for rev 0 and rev 1 of the PHY. Later versions work without
 488  * any fixups.
 489  */
 490 static void
 491 rgephy_load_dspcode(struct mii_softc *sc)
 492 {
 493         struct rgephy_softc *rsc;
 494         int val;
 495
 496         rsc = (struct rgephy_softc *)sc;
 497         if (rsc->mii_revision >= 2)
 498                 return;
 499
 500 #if 1
 501         PHY_WRITE(sc, 31, 0x0001);
 502         PHY_WRITE(sc, 21, 0x1000);
 503         PHY_WRITE(sc, 24, 0x65C7);
 504         PHY_CLRBIT(sc, 4, 0x0800);
 505         val = PHY_READ(sc, 4) & 0xFFF;
 506         PHY_WRITE(sc, 4, val);
 507         PHY_WRITE(sc, 3, 0x00A1);
 508         PHY_WRITE(sc, 2, 0x0008);
 509         PHY_WRITE(sc, 1, 0x1020);
 510         PHY_WRITE(sc, 0, 0x1000);
 511         PHY_SETBIT(sc, 4, 0x0800);
 512         PHY_CLRBIT(sc, 4, 0x0800);
 513         val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
 514         PHY_WRITE(sc, 4, val);
 515         PHY_WRITE(sc, 3, 0xFF41);
 516         PHY_WRITE(sc, 2, 0xDE60);
 517         PHY_WRITE(sc, 1, 0x0140);
 518         PHY_WRITE(sc, 0, 0x0077);
 519         val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
 520         PHY_WRITE(sc, 4, val);
 521         PHY_WRITE(sc, 3, 0xDF01);
 522         PHY_WRITE(sc, 2, 0xDF20);
 523         PHY_WRITE(sc, 1, 0xFF95);
 524         PHY_WRITE(sc, 0, 0xFA00);
 525         val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
 526         PHY_WRITE(sc, 4, val);
 527         PHY_WRITE(sc, 3, 0xFF41);
 528         PHY_WRITE(sc, 2, 0xDE20);
 529         PHY_WRITE(sc, 1, 0x0140);
 530         PHY_WRITE(sc, 0, 0x00BB);
 531         val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
 532         PHY_WRITE(sc, 4, val);
 533         PHY_WRITE(sc, 3, 0xDF01);
 534         PHY_WRITE(sc, 2, 0xDF20);
 535         PHY_WRITE(sc, 1, 0xFF95);
 536         PHY_WRITE(sc, 0, 0xBF00);
 537         PHY_SETBIT(sc, 4, 0x0800);
 538         PHY_CLRBIT(sc, 4, 0x0800);
 539         PHY_WRITE(sc, 31, 0x0000);
 540 #else
 541         (void)val;
 542         PHY_WRITE(sc, 0x1f, 0x0001);
 543         PHY_WRITE(sc, 0x15, 0x1000);
 544         PHY_WRITE(sc, 0x18, 0x65c7);
 545         PHY_WRITE(sc, 0x04, 0x0000);
 546         PHY_WRITE(sc, 0x03, 0x00a1);
 547         PHY_WRITE(sc, 0x02, 0x0008);
 548         PHY_WRITE(sc, 0x01, 0x1020);
 549         PHY_WRITE(sc, 0x00, 0x1000);
 550         PHY_WRITE(sc, 0x04, 0x0800);
 551         PHY_WRITE(sc, 0x04, 0x0000);
 552         PHY_WRITE(sc, 0x04, 0x7000);
 553         PHY_WRITE(sc, 0x03, 0xff41);
 554         PHY_WRITE(sc, 0x02, 0xde60);
 555         PHY_WRITE(sc, 0x01, 0x0140);
 556         PHY_WRITE(sc, 0x00, 0x0077);
 557         PHY_WRITE(sc, 0x04, 0x7800);
 558         PHY_WRITE(sc, 0x04, 0x7000);
 559         PHY_WRITE(sc, 0x04, 0xa000);
 560         PHY_WRITE(sc, 0x03, 0xdf01);
 561         PHY_WRITE(sc, 0x02, 0xdf20);
 562         PHY_WRITE(sc, 0x01, 0xff95);
 563         PHY_WRITE(sc, 0x00, 0xfa00);
 564         PHY_WRITE(sc, 0x04, 0xa800);
 565         PHY_WRITE(sc, 0x04, 0xa000);
 566         PHY_WRITE(sc, 0x04, 0xb000);
 567         PHY_WRITE(sc, 0x0e, 0xff41);
 568         PHY_WRITE(sc, 0x02, 0xde20);
 569         PHY_WRITE(sc, 0x01, 0x0140);
 570         PHY_WRITE(sc, 0x00, 0x00bb);
 571         PHY_WRITE(sc, 0x04, 0xb800);
 572         PHY_WRITE(sc, 0x04, 0xb000);
 573         PHY_WRITE(sc, 0x04, 0xf000);
 574         PHY_WRITE(sc, 0x03, 0xdf01);
 575         PHY_WRITE(sc, 0x02, 0xdf20);
 576         PHY_WRITE(sc, 0x01, 0xff95);
 577         PHY_WRITE(sc, 0x00, 0xbf00);
 578         PHY_WRITE(sc, 0x04, 0xf800);
 579         PHY_WRITE(sc, 0x04, 0xf000);
 580         PHY_WRITE(sc, 0x04, 0x0000);
 581         PHY_WRITE(sc, 0x1f, 0x0000);
 582         PHY_WRITE(sc, 0x0b, 0x0000);
 583
 584 #endif
 585
 586         DELAY(40);
 587 }
 588
 589 static void
 590 rgephy_reset(struct mii_softc *sc)
 591 {
 592         struct rgephy_softc *rsc;
 593         uint16_t ssr;
 594
 595         mii_phy_reset(sc);
 596         DELAY(1000);
 597
 598         rsc = (struct rgephy_softc *)sc;
 599         if (rsc->mii_revision < 2) {
 600                 rgephy_load_dspcode(sc);
 601         } else if (rsc->mii_revision == 3) {
 602                 /* RTL8211C(L) */
 603                 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
 604                 if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
 605                         ssr &= ~RGEPHY_SSR_ALDPS;
 606                         PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
 607                 }
 608         } else {
 609                 PHY_WRITE(sc, 0x1F, 0x0000);
 610                 PHY_WRITE(sc, 0x0e, 0x0000);
 611         }
 612
 613         /* Reset capabilities */
 614         /* Step1: write our capability */
 615         /* 10/100 capability */
 616         PHY_WRITE(sc, RGEPHY_MII_ANAR,
 617             RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
 618             RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10 | ANAR_CSMA);
 619         /* 1000 capability */
 620         PHY_WRITE(sc, RGEPHY_MII_1000CTL,
 621             RGEPHY_1000CTL_AFD | RGEPHY_1000CTL_AHD);
 622
 623         /* Step2: Restart NWay */
 624         /* NWay enable and Restart NWay */
 625         PHY_WRITE(sc, RGEPHY_MII_BMCR,
 626             RGEPHY_BMCR_RESET | RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
 627 }