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[netbsd-mini2440.git] / sys / dev / pci / cs4280.c
blob5bbadc5a2b1c508be8f02696221a3c462cae9757
1 /* $NetBSD: cs4280.c,v 1.55 2009/11/26 15:17:09 njoly Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Tatoku Ogaito
17 * for the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Cirrus Logic CS4280 (and maybe CS461x) driver.
35 * Data sheets can be found
36 * http://www.cirrus.com/ftp/pubs/4280.pdf
37 * http://www.cirrus.com/ftp/pubs/4297.pdf
38 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf
39 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc
40 *
41 * Note: CS4610/CS4611 + CS423x ISA codec should be worked with
42 * wss* at pnpbios?
43 * or
44 * sb* at pnpbios?
45 * Since I could not find any documents on handling ISA codec,
46 * clcs does not support those chips.
47 */
48
49 /*
50 * TODO
51 * Joystick support
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: cs4280.c,v 1.55 2009/11/26 15:17:09 njoly Exp $");
56
57 #include "midi.h"
58
59 #include <sys/param.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/fcntl.h>
63 #include <sys/malloc.h>
64 #include <sys/device.h>
65 #include <sys/proc.h>
66 #include <sys/systm.h>
67
68 #include <dev/pci/pcidevs.h>
69 #include <dev/pci/pcivar.h>
70 #include <dev/pci/cs4280reg.h>
71 #include <dev/pci/cs4280_image.h>
72 #include <dev/pci/cs428xreg.h>
73
74 #include <sys/audioio.h>
75 #include <dev/audio_if.h>
76 #include <dev/midi_if.h>
77 #include <dev/mulaw.h>
78 #include <dev/auconv.h>
79
80 #include <dev/ic/ac97reg.h>
81 #include <dev/ic/ac97var.h>
82
83 #include <dev/pci/cs428x.h>
84
85 #include <sys/bus.h>
86 #include <sys/bswap.h>
87
88 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r))
89 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x))
90
91 /* IF functions for audio driver */
92 static int cs4280_match(device_t, cfdata_t, void *);
93 static void cs4280_attach(device_t, device_t, void *);
94 static int cs4280_intr(void *);
95 static int cs4280_query_encoding(void *, struct audio_encoding *);
96 static int cs4280_set_params(void *, int, int, audio_params_t *,
97 audio_params_t *, stream_filter_list_t *,
98 stream_filter_list_t *);
99 static int cs4280_halt_output(void *);
100 static int cs4280_halt_input(void *);
101 static int cs4280_getdev(void *, struct audio_device *);
102 static int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *),
103 void *, const audio_params_t *);
104 static int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *),
105 void *, const audio_params_t *);
106 static int cs4280_read_codec(void *, u_int8_t, u_int16_t *);
107 static int cs4280_write_codec(void *, u_int8_t, u_int16_t);
108 #if 0
109 static int cs4280_reset_codec(void *);
110 #endif
111 static enum ac97_host_flags cs4280_flags_codec(void *);
112
113 static bool cs4280_resume(device_t, pmf_qual_t);
114 static bool cs4280_suspend(device_t, pmf_qual_t);
115
116 /* Internal functions */
117 static const struct cs4280_card_t * cs4280_identify_card(struct pci_attach_args *);
118 static int cs4280_piix4_match(struct pci_attach_args *);
119 static void cs4280_clkrun_hack(struct cs428x_softc *, int);
120 static void cs4280_clkrun_hack_init(struct cs428x_softc *);
121 static void cs4280_set_adc_rate(struct cs428x_softc *, int );
122 static void cs4280_set_dac_rate(struct cs428x_softc *, int );
123 static int cs4280_download(struct cs428x_softc *, const uint32_t *, uint32_t,
124 uint32_t);
125 static int cs4280_download_image(struct cs428x_softc *);
126 static void cs4280_reset(void *);
127 static int cs4280_init(struct cs428x_softc *, int);
128 static void cs4280_clear_fifos(struct cs428x_softc *);
129
130 #if CS4280_DEBUG > 10
131 /* Thease two function is only for checking image loading is succeeded or not. */
132 static int cs4280_check_images(struct cs428x_softc *);
133 static int cs4280_checkimage(struct cs428x_softc *, uint32_t *, uint32_t,
134 uint32_t);
135 #endif
136
137 /* Special cards */
138 struct cs4280_card_t
139 {
140 pcireg_t id;
141 enum cs428x_flags flags;
142 };
143
144 #define _card(vend, prod, flags) \
145 {PCI_ID_CODE(vend, prod), flags}
146
147 static const struct cs4280_card_t cs4280_cards[] = {
148 #if 0 /* untested, from ALSA driver */
149 _card(PCI_VENDOR_MITAC, PCI_PRODUCT_MITAC_MI6020,
150 CS428X_FLAG_INVAC97EAMP),
151 #endif
152 _card(PCI_VENDOR_TURTLE_BEACH, PCI_PRODUCT_TURTLE_BEACH_SANTA_CRUZ,
153 CS428X_FLAG_INVAC97EAMP),
154 _card(PCI_VENDOR_IBM, PCI_PRODUCT_IBM_TPAUDIO,
155 CS428X_FLAG_CLKRUNHACK)
156 };
157
158 #undef _card
159
160 #define CS4280_CARDS_SIZE (sizeof(cs4280_cards)/sizeof(cs4280_cards[0]))
161
162 static const struct audio_hw_if cs4280_hw_if = {
163 NULL, /* open */
164 NULL, /* close */
165 NULL,
166 cs4280_query_encoding,
167 cs4280_set_params,
168 cs428x_round_blocksize,
169 NULL,
170 NULL,
171 NULL,
172 NULL,
173 NULL,
174 cs4280_halt_output,
175 cs4280_halt_input,
176 NULL,
177 cs4280_getdev,
178 NULL,
179 cs428x_mixer_set_port,
180 cs428x_mixer_get_port,
181 cs428x_query_devinfo,
182 cs428x_malloc,
183 cs428x_free,
184 cs428x_round_buffersize,
185 cs428x_mappage,
186 cs428x_get_props,
187 cs4280_trigger_output,
188 cs4280_trigger_input,
189 NULL,
190 NULL,
191 };
192
193 #if NMIDI > 0
194 /* Midi Interface */
195 static int cs4280_midi_open(void *, int, void (*)(void *, int),
196 void (*)(void *), void *);
197 static void cs4280_midi_close(void*);
198 static int cs4280_midi_output(void *, int);
199 static void cs4280_midi_getinfo(void *, struct midi_info *);
200
201 static const struct midi_hw_if cs4280_midi_hw_if = {
202 cs4280_midi_open,
203 cs4280_midi_close,
204 cs4280_midi_output,
205 cs4280_midi_getinfo,
206 0,
207 };
208 #endif
209
210 CFATTACH_DECL(clcs, sizeof(struct cs428x_softc),
211 cs4280_match, cs4280_attach, NULL, NULL);
212
213 static struct audio_device cs4280_device = {
214 "CS4280",
215 "",
216 "cs4280"
217 };
218
219
220 static int
221 cs4280_match(device_t parent, cfdata_t match, void *aux)
222 {
223 struct pci_attach_args *pa;
224
225 pa = (struct pci_attach_args *)aux;
226 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS)
227 return 0;
228 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4280
229 #if 0 /* I can't confirm */
230 || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CIRRUS_CS4610
231 #endif
232 )
233 return 1;
234 return 0;
235 }
236
237 static void
238 cs4280_attach(device_t parent, device_t self, void *aux)
239 {
240 struct cs428x_softc *sc;
241 struct pci_attach_args *pa;
242 pci_chipset_tag_t pc;
243 const struct cs4280_card_t *cs_card;
244 char const *intrstr;
245 pcireg_t reg;
246 char devinfo[256];
247 uint32_t mem;
248 int error;
249
250 sc = device_private(self);
251 pa = (struct pci_attach_args *)aux;
252 pc = pa->pa_pc;
253 aprint_naive(": Audio controller\n");
254
255 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
256 aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
257 PCI_REVISION(pa->pa_class));
258
259 cs_card = cs4280_identify_card(pa);
260 if (cs_card != NULL) {
261 aprint_normal_dev(&sc->sc_dev, "%s %s\n",
262 pci_findvendor(cs_card->id),
263 pci_findproduct(cs_card->id));
264 sc->sc_flags = cs_card->flags;
265 } else {
266 sc->sc_flags = CS428X_FLAG_NONE;
267 }
268
269 sc->sc_pc = pa->pa_pc;
270 sc->sc_pt = pa->pa_tag;
271
272 /* Map I/O register */
273 if (pci_mapreg_map(pa, PCI_BA0,
274 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
275 &sc->ba0t, &sc->ba0h, NULL, NULL)) {
276 aprint_error_dev(&sc->sc_dev, "can't map BA0 space\n");
277 return;
278 }
279 if (pci_mapreg_map(pa, PCI_BA1,
280 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
281 &sc->ba1t, &sc->ba1h, NULL, NULL)) {
282 aprint_error_dev(&sc->sc_dev, "can't map BA1 space\n");
283 return;
284 }
285
286 sc->sc_dmatag = pa->pa_dmat;
287
288 /* power up chip */
289 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
290 pci_activate_null)) && error != EOPNOTSUPP) {
291 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error);
292 return;
293 }
294
295 /* Enable the device (set bus master flag) */
296 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
297 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
298 reg | PCI_COMMAND_MASTER_ENABLE);
299
300 /* LATENCY_TIMER setting */
301 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
302 if ( PCI_LATTIMER(mem) < 32 ) {
303 mem &= 0xffff00ff;
304 mem |= 0x00002000;
305 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem);
306 }
307
308 /* CLKRUN hack initialization */
309 cs4280_clkrun_hack_init(sc);
310
311 /* Map and establish the interrupt. */
312 if (pci_intr_map(pa, &sc->intrh)) {
313 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n");
314 return;
315 }
316 intrstr = pci_intr_string(pc, sc->intrh);
317
318 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->intrh, IPL_AUDIO,
319 cs4280_intr, sc);
320 if (sc->sc_ih == NULL) {
321 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt");
322 if (intrstr != NULL)
323 aprint_error(" at %s", intrstr);
324 aprint_error("\n");
325 return;
326 }
327 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr);
328
329 /* Initialization */
330 if(cs4280_init(sc, 1) != 0)
331 return;
332
333 sc->type = TYPE_CS4280;
334 sc->halt_input = cs4280_halt_input;
335 sc->halt_output = cs4280_halt_output;
336
337 /* setup buffer related parameters */
338 sc->dma_size = CS4280_DCHUNK;
339 sc->dma_align = CS4280_DALIGN;
340 sc->hw_blocksize = CS4280_ICHUNK;
341
342 /* AC 97 attachment */
343 sc->host_if.arg = sc;
344 sc->host_if.attach = cs428x_attach_codec;
345 sc->host_if.read = cs4280_read_codec;
346 sc->host_if.write = cs4280_write_codec;
347 #if 0
348 sc->host_if.reset = cs4280_reset_codec;
349 #else
350 sc->host_if.reset = NULL;
351 #endif
352 sc->host_if.flags = cs4280_flags_codec;
353 if (ac97_attach(&sc->host_if, self) != 0) {
354 aprint_error_dev(&sc->sc_dev, "ac97_attach failed\n");
355 return;
356 }
357
358 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev);
359
360 #if NMIDI > 0
361 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev);
362 #endif
363
364 if (!pmf_device_register(self, cs4280_suspend, cs4280_resume))
365 aprint_error_dev(self, "couldn't establish power handler\n");
366 }
367
368 /* Interrupt handling function */
369 static int
370 cs4280_intr(void *p)
371 {
372 /*
373 * XXX
374 *
375 * Since CS4280 has only 4kB DMA buffer and
376 * interrupt occurs every 2kB block, I create dummy buffer
377 * which returns to audio driver and actual DMA buffer
378 * using in DMA transfer.
379 *
380 *
381 * ring buffer in audio.c is pointed by BUFADDR
382 * <------ ring buffer size == 64kB ------>
383 * <-----> blksize == 2048*(sc->sc_[pr]count) kB
384 * |= = = =|= = = =|= = = =|= = = =|= = = =|
385 * | | | | | | <- call audio_intp every
386 * sc->sc_[pr]_count time.
387 *
388 * actual DMA buffer is pointed by KERNADDR
389 * <-> DMA buffer size = 4kB
390 * |= =|
391 *
392 *
393 */
394 struct cs428x_softc *sc;
395 uint32_t intr, mem;
396 char * empty_dma;
397 int handled;
398
399 sc = p;
400 handled = 0;
401 /* grab interrupt register then clear it */
402 intr = BA0READ4(sc, CS4280_HISR);
403 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV);
404
405 /* not for us ? */
406 if ((intr & HISR_INTENA) == 0)
407 return 0;
408
409 /* Playback Interrupt */
410 if (intr & HISR_PINT) {
411 handled = 1;
412 mem = BA1READ4(sc, CS4280_PFIE);
413 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE);
414 if (sc->sc_prun) {
415 if ((sc->sc_pi%sc->sc_pcount) == 0)
416 sc->sc_pintr(sc->sc_parg);
417 /* copy buffer */
418 ++sc->sc_pi;
419 empty_dma = sc->sc_pdma->addr;
420 if (sc->sc_pi&1)
421 empty_dma += sc->hw_blocksize;
422 memcpy(empty_dma, sc->sc_pn, sc->hw_blocksize);
423 sc->sc_pn += sc->hw_blocksize;
424 if (sc->sc_pn >= sc->sc_pe)
425 sc->sc_pn = sc->sc_ps;
426 } else {
427 aprint_error_dev(&sc->sc_dev, "unexpected play intr\n");
428 }
429 BA1WRITE4(sc, CS4280_PFIE, mem);
430 }
431 /* Capture Interrupt */
432 if (intr & HISR_CINT) {
433 int i;
434 int16_t rdata;
435
436 handled = 1;
437 mem = BA1READ4(sc, CS4280_CIE);
438 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE);
439
440 if (sc->sc_rrun) {
441 ++sc->sc_ri;
442 empty_dma = sc->sc_rdma->addr;
443 if ((sc->sc_ri&1) == 0)
444 empty_dma += sc->hw_blocksize;
445
446 /*
447 * XXX
448 * I think this audio data conversion should be
449 * happend in upper layer, but I put this here
450 * since there is no conversion function available.
451 */
452 switch(sc->sc_rparam) {
453 case CF_16BIT_STEREO:
454 /* just copy it */
455 memcpy(sc->sc_rn, empty_dma, sc->hw_blocksize);
456 sc->sc_rn += sc->hw_blocksize;
457 break;
458 case CF_16BIT_MONO:
459 for (i = 0; i < 512; i++) {
460 rdata = *((int16_t *)empty_dma)>>1;
461 empty_dma += 2;
462 rdata += *((int16_t *)empty_dma)>>1;
463 empty_dma += 2;
464 *((int16_t *)sc->sc_rn) = rdata;
465 sc->sc_rn += 2;
466 }
467 break;
468 case CF_8BIT_STEREO:
469 for (i = 0; i < 512; i++) {
470 rdata = *((int16_t*)empty_dma);
471 empty_dma += 2;
472 *sc->sc_rn++ = rdata >> 8;
473 rdata = *((int16_t*)empty_dma);
474 empty_dma += 2;
475 *sc->sc_rn++ = rdata >> 8;
476 }
477 break;
478 case CF_8BIT_MONO:
479 for (i = 0; i < 512; i++) {
480 rdata = *((int16_t*)empty_dma) >>1;
481 empty_dma += 2;
482 rdata += *((int16_t*)empty_dma) >>1;
483 empty_dma += 2;
484 *sc->sc_rn++ = rdata >>8;
485 }
486 break;
487 default:
488 /* Should not reach here */
489 aprint_error_dev(&sc->sc_dev,
490 "unknown sc->sc_rparam: %d\n",
491 sc->sc_rparam);
492 }
493 if (sc->sc_rn >= sc->sc_re)
494 sc->sc_rn = sc->sc_rs;
495 }
496 BA1WRITE4(sc, CS4280_CIE, mem);
497
498 if (sc->sc_rrun) {
499 if ((sc->sc_ri%(sc->sc_rcount)) == 0)
500 sc->sc_rintr(sc->sc_rarg);
501 } else {
502 aprint_error_dev(&sc->sc_dev,
503 "unexpected record intr\n");
504 }
505 }
506
507 #if NMIDI > 0
508 /* Midi port Interrupt */
509 if (intr & HISR_MIDI) {
510 int data;
511
512 handled = 1;
513 DPRINTF(("i: %d: ",
514 BA0READ4(sc, CS4280_MIDSR)));
515 /* Read the received data */
516 while ((sc->sc_iintr != NULL) &&
517 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) {
518 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK;
519 DPRINTF(("r:%x\n",data));
520 sc->sc_iintr(sc->sc_arg, data);
521 }
522
523 /* Write the data */
524 #if 1
525 /* XXX:
526 * It seems "Transmit Buffer Full" never activate until EOI
527 * is deliverd. Shall I throw EOI top of this routine ?
528 */
529 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
530 DPRINTF(("w: "));
531 if (sc->sc_ointr != NULL)
532 sc->sc_ointr(sc->sc_arg);
533 }
534 #else
535 while ((sc->sc_ointr != NULL) &&
536 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) {
537 DPRINTF(("w: "));
538 sc->sc_ointr(sc->sc_arg);
539 }
540 #endif
541 DPRINTF(("\n"));
542 }
543 #endif
544
545 return handled;
546 }
547
548 static int
549 cs4280_query_encoding(void *addr, struct audio_encoding *fp)
550 {
551 switch (fp->index) {
552 case 0:
553 strcpy(fp->name, AudioEulinear);
554 fp->encoding = AUDIO_ENCODING_ULINEAR;
555 fp->precision = 8;
556 fp->flags = 0;
557 break;
558 case 1:
559 strcpy(fp->name, AudioEmulaw);
560 fp->encoding = AUDIO_ENCODING_ULAW;
561 fp->precision = 8;
562 fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
563 break;
564 case 2:
565 strcpy(fp->name, AudioEalaw);
566 fp->encoding = AUDIO_ENCODING_ALAW;
567 fp->precision = 8;
568 fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
569 break;
570 case 3:
571 strcpy(fp->name, AudioEslinear);
572 fp->encoding = AUDIO_ENCODING_SLINEAR;
573 fp->precision = 8;
574 fp->flags = 0;
575 break;
576 case 4:
577 strcpy(fp->name, AudioEslinear_le);
578 fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
579 fp->precision = 16;
580 fp->flags = 0;
581 break;
582 case 5:
583 strcpy(fp->name, AudioEulinear_le);
584 fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
585 fp->precision = 16;
586 fp->flags = 0;
587 break;
588 case 6:
589 strcpy(fp->name, AudioEslinear_be);
590 fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
591 fp->precision = 16;
592 fp->flags = 0;
593 break;
594 case 7:
595 strcpy(fp->name, AudioEulinear_be);
596 fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
597 fp->precision = 16;
598 fp->flags = 0;
599 break;
600 default:
601 return EINVAL;
602 }
603 return 0;
604 }
605
606 static int
607 cs4280_set_params(void *addr, int setmode, int usemode,
608 audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil,
609 stream_filter_list_t *rfil)
610 {
611 audio_params_t hw;
612 struct cs428x_softc *sc;
613 struct audio_params *p;
614 stream_filter_list_t *fil;
615 int mode;
616
617 sc = addr;
618 for (mode = AUMODE_RECORD; mode != -1;
619 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) {
620 if ((setmode & mode) == 0)
621 continue;
622
623 p = mode == AUMODE_PLAY ? play : rec;
624
625 if (p == play) {
626 DPRINTFN(5,("play: sample=%d precision=%d channels=%d\n",
627 p->sample_rate, p->precision, p->channels));
628 /* play back data format may be 8- or 16-bit and
629 * either stereo or mono.
630 * playback rate may range from 8000Hz to 48000Hz
631 */
632 if (p->sample_rate < 8000 || p->sample_rate > 48000 ||
633 (p->precision != 8 && p->precision != 16) ||
634 (p->channels != 1 && p->channels != 2) ) {
635 return EINVAL;
636 }
637 } else {
638 DPRINTFN(5,("rec: sample=%d precision=%d channels=%d\n",
639 p->sample_rate, p->precision, p->channels));
640 /* capture data format must be 16bit stereo
641 * and sample rate range from 11025Hz to 48000Hz.
642 *
643 * XXX: it looks like to work with 8000Hz,
644 * although data sheets say lower limit is
645 * 11025 Hz.
646 */
647
648 if (p->sample_rate < 8000 || p->sample_rate > 48000 ||
649 (p->precision != 8 && p->precision != 16) ||
650 (p->channels != 1 && p->channels != 2) ) {
651 return EINVAL;
652 }
653 }
654 fil = mode == AUMODE_PLAY ? pfil : rfil;
655 hw = *p;
656 hw.encoding = AUDIO_ENCODING_SLINEAR_LE;
657
658 /* capturing data is slinear */
659 switch (p->encoding) {
660 case AUDIO_ENCODING_SLINEAR_BE:
661 if (mode == AUMODE_RECORD && p->precision == 16) {
662 fil->append(fil, swap_bytes, &hw);
663 }
664 break;
665 case AUDIO_ENCODING_SLINEAR_LE:
666 break;
667 case AUDIO_ENCODING_ULINEAR_BE:
668 if (mode == AUMODE_RECORD) {
669 fil->append(fil, p->precision == 16
670 ? swap_bytes_change_sign16
671 : change_sign8, &hw);
672 }
673 break;
674 case AUDIO_ENCODING_ULINEAR_LE:
675 if (mode == AUMODE_RECORD) {
676 fil->append(fil, p->precision == 16
677 ? change_sign16 : change_sign8,
678 &hw);
679 }
680 break;
681 case AUDIO_ENCODING_ULAW:
682 if (mode == AUMODE_PLAY) {
683 hw.precision = 16;
684 hw.validbits = 16;
685 fil->append(fil, mulaw_to_linear16, &hw);
686 } else {
687 fil->append(fil, linear8_to_mulaw, &hw);
688 }
689 break;
690 case AUDIO_ENCODING_ALAW:
691 if (mode == AUMODE_PLAY) {
692 hw.precision = 16;
693 hw.validbits = 16;
694 fil->append(fil, alaw_to_linear16, &hw);
695 } else {
696 fil->append(fil, linear8_to_alaw, &hw);
697 }
698 break;
699 default:
700 return EINVAL;
701 }
702 }
703
704 /* set sample rate */
705 cs4280_set_dac_rate(sc, play->sample_rate);
706 cs4280_set_adc_rate(sc, rec->sample_rate);
707 return 0;
708 }
709
710 static int
711 cs4280_halt_output(void *addr)
712 {
713 struct cs428x_softc *sc;
714 uint32_t mem;
715
716 sc = addr;
717 mem = BA1READ4(sc, CS4280_PCTL);
718 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
719 sc->sc_prun = 0;
720 cs4280_clkrun_hack(sc, -1);
721
722 return 0;
723 }
724
725 static int
726 cs4280_halt_input(void *addr)
727 {
728 struct cs428x_softc *sc;
729 uint32_t mem;
730
731 sc = addr;
732 mem = BA1READ4(sc, CS4280_CCTL);
733 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
734 sc->sc_rrun = 0;
735 cs4280_clkrun_hack(sc, -1);
736
737 return 0;
738 }
739
740 static int
741 cs4280_getdev(void *addr, struct audio_device *retp)
742 {
743
744 *retp = cs4280_device;
745 return 0;
746 }
747
748 static int
749 cs4280_trigger_output(void *addr, void *start, void *end, int blksize,
750 void (*intr)(void *), void *arg,
751 const audio_params_t *param)
752 {
753 struct cs428x_softc *sc;
754 uint32_t pfie, pctl, pdtc;
755 struct cs428x_dma *p;
756
757 sc = addr;
758 #ifdef DIAGNOSTIC
759 if (sc->sc_prun)
760 printf("cs4280_trigger_output: already running\n");
761 #endif
762 sc->sc_prun = 1;
763 cs4280_clkrun_hack(sc, 1);
764
765 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p "
766 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
767 sc->sc_pintr = intr;
768 sc->sc_parg = arg;
769
770 /* stop playback DMA */
771 BA1WRITE4(sc, CS4280_PCTL, BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK);
772
773 /* setup PDTC */
774 pdtc = BA1READ4(sc, CS4280_PDTC);
775 pdtc &= ~PDTC_MASK;
776 pdtc |= CS4280_MK_PDTC(param->precision * param->channels);
777 BA1WRITE4(sc, CS4280_PDTC, pdtc);
778
779 DPRINTF(("param: precision=%d channels=%d encoding=%d\n",
780 param->precision, param->channels, param->encoding));
781 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next)
782 continue;
783 if (p == NULL) {
784 printf("cs4280_trigger_output: bad addr %p\n", start);
785 return EINVAL;
786 }
787 if (DMAADDR(p) % sc->dma_align != 0 ) {
788 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start"
789 "4kB align\n", (ulong)DMAADDR(p));
790 return EINVAL;
791 }
792
793 sc->sc_pcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/
794 sc->sc_ps = (char *)start;
795 sc->sc_pe = (char *)end;
796 sc->sc_pdma = p;
797 sc->sc_pbuf = KERNADDR(p);
798 sc->sc_pi = 0;
799 sc->sc_pn = sc->sc_ps;
800 if (blksize >= sc->dma_size) {
801 sc->sc_pn = sc->sc_ps + sc->dma_size;
802 memcpy(sc->sc_pbuf, start, sc->dma_size);
803 ++sc->sc_pi;
804 } else {
805 sc->sc_pn = sc->sc_ps + sc->hw_blocksize;
806 memcpy(sc->sc_pbuf, start, sc->hw_blocksize);
807 }
808
809 /* initiate playback DMA */
810 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p));
811
812 /* set PFIE */
813 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK;
814
815 if (param->precision == 8)
816 pfie |= PFIE_8BIT;
817 if (param->channels == 1)
818 pfie |= PFIE_MONO;
819
820 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
821 param->encoding == AUDIO_ENCODING_SLINEAR_BE)
822 pfie |= PFIE_SWAPPED;
823 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
824 param->encoding == AUDIO_ENCODING_ULINEAR_LE)
825 pfie |= PFIE_UNSIGNED;
826
827 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE);
828
829 sc->sc_prate = param->sample_rate;
830 cs4280_set_dac_rate(sc, param->sample_rate);
831
832 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK;
833 pctl |= sc->pctl;
834 BA1WRITE4(sc, CS4280_PCTL, pctl);
835 return 0;
836 }
837
838 static int
839 cs4280_trigger_input(void *addr, void *start, void *end, int blksize,
840 void (*intr)(void *), void *arg,
841 const audio_params_t *param)
842 {
843 struct cs428x_softc *sc;
844 uint32_t cctl, cie;
845 struct cs428x_dma *p;
846
847 sc = addr;
848 #ifdef DIAGNOSTIC
849 if (sc->sc_rrun)
850 printf("cs4280_trigger_input: already running\n");
851 #endif
852 sc->sc_rrun = 1;
853 cs4280_clkrun_hack(sc, 1);
854
855 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p "
856 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
857 sc->sc_rintr = intr;
858 sc->sc_rarg = arg;
859
860 /* stop capture DMA */
861 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK);
862
863 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next)
864 continue;
865 if (p == NULL) {
866 printf("cs4280_trigger_input: bad addr %p\n", start);
867 return EINVAL;
868 }
869 if (DMAADDR(p) % sc->dma_align != 0) {
870 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start"
871 "4kB align\n", (ulong)DMAADDR(p));
872 return EINVAL;
873 }
874
875 sc->sc_rcount = blksize / sc->hw_blocksize; /* sc->hw_blocksize is fixed hardware blksize*/
876 sc->sc_rs = (char *)start;
877 sc->sc_re = (char *)end;
878 sc->sc_rdma = p;
879 sc->sc_rbuf = KERNADDR(p);
880 sc->sc_ri = 0;
881 sc->sc_rn = sc->sc_rs;
882
883 /* initiate capture DMA */
884 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p));
885
886 /* setup format information for internal converter */
887 sc->sc_rparam = 0;
888 if (param->precision == 8) {
889 sc->sc_rparam += CF_8BIT;
890 sc->sc_rcount <<= 1;
891 }
892 if (param->channels == 1) {
893 sc->sc_rparam += CF_MONO;
894 sc->sc_rcount <<= 1;
895 }
896
897 /* set CIE */
898 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
899 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE);
900
901 sc->sc_rrate = param->sample_rate;
902 cs4280_set_adc_rate(sc, param->sample_rate);
903
904 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK;
905 cctl |= sc->cctl;
906 BA1WRITE4(sc, CS4280_CCTL, cctl);
907 return 0;
908 }
909
910 static bool
911 cs4280_suspend(device_t dv, pmf_qual_t qual)
912 {
913 struct cs428x_softc *sc = device_private(dv);
914
915 if (sc->sc_prun) {
916 sc->sc_suspend_state.cs4280.pctl = BA1READ4(sc, CS4280_PCTL);
917 sc->sc_suspend_state.cs4280.pfie = BA1READ4(sc, CS4280_PFIE);
918 sc->sc_suspend_state.cs4280.pba = BA1READ4(sc, CS4280_PBA);
919 sc->sc_suspend_state.cs4280.pdtc = BA1READ4(sc, CS4280_PDTC);
920 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n",
921 sc->sc_suspend_state.cs4280.pctl,
922 sc->sc_suspend_state.cs4280.pfie,
923 sc->sc_suspend_state.cs4280.pba,
924 sc->sc_suspend_state.cs4280.pdtc));
925 }
926
927 /* save current capture status */
928 if (sc->sc_rrun) {
929 sc->sc_suspend_state.cs4280.cctl = BA1READ4(sc, CS4280_CCTL);
930 sc->sc_suspend_state.cs4280.cie = BA1READ4(sc, CS4280_CIE);
931 sc->sc_suspend_state.cs4280.cba = BA1READ4(sc, CS4280_CBA);
932 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n",
933 sc->sc_suspend_state.cs4280.cctl,
934 sc->sc_suspend_state.cs4280.cie,
935 sc->sc_suspend_state.cs4280.cba));
936 }
937
938 /* Stop DMA */
939 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl & ~PCTL_MASK);
940 BA1WRITE4(sc, CS4280_CCTL, BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK);
941
942 return true;
943 }
944
945 static bool
946 cs4280_resume(device_t dv, pmf_qual_t qual)
947 {
948 struct cs428x_softc *sc = device_private(dv);
949
950 cs4280_init(sc, 0);
951 #if 0
952 cs4280_reset_codec(sc);
953 #endif
954 /* restore ac97 registers */
955 (*sc->codec_if->vtbl->restore_ports)(sc->codec_if);
956
957 /* restore DMA related status */
958 if(sc->sc_prun) {
959 DPRINTF(("pctl=0x%08x pfie=0x%08x pba=0x%08x pdtc=0x%08x\n",
960 sc->sc_suspend_state.cs4280.pctl,
961 sc->sc_suspend_state.cs4280.pfie,
962 sc->sc_suspend_state.cs4280.pba,
963 sc->sc_suspend_state.cs4280.pdtc));
964 cs4280_set_dac_rate(sc, sc->sc_prate);
965 BA1WRITE4(sc, CS4280_PDTC, sc->sc_suspend_state.cs4280.pdtc);
966 BA1WRITE4(sc, CS4280_PBA, sc->sc_suspend_state.cs4280.pba);
967 BA1WRITE4(sc, CS4280_PFIE, sc->sc_suspend_state.cs4280.pfie);
968 BA1WRITE4(sc, CS4280_PCTL, sc->sc_suspend_state.cs4280.pctl);
969 }
970
971 if (sc->sc_rrun) {
972 DPRINTF(("cctl=0x%08x cie=0x%08x cba=0x%08x\n",
973 sc->sc_suspend_state.cs4280.cctl,
974 sc->sc_suspend_state.cs4280.cie,
975 sc->sc_suspend_state.cs4280.cba));
976 cs4280_set_adc_rate(sc, sc->sc_rrate);
977 BA1WRITE4(sc, CS4280_CBA, sc->sc_suspend_state.cs4280.cba);
978 BA1WRITE4(sc, CS4280_CIE, sc->sc_suspend_state.cs4280.cie);
979 BA1WRITE4(sc, CS4280_CCTL, sc->sc_suspend_state.cs4280.cctl);
980 }
981
982 return true;
983 }
984
985 static int
986 cs4280_read_codec(void *addr, u_int8_t reg, u_int16_t *result)
987 {
988 struct cs428x_softc *sc = addr;
989 int rv;
990
991 cs4280_clkrun_hack(sc, 1);
992 rv = cs428x_read_codec(addr, reg, result);
993 cs4280_clkrun_hack(sc, -1);
994
995 return rv;
996 }
997
998 static int
999 cs4280_write_codec(void *addr, u_int8_t reg, u_int16_t data)
1000 {
1001 struct cs428x_softc *sc = addr;
1002 int rv;
1003
1004 cs4280_clkrun_hack(sc, 1);
1005 rv = cs428x_write_codec(addr, reg, data);
1006 cs4280_clkrun_hack(sc, -1);
1007
1008 return rv;
1009 }
1010
1011 #if 0 /* XXX buggy and not required */
1012 /* control AC97 codec */
1013 static int
1014 cs4280_reset_codec(void *addr)
1015 {
1016 struct cs428x_softc *sc;
1017 int n;
1018
1019 sc = addr;
1020
1021 /* Reset codec */
1022 BA0WRITE4(sc, CS428X_ACCTL, 0);
1023 delay(100); /* delay 100us */
1024 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN);
1025
1026 /*
1027 * It looks like we do the following procedure, too
1028 */
1029
1030 /* Enable AC-link sync generation */
1031 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
1032 delay(50*1000); /* XXX delay 50ms */
1033
1034 /* Assert valid frame signal */
1035 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1036
1037 /* Wait for valid AC97 input slot */
1038 n = 0;
1039 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) !=
1040 (ACISV_ISV3 | ACISV_ISV4)) {
1041 delay(1000);
1042 if (++n > 1000) {
1043 printf("reset_codec: AC97 inputs slot ready timeout\n");
1044 return ETIMEDOUT;
1045 }
1046 }
1047
1048 return 0;
1049 }
1050 #endif
1051
1052 static enum ac97_host_flags cs4280_flags_codec(void *addr)
1053 {
1054 struct cs428x_softc *sc;
1055
1056 sc = addr;
1057 if (sc->sc_flags & CS428X_FLAG_INVAC97EAMP)
1058 return AC97_HOST_INVERTED_EAMP;
1059
1060 return 0;
1061 }
1062
1063 /* Internal functions */
1064
1065 static const struct cs4280_card_t *
1066 cs4280_identify_card(struct pci_attach_args *pa)
1067 {
1068 pcireg_t idreg;
1069 u_int16_t i;
1070
1071 idreg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
1072 for (i = 0; i < CS4280_CARDS_SIZE; i++) {
1073 if (idreg == cs4280_cards[i].id)
1074 return &cs4280_cards[i];
1075 }
1076
1077 return NULL;
1078 }
1079
1080 static int
1081 cs4280_piix4_match(struct pci_attach_args *pa)
1082 {
1083 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
1084 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_82371AB_PMC) {
1085 return 1;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static void
1092 cs4280_clkrun_hack(struct cs428x_softc *sc, int change)
1093 {
1094 uint16_t control, val;
1095
1096 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK))
1097 return;
1098
1099 sc->sc_active += change;
1100 val = control = bus_space_read_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10);
1101 if (!sc->sc_active)
1102 val |= 0x2000;
1103 else
1104 val &= ~0x2000;
1105 if (val != control)
1106 bus_space_write_2(sc->sc_pm_iot, sc->sc_pm_ioh, 0x10, val);
1107 }
1108
1109 static void
1110 cs4280_clkrun_hack_init(struct cs428x_softc *sc)
1111 {
1112 struct pci_attach_args smbuspa;
1113 uint16_t reg;
1114 pcireg_t port;
1115
1116 if (!(sc->sc_flags & CS428X_FLAG_CLKRUNHACK))
1117 return;
1118
1119 if (pci_find_device(&smbuspa, cs4280_piix4_match)) {
1120 sc->sc_active = 0;
1121 aprint_normal_dev(&sc->sc_dev, "enabling CLKRUN hack\n");
1122
1123 reg = pci_conf_read(smbuspa.pa_pc, smbuspa.pa_tag, 0x40);
1124 port = reg & 0xffc0;
1125 aprint_normal_dev(&sc->sc_dev, "power management port 0x%x\n",
1126 port);
1127
1128 sc->sc_pm_iot = smbuspa.pa_iot;
1129 if (bus_space_map(sc->sc_pm_iot, port, 0x20 /* XXX */, 0,
1130 &sc->sc_pm_ioh) == 0)
1131 return;
1132 }
1133
1134 /* handle error */
1135 sc->sc_flags &= ~CS428X_FLAG_CLKRUNHACK;
1136 aprint_normal_dev(&sc->sc_dev, "disabling CLKRUN hack\n");
1137 }
1138
1139 static void
1140 cs4280_set_adc_rate(struct cs428x_softc *sc, int rate)
1141 {
1142 /* calculate capture rate:
1143 *
1144 * capture_coefficient_increment = -round(rate*128*65536/48000;
1145 * capture_phase_increment = floor(48000*65536*1024/rate);
1146 * cx = round(48000*65536*1024 - capture_phase_increment*rate);
1147 * cy = floor(cx/200);
1148 * capture_sample_rate_correction = cx - 200*cy;
1149 * capture_delay = ceil(24*48000/rate);
1150 * capture_num_triplets = floor(65536*rate/24000);
1151 * capture_group_length = 24000/GCD(rate, 24000);
1152 * where GCD means "Greatest Common Divisor".
1153 *
1154 * capture_coefficient_increment, capture_phase_increment and
1155 * capture_num_triplets are 32-bit signed quantities.
1156 * capture_sample_rate_correction and capture_group_length are
1157 * 16-bit signed quantities.
1158 * capture_delay is a 14-bit unsigned quantity.
1159 */
1160 uint32_t cci, cpi, cnt, cx, cy, tmp1;
1161 uint16_t csrc, cgl, cdlay;
1162
1163 /* XXX
1164 * Even though, embedded_audio_spec says capture rate range 11025 to
1165 * 48000, dhwiface.cpp says,
1166 *
1167 * "We can only decimate by up to a factor of 1/9th the hardware rate.
1168 * Return an error if an attempt is made to stray outside that limit."
1169 *
1170 * so assume range as 48000/9 to 48000
1171 */
1172
1173 if (rate < 8000)
1174 rate = 8000;
1175 if (rate > 48000)
1176 rate = 48000;
1177
1178 cx = rate << 16;
1179 cci = cx / 48000;
1180 cx -= cci * 48000;
1181 cx <<= 7;
1182 cci <<= 7;
1183 cci += cx / 48000;
1184 cci = - cci;
1185
1186 cx = 48000 << 16;
1187 cpi = cx / rate;
1188 cx -= cpi * rate;
1189 cx <<= 10;
1190 cpi <<= 10;
1191 cy = cx / rate;
1192 cpi += cy;
1193 cx -= cy * rate;
1194
1195 cy = cx / 200;
1196 csrc = cx - 200*cy;
1197
1198 cdlay = ((48000 * 24) + rate - 1) / rate;
1199 #if 0
1200 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */
1201 #endif
1202
1203 cnt = rate << 16;
1204 cnt /= 24000;
1205
1206 cgl = 1;
1207 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) {
1208 if (((rate / tmp1) * tmp1) != rate)
1209 cgl *= 2;
1210 }
1211 if (((rate / 3) * 3) != rate)
1212 cgl *= 3;
1213 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) {
1214 if (((rate / tmp1) * tmp1) != rate)
1215 cgl *= 5;
1216 }
1217 #if 0
1218 /* XXX what manual says */
1219 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK;
1220 tmp1 |= csrc<<16;
1221 BA1WRITE4(sc, CS4280_CSRC, tmp1);
1222 #else
1223 /* suggested by cs461x.c (ALSA driver) */
1224 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy));
1225 #endif
1226
1227 #if 0
1228 /* I am confused. The sample rate calculation section says
1229 * cci *is* 32-bit signed quantity but in the parameter description
1230 * section, CCI only assigned 16bit.
1231 * I believe size of the variable.
1232 */
1233 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK;
1234 tmp1 |= cci<<16;
1235 BA1WRITE4(sc, CS4280_CCI, tmp1);
1236 #else
1237 BA1WRITE4(sc, CS4280_CCI, cci);
1238 #endif
1239
1240 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK;
1241 tmp1 |= cdlay <<18;
1242 BA1WRITE4(sc, CS4280_CD, tmp1);
1243
1244 BA1WRITE4(sc, CS4280_CPI, cpi);
1245
1246 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK;
1247 tmp1 |= cgl;
1248 BA1WRITE4(sc, CS4280_CGL, tmp1);
1249
1250 BA1WRITE4(sc, CS4280_CNT, cnt);
1251
1252 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK;
1253 tmp1 |= cgl;
1254 BA1WRITE4(sc, CS4280_CGC, tmp1);
1255 }
1256
1257 static void
1258 cs4280_set_dac_rate(struct cs428x_softc *sc, int rate)
1259 {
1260 /*
1261 * playback rate may range from 8000Hz to 48000Hz
1262 *
1263 * play_phase_increment = floor(rate*65536*1024/48000)
1264 * px = round(rate*65536*1024 - play_phase_incremnt*48000)
1265 * py=floor(px/200)
1266 * play_sample_rate_correction = px - 200*py
1267 *
1268 * play_phase_increment is a 32bit signed quantity.
1269 * play_sample_rate_correction is a 16bit signed quantity.
1270 */
1271 int32_t ppi;
1272 int16_t psrc;
1273 uint32_t px, py;
1274
1275 if (rate < 8000)
1276 rate = 8000;
1277 if (rate > 48000)
1278 rate = 48000;
1279 px = rate << 16;
1280 ppi = px/48000;
1281 px -= ppi*48000;
1282 ppi <<= 10;
1283 px <<= 10;
1284 py = px / 48000;
1285 ppi += py;
1286 px -= py*48000;
1287 py = px/200;
1288 px -= py*200;
1289 psrc = px;
1290 #if 0
1291 /* what manual says */
1292 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK;
1293 BA1WRITE4(sc, CS4280_PSRC,
1294 ( ((psrc<<16) & PSRC_MASK) | px ));
1295 #else
1296 /* suggested by cs461x.c (ALSA driver) */
1297 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py));
1298 #endif
1299 BA1WRITE4(sc, CS4280_PPI, ppi);
1300 }
1301
1302 /* Download Processor Code and Data image */
1303 static int
1304 cs4280_download(struct cs428x_softc *sc, const uint32_t *src,
1305 uint32_t offset, uint32_t len)
1306 {
1307 uint32_t ctr;
1308 #if CS4280_DEBUG > 10
1309 uint32_t con, data;
1310 uint8_t c0, c1, c2, c3;
1311 #endif
1312 if ((offset & 3) || (len & 3))
1313 return -1;
1314
1315 len /= sizeof(uint32_t);
1316 for (ctr = 0; ctr < len; ctr++) {
1317 /* XXX:
1318 * I cannot confirm this is the right thing or not
1319 * on BIG-ENDIAN machines.
1320 */
1321 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr)));
1322 #if CS4280_DEBUG > 10
1323 data = htole32(*(src+ctr));
1324 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0);
1325 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1);
1326 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2);
1327 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3);
1328 con = (c3 << 24) | (c2 << 16) | (c1 << 8) | c0;
1329 if (data != con ) {
1330 printf("0x%06x: write=0x%08x read=0x%08x\n",
1331 offset+ctr*4, data, con);
1332 return -1;
1333 }
1334 #endif
1335 }
1336 return 0;
1337 }
1338
1339 static int
1340 cs4280_download_image(struct cs428x_softc *sc)
1341 {
1342 int idx, err;
1343 uint32_t offset = 0;
1344
1345 err = 0;
1346 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) {
1347 err = cs4280_download(sc, &BA1Struct.map[offset],
1348 BA1Struct.memory[idx].offset,
1349 BA1Struct.memory[idx].size);
1350 if (err != 0) {
1351 aprint_error_dev(&sc->sc_dev,
1352 "load_image failed at %d\n", idx);
1353 return -1;
1354 }
1355 offset += BA1Struct.memory[idx].size / sizeof(uint32_t);
1356 }
1357 return err;
1358 }
1359
1360 /* Processor Soft Reset */
1361 static void
1362 cs4280_reset(void *sc_)
1363 {
1364 struct cs428x_softc *sc;
1365
1366 sc = sc_;
1367 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */
1368 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP);
1369 delay(100);
1370 /* Clear RSTSP bit in SPCR */
1371 BA1WRITE4(sc, CS4280_SPCR, 0);
1372 /* enable DMA reqest */
1373 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN);
1374 }
1375
1376 static int
1377 cs4280_init(struct cs428x_softc *sc, int init)
1378 {
1379 int n;
1380 uint32_t mem;
1381 int rv;
1382
1383 rv = 1;
1384 cs4280_clkrun_hack(sc, 1);
1385
1386 /* Start PLL out in known state */
1387 BA0WRITE4(sc, CS4280_CLKCR1, 0);
1388 /* Start serial ports out in known state */
1389 BA0WRITE4(sc, CS4280_SERMC1, 0);
1390
1391 /* Specify type of CODEC */
1392 /* XXX should not be here */
1393 #define SERACC_CODEC_TYPE_1_03
1394 #ifdef SERACC_CODEC_TYPE_1_03
1395 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */
1396 #else
1397 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */
1398 #endif
1399
1400 /* Reset codec */
1401 BA0WRITE4(sc, CS428X_ACCTL, 0);
1402 delay(100); /* delay 100us */
1403 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_RSTN);
1404
1405 /* Enable AC-link sync generation */
1406 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
1407 delay(50*1000); /* delay 50ms */
1408
1409 /* Set the serial port timing configuration */
1410 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97);
1411
1412 /* Setup clock control */
1413 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE);
1414 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE);
1415 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8);
1416
1417 /* Power up the PLL */
1418 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP);
1419 delay(50*1000); /* delay 50ms */
1420
1421 /* Turn on clock */
1422 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE;
1423 BA0WRITE4(sc, CS4280_CLKCR1, mem);
1424
1425 /* Set the serial port FIFO pointer to the
1426 * first sample in FIFO. (not documented) */
1427 cs4280_clear_fifos(sc);
1428
1429 #if 0
1430 /* Set the serial port FIFO pointer to the first sample in the FIFO */
1431 BA0WRITE4(sc, CS4280_SERBSP, 0);
1432 #endif
1433
1434 /* Configure the serial port */
1435 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97);
1436 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97);
1437 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97);
1438
1439 /* Wait for CODEC ready */
1440 n = 0;
1441 while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
1442 delay(125);
1443 if (++n > 1000) {
1444 aprint_error_dev(&sc->sc_dev, "codec ready timeout\n");
1445 goto exit;
1446 }
1447 }
1448
1449 /* Assert valid frame signal */
1450 BA0WRITE4(sc, CS428X_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1451
1452 /* Wait for valid AC97 input slot */
1453 n = 0;
1454 while ((BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) !=
1455 (ACISV_ISV3 | ACISV_ISV4)) {
1456 delay(1000);
1457 if (++n > 1000) {
1458 printf("AC97 inputs slot ready timeout\n");
1459 goto exit;
1460 }
1461 }
1462
1463 /* Set AC97 output slot valid signals */
1464 BA0WRITE4(sc, CS428X_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
1465
1466 /* reset the processor */
1467 cs4280_reset(sc);
1468
1469 /* Download the image to the processor */
1470 if (cs4280_download_image(sc) != 0) {
1471 aprint_error_dev(&sc->sc_dev, "image download error\n");
1472 goto exit;
1473 }
1474
1475 /* Save playback parameter and then write zero.
1476 * this ensures that DMA doesn't immediately occur upon
1477 * starting the processor core
1478 */
1479 mem = BA1READ4(sc, CS4280_PCTL);
1480 sc->pctl = mem & PCTL_MASK; /* save startup value */
1481 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1482 if (init != 0)
1483 sc->sc_prun = 0;
1484
1485 /* Save capture parameter and then write zero.
1486 * this ensures that DMA doesn't immediately occur upon
1487 * starting the processor core
1488 */
1489 mem = BA1READ4(sc, CS4280_CCTL);
1490 sc->cctl = mem & CCTL_MASK; /* save startup value */
1491 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
1492 if (init != 0)
1493 sc->sc_rrun = 0;
1494
1495 /* Processor Startup Procedure */
1496 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV);
1497 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
1498
1499 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */
1500 n = 0;
1501 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) {
1502 delay(10);
1503 if (++n > 1000) {
1504 printf("SPCR 1->0 transition timeout\n");
1505 goto exit;
1506 }
1507 }
1508
1509 n = 0;
1510 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) {
1511 delay(10);
1512 if (++n > 1000) {
1513 printf("SPCS 0->1 transition timeout\n");
1514 goto exit;
1515 }
1516 }
1517 /* Processor is now running !!! */
1518
1519 /* Setup volume */
1520 BA1WRITE4(sc, CS4280_PVOL, 0x80008000);
1521 BA1WRITE4(sc, CS4280_CVOL, 0x80008000);
1522
1523 /* Interrupt enable */
1524 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM);
1525
1526 /* playback interrupt enable */
1527 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK;
1528 mem |= PFIE_PI_ENABLE;
1529 BA1WRITE4(sc, CS4280_PFIE, mem);
1530 /* capture interrupt enable */
1531 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
1532 mem |= CIE_CI_ENABLE;
1533 BA1WRITE4(sc, CS4280_CIE, mem);
1534
1535 #if NMIDI > 0
1536 /* Reset midi port */
1537 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
1538 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST);
1539 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
1540 /* midi interrupt enable */
1541 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE;
1542 BA0WRITE4(sc, CS4280_MIDCR, mem);
1543 #endif
1544
1545 rv = 0;
1546
1547 exit:
1548 cs4280_clkrun_hack(sc, -1);
1549 return rv;
1550 }
1551
1552 static void
1553 cs4280_clear_fifos(struct cs428x_softc *sc)
1554 {
1555 int pd, cnt, n;
1556 uint32_t mem;
1557
1558 pd = 0;
1559 /*
1560 * If device power down, power up the device and keep power down
1561 * state.
1562 */
1563 mem = BA0READ4(sc, CS4280_CLKCR1);
1564 if (!(mem & CLKCR1_SWCE)) {
1565 printf("cs4280_clear_fifo: power down found.\n");
1566 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE);
1567 pd = 1;
1568 }
1569 BA0WRITE4(sc, CS4280_SERBWP, 0);
1570 for (cnt = 0; cnt < 256; cnt++) {
1571 n = 0;
1572 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) {
1573 delay(1000);
1574 if (++n > 1000) {
1575 printf("clear_fifo: fist timeout cnt=%d\n", cnt);
1576 break;
1577 }
1578 }
1579 BA0WRITE4(sc, CS4280_SERBAD, cnt);
1580 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC);
1581 }
1582 if (pd)
1583 BA0WRITE4(sc, CS4280_CLKCR1, mem);
1584 }
1585
1586 #if NMIDI > 0
1587 static int
1588 cs4280_midi_open(void *addr, int flags, void (*iintr)(void *, int),
1589 void (*ointr)(void *), void *arg)
1590 {
1591 struct cs428x_softc *sc;
1592 uint32_t mem;
1593
1594 DPRINTF(("midi_open\n"));
1595 sc = addr;
1596 sc->sc_iintr = iintr;
1597 sc->sc_ointr = ointr;
1598 sc->sc_arg = arg;
1599
1600 /* midi interrupt enable */
1601 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
1602 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB;
1603 BA0WRITE4(sc, CS4280_MIDCR, mem);
1604 #ifdef CS4280_DEBUG
1605 if (mem != BA0READ4(sc, CS4280_MIDCR)) {
1606 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR)));
1607 return(EINVAL);
1608 }
1609 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
1610 #endif
1611 return 0;
1612 }
1613
1614 static void
1615 cs4280_midi_close(void *addr)
1616 {
1617 struct cs428x_softc *sc;
1618 uint32_t mem;
1619
1620 DPRINTF(("midi_close\n"));
1621 sc = addr;
1622 tsleep(sc, PWAIT, "cs0clm", hz/10); /* give uart a chance to drain */
1623 mem = BA0READ4(sc, CS4280_MIDCR);
1624 mem &= ~MIDCR_MASK;
1625 BA0WRITE4(sc, CS4280_MIDCR, mem);
1626
1627 sc->sc_iintr = 0;
1628 sc->sc_ointr = 0;
1629 }
1630
1631 static int
1632 cs4280_midi_output(void *addr, int d)
1633 {
1634 struct cs428x_softc *sc;
1635 uint32_t mem;
1636 int x;
1637
1638 sc = addr;
1639 for (x = 0; x != MIDI_BUSY_WAIT; x++) {
1640 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
1641 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK;
1642 mem |= d & MIDWP_MASK;
1643 DPRINTFN(5,("midi_output d=0x%08x",d));
1644 BA0WRITE4(sc, CS4280_MIDWP, mem);
1645 #ifdef DIAGNOSTIC
1646 if (mem != BA0READ4(sc, CS4280_MIDWP)) {
1647 DPRINTF(("Bad write data: %d %d",
1648 mem, BA0READ4(sc, CS4280_MIDWP)));
1649 return EIO;
1650 }
1651 #endif
1652 return 0;
1653 }
1654 delay(MIDI_BUSY_DELAY);
1655 }
1656 return EIO;
1657 }
1658
1659 static void
1660 cs4280_midi_getinfo(void *addr, struct midi_info *mi)
1661 {
1662
1663 mi->name = "CS4280 MIDI UART";
1664 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR;
1665 }
1666
1667 #endif /* NMIDI */
1668
1669 /* DEBUG functions */
1670 #if CS4280_DEBUG > 10
1671 static int
1672 cs4280_checkimage(struct cs428x_softc *sc, uint32_t *src,
1673 uint32_t offset, uint32_t len)
1674 {
1675 uint32_t ctr, data;
1676 int err;
1677
1678 if ((offset & 3) || (len & 3))
1679 return -1;
1680
1681 err = 0;
1682 len /= sizeof(uint32_t);
1683 for (ctr = 0; ctr < len; ctr++) {
1684 /* I cannot confirm this is the right thing
1685 * on BIG-ENDIAN machines
1686 */
1687 data = BA1READ4(sc, offset+ctr*4);
1688 if (data != htole32(*(src+ctr))) {
1689 printf("0x%06x: 0x%08x(0x%08x)\n",
1690 offset+ctr*4, data, *(src+ctr));
1691 *(src+ctr) = data;
1692 ++err;
1693 }
1694 }
1695 return err;
1696 }
1697
1698 static int
1699 cs4280_check_images(struct cs428x_softc *sc)
1700 {
1701 int idx, err;
1702 uint32_t offset;
1703
1704 offset = 0;
1705 err = 0;
1706 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx)*/
1707 for (idx = 0; idx < 1; ++idx) {
1708 err = cs4280_checkimage(sc, &BA1Struct.map[offset],
1709 BA1Struct.memory[idx].offset,
1710 BA1Struct.memory[idx].size);
1711 if (err != 0) {
1712 aprint_error_dev(&sc->sc_dev,
1713 "check_image failed at %d\n", idx);
1714 }
1715 offset += BA1Struct.memory[idx].size / sizeof(uint32_t);
1716 }
1717 return err;
1718 }
1719
1720 #endif /* CS4280_DEBUG */
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