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[netbsd-mini2440.git] / sys / dev / pci / piixide.c
blob16d35bca4082734a4c1c0b6f2eaf3bb7f13490a4
1 /* $NetBSD: piixide.c,v 1.52 2009/11/30 09:33:48 sborrill Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.52 2009/11/30 09:33:48 sborrill Exp $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32
33 #include <dev/pci/pcivar.h>
34 #include <dev/pci/pcidevs.h>
35 #include <dev/pci/pciidereg.h>
36 #include <dev/pci/pciidevar.h>
37 #include <dev/pci/pciide_piix_reg.h>
38
39 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *);
40 static void piix_setup_channel(struct ata_channel *);
41 static void piix3_4_setup_channel(struct ata_channel *);
42 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
43 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
44 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
45 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *);
46 static int piix_dma_init(void *, int, int, void *, size_t, int);
47
48 static bool piixide_resume(device_t, pmf_qual_t);
49 static bool piixide_suspend(device_t, pmf_qual_t);
50 static int piixide_match(device_t, cfdata_t, void *);
51 static void piixide_attach(device_t, device_t, void *);
52
53 static const struct pciide_product_desc pciide_intel_products[] = {
54 { PCI_PRODUCT_INTEL_82092AA,
55 0,
56 "Intel 82092AA IDE controller",
57 default_chip_map,
58 },
59 { PCI_PRODUCT_INTEL_82371FB_IDE,
60 0,
61 "Intel 82371FB IDE controller (PIIX)",
62 piix_chip_map,
63 },
64 { PCI_PRODUCT_INTEL_82371SB_IDE,
65 0,
66 "Intel 82371SB IDE Interface (PIIX3)",
67 piix_chip_map,
68 },
69 { PCI_PRODUCT_INTEL_82371AB_IDE,
70 0,
71 "Intel 82371AB IDE controller (PIIX4)",
72 piix_chip_map,
73 },
74 { PCI_PRODUCT_INTEL_82440MX_IDE,
75 0,
76 "Intel 82440MX IDE controller",
77 piix_chip_map
78 },
79 { PCI_PRODUCT_INTEL_82801AA_IDE,
80 0,
81 "Intel 82801AA IDE Controller (ICH)",
82 piix_chip_map,
83 },
84 { PCI_PRODUCT_INTEL_82801AB_IDE,
85 0,
86 "Intel 82801AB IDE Controller (ICH0)",
87 piix_chip_map,
88 },
89 { PCI_PRODUCT_INTEL_82801BA_IDE,
90 0,
91 "Intel 82801BA IDE Controller (ICH2)",
92 piix_chip_map,
93 },
94 { PCI_PRODUCT_INTEL_82801BAM_IDE,
95 0,
96 "Intel 82801BAM IDE Controller (ICH2-M)",
97 piix_chip_map,
98 },
99 { PCI_PRODUCT_INTEL_82801CA_IDE_1,
100 0,
101 "Intel 82801CA IDE Controller (ICH3)",
102 piix_chip_map,
103 },
104 { PCI_PRODUCT_INTEL_82801CA_IDE_2,
105 0,
106 "Intel 82801CA IDE Controller (ICH3)",
107 piix_chip_map,
108 },
109 { PCI_PRODUCT_INTEL_82801DB_IDE,
110 0,
111 "Intel 82801DB IDE Controller (ICH4)",
112 piix_chip_map,
113 },
114 { PCI_PRODUCT_INTEL_82801DBM_IDE,
115 0,
116 "Intel 82801DBM IDE Controller (ICH4-M)",
117 piix_chip_map,
118 },
119 { PCI_PRODUCT_INTEL_82801EB_IDE,
120 0,
121 "Intel 82801EB IDE Controller (ICH5)",
122 piix_chip_map,
123 },
124 { PCI_PRODUCT_INTEL_82801EB_SATA,
125 0,
126 "Intel 82801EB Serial ATA Controller",
127 piixsata_chip_map,
128 },
129 { PCI_PRODUCT_INTEL_82801ER_SATA,
130 0,
131 "Intel 82801ER Serial ATA/Raid Controller",
132 piixsata_chip_map,
133 },
134 { PCI_PRODUCT_INTEL_6300ESB_IDE,
135 0,
136 "Intel 6300ESB IDE Controller (ICH5)",
137 piix_chip_map,
138 },
139 { PCI_PRODUCT_INTEL_6300ESB_SATA,
140 0,
141 "Intel 6300ESB Serial ATA Controller",
142 piixsata_chip_map,
143 },
144 { PCI_PRODUCT_INTEL_6300ESB_RAID,
145 0,
146 "Intel 6300ESB Serial ATA/RAID Controller",
147 piixsata_chip_map,
148 },
149 { PCI_PRODUCT_INTEL_82801FB_IDE,
150 0,
151 "Intel 82801FB IDE Controller (ICH6)",
152 piix_chip_map,
153 },
154 { PCI_PRODUCT_INTEL_82801FB_SATA,
155 0,
156 "Intel 82801FB Serial ATA/Raid Controller",
157 piixsata_chip_map,
158 },
159 { PCI_PRODUCT_INTEL_82801FR_SATA,
160 0,
161 "Intel 82801FR Serial ATA/Raid Controller",
162 piixsata_chip_map,
163 },
164 { PCI_PRODUCT_INTEL_82801FBM_SATA,
165 0,
166 "Intel 82801FBM Serial ATA Controller (ICH6)",
167 piixsata_chip_map,
168 },
169 { PCI_PRODUCT_INTEL_82801G_IDE,
170 0,
171 "Intel 82801GB/GR IDE Controller (ICH7)",
172 piix_chip_map,
173 },
174 { PCI_PRODUCT_INTEL_82801G_SATA,
175 0,
176 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)",
177 piixsata_chip_map,
178 },
179 { PCI_PRODUCT_INTEL_82801GBM_SATA,
180 0,
181 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)",
182 piixsata_chip_map,
183 },
184 { PCI_PRODUCT_INTEL_82801H_SATA_1,
185 0,
186 "Intel 82801H Serial ATA Controller (ICH8)",
187 piixsata_chip_map,
188 },
189 { PCI_PRODUCT_INTEL_82801H_SATA_RAID,
190 0,
191 "Intel 82801H Serial ATA RAID Controller (ICH8)",
192 piixsata_chip_map,
193 },
194 { PCI_PRODUCT_INTEL_82801H_SATA_2,
195 0,
196 "Intel 82801H Serial ATA Controller (ICH8)",
197 piixsata_chip_map,
198 },
199 { PCI_PRODUCT_INTEL_82801HBM_IDE,
200 0,
201 "Intel 82801HBM IDE Controller (ICH8M)",
202 piix_chip_map,
203 },
204 { PCI_PRODUCT_INTEL_82801HBM_SATA_1,
205 0,
206 "Intel 82801HBM Serial ATA Controller (ICH8M)",
207 piixsata_chip_map,
208 },
209 { PCI_PRODUCT_INTEL_82801HBM_SATA_2,
210 0,
211 "Intel 82801HBM Serial ATA Controller (ICH8M)",
212 piixsata_chip_map,
213 },
214 { PCI_PRODUCT_INTEL_82801HEM_SATA,
215 0,
216 "Intel 82801HEM Serial ATA Controller (ICH8M)",
217 piixsata_chip_map,
218 },
219 { PCI_PRODUCT_INTEL_63XXESB_IDE,
220 0,
221 "Intel 631xESB/632xESB IDE Controller",
222 piix_chip_map,
223 },
224 { PCI_PRODUCT_INTEL_82801I_SATA_1,
225 0,
226 "Intel 82801I Serial ATA Controller (ICH9)",
227 piixsata_chip_map,
228 },
229 { PCI_PRODUCT_INTEL_82801I_SATA_2,
230 0,
231 "Intel 82801I Serial ATA Controller (ICH9)",
232 piixsata_chip_map,
233 },
234 { PCI_PRODUCT_INTEL_82801I_SATA_3,
235 0,
236 "Intel 82801I Serial ATA Controller (ICH9)",
237 piixsata_chip_map,
238 },
239 { PCI_PRODUCT_INTEL_82801I_SATA_4,
240 0,
241 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
242 piixsata_chip_map,
243 },
244 { PCI_PRODUCT_INTEL_82801I_SATA_5,
245 0,
246 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
247 piixsata_chip_map,
248 },
249 { PCI_PRODUCT_INTEL_82801I_SATA_6,
250 0,
251 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
252 piixsata_chip_map,
253 },
254 { PCI_PRODUCT_INTEL_82801I_SATA_7,
255 0,
256 "Intel 82801I Mobile Serial ATA Controller (ICH9)",
257 piixsata_chip_map,
258 },
259 { PCI_PRODUCT_INTEL_63XXESB_SATA,
260 0,
261 "Intel 631xESB/632xESB Serial ATA Controller",
262 piixsata_chip_map,
263 },
264 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x1,
265 0,
266 "Intel ICH10 Serial ATA 2 Controller 2x1",
267 piixsata_chip_map,
268 },
269 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x2,
270 0,
271 "Intel ICH10 Serial ATA 2 Controller 2x2",
272 piixsata_chip_map,
273 },
274 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x1,
275 0,
276 "Intel ICH10 Serial ATA 2 Controller 4x1",
277 piixsata_chip_map,
278 },
279 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x2,
280 0,
281 "Intel ICH10 Serial ATA 2 Controller 4x2",
282 piixsata_chip_map,
283 },
284 {
285 PCI_PRODUCT_INTEL_82965PM_IDE,
286 0,
287 "Intel 82965PM IDE controller",
288 piixsata_chip_map,
289 },
290 {
291 PCI_PRODUCT_INTEL_3400_SATA_1,
292 0,
293 "Intel 3400 Serial ATA Controller",
294 piixsata_chip_map,
295 },
296 {
297 PCI_PRODUCT_INTEL_3400_SATA_1,
298 0,
299 "Intel 3400 Serial ATA Controller",
300 piixsata_chip_map,
301 },
302 {
303 PCI_PRODUCT_INTEL_3400_SATA_2,
304 0,
305 "Intel 3400 Serial ATA Controller",
306 piixsata_chip_map,
307 },
308 {
309 PCI_PRODUCT_INTEL_3400_SATA_3,
310 0,
311 "Intel 3400 Serial ATA Controller",
312 piixsata_chip_map,
313 },
314 {
315 PCI_PRODUCT_INTEL_3400_SATA_4,
316 0,
317 "Intel 3400 Serial ATA Controller",
318 piixsata_chip_map,
319 },
320 {
321 PCI_PRODUCT_INTEL_3400_SATA_5,
322 0,
323 "Intel 3400 Serial ATA Controller",
324 piixsata_chip_map,
325 },
326 {
327 PCI_PRODUCT_INTEL_3400_SATA_6,
328 0,
329 "Intel 3400 Serial ATA Controller",
330 piixsata_chip_map,
331 },
332 { 0,
333 0,
334 NULL,
335 NULL
336 }
337 };
338
339 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc),
340 piixide_match, piixide_attach, NULL, NULL);
341
342 static int
343 piixide_match(device_t parent, cfdata_t match, void *aux)
344 {
345 struct pci_attach_args *pa = aux;
346
347 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
348 if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
349 return (2);
350 }
351 return (0);
352 }
353
354 static void
355 piixide_attach(device_t parent, device_t self, void *aux)
356 {
357 struct pci_attach_args *pa = aux;
358 struct pciide_softc *sc = device_private(self);
359
360 sc->sc_wdcdev.sc_atac.atac_dev = self;
361
362 pciide_common_attach(sc, pa,
363 pciide_lookup_product(pa->pa_id, pciide_intel_products));
364
365 if (!pmf_device_register(self, piixide_suspend, piixide_resume))
366 aprint_error_dev(self, "couldn't establish power handler\n");
367 }
368
369 static bool
370 piixide_resume(device_t dv, pmf_qual_t qual)
371 {
372 struct pciide_softc *sc = device_private(dv);
373
374 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
375 sc->sc_pm_reg[0]);
376 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG,
377 sc->sc_pm_reg[1]);
378
379 return true;
380 }
381
382 static bool
383 piixide_suspend(device_t dv, pmf_qual_t qual)
384 {
385 struct pciide_softc *sc = device_private(dv);
386
387 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag,
388 PIIX_IDETIM);
389 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag,
390 PIIX_UDMAREG);
391
392 return true;
393 }
394
395 static void
396 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
397 {
398 struct pciide_channel *cp;
399 int channel;
400 u_int32_t idetim;
401 bus_size_t cmdsize, ctlsize;
402 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
403
404 if (pciide_chipen(sc, pa) == 0)
405 return;
406
407 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
408 "bus-master DMA support present");
409 pciide_mapreg_dma(sc, pa);
410 aprint_verbose("\n");
411 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
412 if (sc->sc_dma_ok) {
413 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
414 sc->sc_wdcdev.irqack = pciide_irqack;
415 /* Do all revisions require DMA alignment workaround? */
416 sc->sc_wdcdev.dma_init = piix_dma_init;
417 switch(sc->sc_pp->ide_product) {
418 case PCI_PRODUCT_INTEL_82371AB_IDE:
419 case PCI_PRODUCT_INTEL_82440MX_IDE:
420 case PCI_PRODUCT_INTEL_82801AA_IDE:
421 case PCI_PRODUCT_INTEL_82801AB_IDE:
422 case PCI_PRODUCT_INTEL_82801BA_IDE:
423 case PCI_PRODUCT_INTEL_82801BAM_IDE:
424 case PCI_PRODUCT_INTEL_82801CA_IDE_1:
425 case PCI_PRODUCT_INTEL_82801CA_IDE_2:
426 case PCI_PRODUCT_INTEL_82801DB_IDE:
427 case PCI_PRODUCT_INTEL_82801DBM_IDE:
428 case PCI_PRODUCT_INTEL_82801EB_IDE:
429 case PCI_PRODUCT_INTEL_6300ESB_IDE:
430 case PCI_PRODUCT_INTEL_82801FB_IDE:
431 case PCI_PRODUCT_INTEL_82801G_IDE:
432 case PCI_PRODUCT_INTEL_82801HBM_IDE:
433 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
434 }
435 }
436 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
437 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
438 switch(sc->sc_pp->ide_product) {
439 case PCI_PRODUCT_INTEL_82801AA_IDE:
440 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
441 break;
442 case PCI_PRODUCT_INTEL_82801BA_IDE:
443 case PCI_PRODUCT_INTEL_82801BAM_IDE:
444 case PCI_PRODUCT_INTEL_82801CA_IDE_1:
445 case PCI_PRODUCT_INTEL_82801CA_IDE_2:
446 case PCI_PRODUCT_INTEL_82801DB_IDE:
447 case PCI_PRODUCT_INTEL_82801DBM_IDE:
448 case PCI_PRODUCT_INTEL_82801EB_IDE:
449 case PCI_PRODUCT_INTEL_6300ESB_IDE:
450 case PCI_PRODUCT_INTEL_82801FB_IDE:
451 case PCI_PRODUCT_INTEL_82801G_IDE:
452 case PCI_PRODUCT_INTEL_82801HBM_IDE:
453 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
454 break;
455 default:
456 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
457 }
458 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
459 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel;
460 else
461 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel;
462 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
463 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
464
465 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
466 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
467 DEBUG_PROBE);
468 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
469 ATADEBUG_PRINT((", sidetim=0x%x",
470 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
471 DEBUG_PROBE);
472 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
473 ATADEBUG_PRINT((", udamreg 0x%x",
474 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
475 DEBUG_PROBE);
476 }
477 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
478 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
482 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
483 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
490 ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
491 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
492 DEBUG_PROBE);
493 }
494
495 }
496 ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
497
498 wdc_allocate_regs(&sc->sc_wdcdev);
499
500 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
501 channel++) {
502 cp = &sc->pciide_channels[channel];
503 if (pciide_chansetup(sc, channel, interface) == 0)
504 continue;
505 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
506 if ((PIIX_IDETIM_READ(idetim, channel) &
507 PIIX_IDETIM_IDE) == 0) {
508 #if 1
509 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
510 "%s channel ignored (disabled)\n", cp->name);
511 cp->ata_channel.ch_flags |= ATACH_DISABLED;
512 continue;
513 #else
514 pcireg_t interface;
515
516 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
517 channel);
518 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
519 idetim);
520 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
521 sc->sc_tag, PCI_CLASS_REG));
522 aprint_normal("channel %d idetim=%08x interface=%02x\n",
523 channel, idetim, interface);
524 #endif
525 }
526 pciide_mapchan(pa, cp, interface,
527 &cmdsize, &ctlsize, pciide_pci_intr);
528 }
529
530 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
531 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
532 DEBUG_PROBE);
533 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
534 ATADEBUG_PRINT((", sidetim=0x%x",
535 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
536 DEBUG_PROBE);
537 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
538 ATADEBUG_PRINT((", udamreg 0x%x",
539 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
540 DEBUG_PROBE);
541 }
542 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
543 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
544 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
545 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
555 ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
556 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
557 DEBUG_PROBE);
558 }
559 }
560 ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
561 }
562
563 static void
564 piix_setup_channel(struct ata_channel *chp)
565 {
566 u_int8_t mode[2], drive;
567 u_int32_t oidetim, idetim, idedma_ctl;
568 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
569 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
570 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive;
571
572 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
573 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
574 idedma_ctl = 0;
575
576 /* set up new idetim: Enable IDE registers decode */
577 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
578 chp->ch_channel);
579
580 /* setup DMA */
581 pciide_channel_dma_setup(cp);
582
583 /*
584 * Here we have to mess up with drives mode: PIIX can't have
585 * different timings for master and slave drives.
586 * We need to find the best combination.
587 */
588
589 /* If both drives supports DMA, take the lower mode */
590 if ((drvp[0].drive_flags & DRIVE_DMA) &&
591 (drvp[1].drive_flags & DRIVE_DMA)) {
592 mode[0] = mode[1] =
593 min(drvp[0].DMA_mode, drvp[1].DMA_mode);
594 drvp[0].DMA_mode = mode[0];
595 drvp[1].DMA_mode = mode[1];
596 goto ok;
597 }
598 /*
599 * If only one drive supports DMA, use its mode, and
600 * put the other one in PIO mode 0 if mode not compatible
601 */
602 if (drvp[0].drive_flags & DRIVE_DMA) {
603 mode[0] = drvp[0].DMA_mode;
604 mode[1] = drvp[1].PIO_mode;
605 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
606 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
607 mode[1] = drvp[1].PIO_mode = 0;
608 goto ok;
609 }
610 if (drvp[1].drive_flags & DRIVE_DMA) {
611 mode[1] = drvp[1].DMA_mode;
612 mode[0] = drvp[0].PIO_mode;
613 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
614 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
615 mode[0] = drvp[0].PIO_mode = 0;
616 goto ok;
617 }
618 /*
619 * If both drives are not DMA, takes the lower mode, unless
620 * one of them is PIO mode < 2
621 */
622 if (drvp[0].PIO_mode < 2) {
623 mode[0] = drvp[0].PIO_mode = 0;
624 mode[1] = drvp[1].PIO_mode;
625 } else if (drvp[1].PIO_mode < 2) {
626 mode[1] = drvp[1].PIO_mode = 0;
627 mode[0] = drvp[0].PIO_mode;
628 } else {
629 mode[0] = mode[1] =
630 min(drvp[1].PIO_mode, drvp[0].PIO_mode);
631 drvp[0].PIO_mode = mode[0];
632 drvp[1].PIO_mode = mode[1];
633 }
634 ok: /* The modes are setup */
635 for (drive = 0; drive < 2; drive++) {
636 if (drvp[drive].drive_flags & DRIVE_DMA) {
637 idetim |= piix_setup_idetim_timings(
638 mode[drive], 1, chp->ch_channel);
639 goto end;
640 }
641 }
642 /* If we are there, none of the drives are DMA */
643 if (mode[0] >= 2)
644 idetim |= piix_setup_idetim_timings(
645 mode[0], 0, chp->ch_channel);
646 else
647 idetim |= piix_setup_idetim_timings(
648 mode[1], 0, chp->ch_channel);
649 end: /*
650 * timing mode is now set up in the controller. Enable
651 * it per-drive
652 */
653 for (drive = 0; drive < 2; drive++) {
654 /* If no drive, skip */
655 if ((drvp[drive].drive_flags & DRIVE) == 0)
656 continue;
657 idetim |= piix_setup_idetim_drvs(&drvp[drive]);
658 if (drvp[drive].drive_flags & DRIVE_DMA)
659 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
660 }
661 if (idedma_ctl != 0) {
662 /* Add software bits in status register */
663 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
664 idedma_ctl);
665 }
666 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
667 }
668
669 static void
670 piix3_4_setup_channel(struct ata_channel *chp)
671 {
672 struct ata_drive_datas *drvp;
673 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
674 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
675 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
676 struct wdc_softc *wdc = &sc->sc_wdcdev;
677 int drive, s;
678 int channel = chp->ch_channel;
679
680 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
681 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
682 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
683 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
684 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
685 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
686 PIIX_SIDETIM_RTC_MASK(channel));
687 idedma_ctl = 0;
688
689 /* set up new idetim: Enable IDE registers decode */
690 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
691
692 /* setup DMA if needed */
693 pciide_channel_dma_setup(cp);
694
695 for (drive = 0; drive < 2; drive++) {
696 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
697 PIIX_UDMATIM_SET(0x3, channel, drive));
698 drvp = &chp->ch_drive[drive];
699 /* If no drive, skip */
700 if ((drvp->drive_flags & DRIVE) == 0)
701 continue;
702 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
703 (drvp->drive_flags & DRIVE_UDMA) == 0))
704 goto pio;
705
706 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
707 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
708 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
709 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
710 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
711 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
712 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
713 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
714 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
715 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
716 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
717 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
718 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
719 ideconf |= PIIX_CONFIG_PINGPONG;
720 }
721 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
722 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
723 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
724 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
725 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
726 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
727 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
728 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
729 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
730 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE ||
731 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) {
732 /* setup Ultra/100 */
733 if (drvp->UDMA_mode > 2 &&
734 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
735 drvp->UDMA_mode = 2;
736 if (drvp->UDMA_mode > 4) {
737 ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
738 } else {
739 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
740 if (drvp->UDMA_mode > 2) {
741 ideconf |= PIIX_CONFIG_UDMA66(channel,
742 drive);
743 } else {
744 ideconf &= ~PIIX_CONFIG_UDMA66(channel,
745 drive);
746 }
747 }
748 }
749 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
750 /* setup Ultra/66 */
751 if (drvp->UDMA_mode > 2 &&
752 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
753 drvp->UDMA_mode = 2;
754 if (drvp->UDMA_mode > 2)
755 ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
756 else
757 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
758 }
759 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) &&
760 (drvp->drive_flags & DRIVE_UDMA)) {
761 /* use Ultra/DMA */
762 s = splbio();
763 drvp->drive_flags &= ~DRIVE_DMA;
764 splx(s);
765 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
766 udmareg |= PIIX_UDMATIM_SET(
767 piix4_sct_udma[drvp->UDMA_mode], channel, drive);
768 } else {
769 /* use Multiword DMA */
770 s = splbio();
771 drvp->drive_flags &= ~DRIVE_UDMA;
772 splx(s);
773 if (drive == 0) {
774 idetim |= piix_setup_idetim_timings(
775 drvp->DMA_mode, 1, channel);
776 } else {
777 sidetim |= piix_setup_sidetim_timings(
778 drvp->DMA_mode, 1, channel);
779 idetim =PIIX_IDETIM_SET(idetim,
780 PIIX_IDETIM_SITRE, channel);
781 }
782 }
783 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
784
785 pio: /* use PIO mode */
786 idetim |= piix_setup_idetim_drvs(drvp);
787 if (drive == 0) {
788 idetim |= piix_setup_idetim_timings(
789 drvp->PIO_mode, 0, channel);
790 } else {
791 sidetim |= piix_setup_sidetim_timings(
792 drvp->PIO_mode, 0, channel);
793 idetim =PIIX_IDETIM_SET(idetim,
794 PIIX_IDETIM_SITRE, channel);
795 }
796 }
797 if (idedma_ctl != 0) {
798 /* Add software bits in status register */
799 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
800 idedma_ctl);
801 }
802 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
803 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
804 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
805 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
806 }
807
808
809 /* setup ISP and RTC fields, based on mode */
810 static u_int32_t
811 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
812 {
813
814 if (dma)
815 return PIIX_IDETIM_SET(0,
816 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
817 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
818 channel);
819 else
820 return PIIX_IDETIM_SET(0,
821 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
822 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
823 channel);
824 }
825
826 /* setup DTE, PPE, IE and TIME field based on PIO mode */
827 static u_int32_t
828 piix_setup_idetim_drvs(struct ata_drive_datas *drvp)
829 {
830 u_int32_t ret = 0;
831 struct ata_channel *chp = drvp->chnl_softc;
832 u_int8_t channel = chp->ch_channel;
833 u_int8_t drive = drvp->drive;
834
835 /*
836 * If drive is using UDMA, timings setups are independent
837 * So just check DMA and PIO here.
838 */
839 if (drvp->drive_flags & DRIVE_DMA) {
840 /* if mode = DMA mode 0, use compatible timings */
841 if ((drvp->drive_flags & DRIVE_DMA) &&
842 drvp->DMA_mode == 0) {
843 drvp->PIO_mode = 0;
844 return ret;
845 }
846 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
847 /*
848 * PIO and DMA timings are the same, use fast timings for PIO
849 * too, else use compat timings.
850 */
851 if ((piix_isp_pio[drvp->PIO_mode] !=
852 piix_isp_dma[drvp->DMA_mode]) ||
853 (piix_rtc_pio[drvp->PIO_mode] !=
854 piix_rtc_dma[drvp->DMA_mode]))
855 drvp->PIO_mode = 0;
856 /* if PIO mode <= 2, use compat timings for PIO */
857 if (drvp->PIO_mode <= 2) {
858 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
859 channel);
860 return ret;
861 }
862 }
863
864 /*
865 * Now setup PIO modes. If mode < 2, use compat timings.
866 * Else enable fast timings. Enable IORDY and prefetch/post
867 * if PIO mode >= 3.
868 */
869
870 if (drvp->PIO_mode < 2)
871 return ret;
872
873 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
874 if (drvp->PIO_mode >= 3) {
875 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
876 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
877 }
878 return ret;
879 }
880
881 /* setup values in SIDETIM registers, based on mode */
882 static u_int32_t
883 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel)
884 {
885 if (dma)
886 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
887 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel);
888 else
889 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
890 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
891 }
892
893 static void
894 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
895 {
896 struct pciide_channel *cp;
897 bus_size_t cmdsize, ctlsize;
898 pcireg_t interface, cmdsts;
899 int channel;
900
901 if (pciide_chipen(sc, pa) == 0)
902 return;
903
904 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
905 "bus-master DMA support present");
906 pciide_mapreg_dma(sc, pa);
907 aprint_verbose("\n");
908
909 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
910 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
911 if (sc->sc_dma_ok) {
912 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
913 sc->sc_wdcdev.irqack = pciide_irqack;
914 /* Do all revisions require DMA alignment workaround? */
915 sc->sc_wdcdev.dma_init = piix_dma_init;
916 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
917 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
918 }
919 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
920
921 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
922 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
923
924 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
925 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE;
926 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
927
928 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
929 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
930 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
931
932 interface = PCI_INTERFACE(pa->pa_class);
933
934 wdc_allocate_regs(&sc->sc_wdcdev);
935
936 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
937 channel++) {
938 cp = &sc->pciide_channels[channel];
939 if (pciide_chansetup(sc, channel, interface) == 0)
940 continue;
941 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
942 pciide_pci_intr);
943 }
944 }
945
946 static int
947 piix_dma_init(void *v, int channel, int drive, void *databuf,
948 size_t datalen, int flags)
949 {
950
951 /* use PIO for unaligned transfer */
952 if (((uintptr_t)databuf) & 0x1)
953 return EINVAL;
954
955 return pciide_dma_init(v, channel, drive, databuf, datalen, flags);
956 }
NetBSD on the FriendlyARM MINI2440