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[netbsd-mini2440.git] / sys / dev / pci / viaide.c
bloba372a1408dbc25e243913604cc5d39d1add9959d
1 /* $NetBSD: viaide.c,v 1.66 2009/12/23 00:11:36 mrg Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: viaide.c,v 1.66 2009/12/23 00:11:36 mrg Exp $");
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <dev/pci/pciidereg.h>
37 #include <dev/pci/pciidevar.h>
38 #include <dev/pci/pciide_apollo_reg.h>
39
40 static int via_pcib_match(struct pci_attach_args *);
41 static void via_chip_map(struct pciide_softc *, struct pci_attach_args *);
42 static void via_mapchan(struct pci_attach_args *, struct pciide_channel *,
43 pcireg_t, bus_size_t *, bus_size_t *, int (*)(void *));
44 static void via_mapregs_compat_native(struct pci_attach_args *,
45 struct pciide_channel *, bus_size_t *, bus_size_t *);
46 static int via_sata_chip_map_common(struct pciide_softc *,
47 struct pci_attach_args *);
48 static void via_sata_chip_map(struct pciide_softc *,
49 struct pci_attach_args *, int);
50 static void via_sata_chip_map_6(struct pciide_softc *,
51 struct pci_attach_args *);
52 static void via_sata_chip_map_7(struct pciide_softc *,
53 struct pci_attach_args *);
54 static void via_sata_chip_map_new(struct pciide_softc *,
55 struct pci_attach_args *);
56 static void via_setup_channel(struct ata_channel *);
57
58 static int viaide_match(device_t, cfdata_t, void *);
59 static void viaide_attach(device_t, device_t, void *);
60 static const struct pciide_product_desc *
61 viaide_lookup(pcireg_t);
62 static bool viaide_suspend(device_t, pmf_qual_t);
63 static bool viaide_resume(device_t, pmf_qual_t);
64
65 CFATTACH_DECL_NEW(viaide, sizeof(struct pciide_softc),
66 viaide_match, viaide_attach, NULL, NULL);
67
68 static const struct pciide_product_desc pciide_amd_products[] = {
69 { PCI_PRODUCT_AMD_PBC756_IDE,
70 0,
71 "AMD AMD756 IDE Controller",
72 via_chip_map
73 },
74 { PCI_PRODUCT_AMD_PBC766_IDE,
75 0,
76 "AMD AMD766 IDE Controller",
77 via_chip_map
78 },
79 { PCI_PRODUCT_AMD_PBC768_IDE,
80 0,
81 "AMD AMD768 IDE Controller",
82 via_chip_map
83 },
84 { PCI_PRODUCT_AMD_PBC8111_IDE,
85 0,
86 "AMD AMD8111 IDE Controller",
87 via_chip_map
88 },
89 { PCI_PRODUCT_AMD_CS5536_IDE,
90 0,
91 "AMD CS5536 IDE Controller",
92 via_chip_map
93 },
94 { 0,
95 0,
96 NULL,
97 NULL
98 }
99 };
100
101 static const struct pciide_product_desc pciide_nvidia_products[] = {
102 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
103 0,
104 "NVIDIA nForce IDE Controller",
105 via_chip_map
106 },
107 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
108 0,
109 "NVIDIA nForce2 IDE Controller",
110 via_chip_map
111 },
112 { PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133,
113 0,
114 "NVIDIA nForce2 Ultra 400 IDE Controller",
115 via_chip_map
116 },
117 { PCI_PRODUCT_NVIDIA_NFORCE2_400_SATA,
118 0,
119 "NVIDIA nForce2 Ultra 400 Serial ATA Controller",
120 via_sata_chip_map_6
121 },
122 { PCI_PRODUCT_NVIDIA_NFORCE3_ATA133,
123 0,
124 "NVIDIA nForce3 IDE Controller",
125 via_chip_map
126 },
127 { PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133,
128 0,
129 "NVIDIA nForce3 250 IDE Controller",
130 via_chip_map
131 },
132 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA,
133 0,
134 "NVIDIA nForce3 250 Serial ATA Controller",
135 via_sata_chip_map_6
136 },
137 { PCI_PRODUCT_NVIDIA_NFORCE3_250_SATA2,
138 0,
139 "NVIDIA nForce3 250 Serial ATA Controller",
140 via_sata_chip_map_6
141 },
142 { PCI_PRODUCT_NVIDIA_NFORCE4_ATA133,
143 0,
144 "NVIDIA nForce4 IDE Controller",
145 via_chip_map
146 },
147 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA1,
148 0,
149 "NVIDIA nForce4 Serial ATA Controller",
150 via_sata_chip_map_6
151 },
152 { PCI_PRODUCT_NVIDIA_NFORCE4_SATA2,
153 0,
154 "NVIDIA nForce4 Serial ATA Controller",
155 via_sata_chip_map_6
156 },
157 { PCI_PRODUCT_NVIDIA_NFORCE430_ATA133,
158 0,
159 "NVIDIA nForce430 IDE Controller",
160 via_chip_map
161 },
162 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA1,
163 0,
164 "NVIDIA nForce430 Serial ATA Controller",
165 via_sata_chip_map_6
166 },
167 { PCI_PRODUCT_NVIDIA_NFORCE430_SATA2,
168 0,
169 "NVIDIA nForce430 Serial ATA Controller",
170 via_sata_chip_map_6
171 },
172 { PCI_PRODUCT_NVIDIA_MCP04_IDE,
173 0,
174 "NVIDIA MCP04 IDE Controller",
175 via_chip_map
176 },
177 { PCI_PRODUCT_NVIDIA_MCP04_SATA,
178 0,
179 "NVIDIA MCP04 Serial ATA Controller",
180 via_sata_chip_map_6
181 },
182 { PCI_PRODUCT_NVIDIA_MCP04_SATA2,
183 0,
184 "NVIDIA MCP04 Serial ATA Controller",
185 via_sata_chip_map_6
186 },
187 { PCI_PRODUCT_NVIDIA_MCP55_IDE,
188 0,
189 "NVIDIA MCP55 IDE Controller",
190 via_chip_map
191 },
192 { PCI_PRODUCT_NVIDIA_MCP55_SATA,
193 0,
194 "NVIDIA MCP55 Serial ATA Controller",
195 via_sata_chip_map_6
196 },
197 { PCI_PRODUCT_NVIDIA_MCP55_SATA2,
198 0,
199 "NVIDIA MCP55 Serial ATA Controller",
200 via_sata_chip_map_6
201 },
202 { PCI_PRODUCT_NVIDIA_MCP61_IDE,
203 0,
204 "NVIDIA MCP61 IDE Controller",
205 via_chip_map
206 },
207 { PCI_PRODUCT_NVIDIA_MCP65_IDE,
208 0,
209 "NVIDIA MCP65 IDE Controller",
210 via_chip_map
211 },
212 { PCI_PRODUCT_NVIDIA_MCP73_IDE,
213 0,
214 "NVIDIA MCP73 IDE Controller",
215 via_chip_map
216 },
217 { PCI_PRODUCT_NVIDIA_MCP77_IDE,
218 0,
219 "NVIDIA MCP77 IDE Controller",
220 via_chip_map
221 },
222 { PCI_PRODUCT_NVIDIA_MCP61_SATA,
223 0,
224 "NVIDIA MCP61 Serial ATA Controller",
225 via_sata_chip_map_6
226 },
227 { PCI_PRODUCT_NVIDIA_MCP61_SATA2,
228 0,
229 "NVIDIA MCP61 Serial ATA Controller",
230 via_sata_chip_map_6
231 },
232 { PCI_PRODUCT_NVIDIA_MCP61_SATA3,
233 0,
234 "NVIDIA MCP61 Serial ATA Controller",
235 via_sata_chip_map_6
236 },
237 { PCI_PRODUCT_NVIDIA_MCP65_SATA,
238 0,
239 "NVIDIA MCP65 Serial ATA Controller",
240 via_sata_chip_map_6
241 },
242 { PCI_PRODUCT_NVIDIA_MCP65_SATA2,
243 0,
244 "NVIDIA MCP65 Serial ATA Controller",
245 via_sata_chip_map_6
246 },
247 { PCI_PRODUCT_NVIDIA_MCP65_SATA3,
248 0,
249 "NVIDIA MCP65 Serial ATA Controller",
250 via_sata_chip_map_6
251 },
252 { PCI_PRODUCT_NVIDIA_MCP65_SATA4,
253 0,
254 "NVIDIA MCP65 Serial ATA Controller",
255 via_sata_chip_map_6
256 },
257 { PCI_PRODUCT_NVIDIA_MCP67_IDE,
258 0,
259 "NVIDIA MCP67 IDE Controller",
260 via_chip_map,
261 },
262 { PCI_PRODUCT_NVIDIA_MCP67_SATA,
263 0,
264 "NVIDIA MCP67 Serial ATA Controller",
265 via_sata_chip_map_6,
266 },
267 { PCI_PRODUCT_NVIDIA_MCP67_SATA2,
268 0,
269 "NVIDIA MCP67 Serial ATA Controller",
270 via_sata_chip_map_6,
271 },
272 { PCI_PRODUCT_NVIDIA_MCP67_SATA3,
273 0,
274 "NVIDIA MCP67 Serial ATA Controller",
275 via_sata_chip_map_6,
276 },
277 { PCI_PRODUCT_NVIDIA_MCP67_SATA4,
278 0,
279 "NVIDIA MCP67 Serial ATA Controller",
280 via_sata_chip_map_6,
281 },
282 { 0,
283 0,
284 NULL,
285 NULL
286 }
287 };
288
289 static const struct pciide_product_desc pciide_via_products[] = {
290 { PCI_PRODUCT_VIATECH_VT82C586_IDE,
291 0,
292 NULL,
293 via_chip_map,
294 },
295 { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
296 0,
297 NULL,
298 via_chip_map,
299 },
300 { PCI_PRODUCT_VIATECH_CX700_IDE,
301 0,
302 NULL,
303 via_chip_map,
304 },
305 { PCI_PRODUCT_VIATECH_CX700M2_IDE,
306 0,
307 NULL,
308 via_chip_map,
309 },
310 { PCI_PRODUCT_VIATECH_VT6421_RAID,
311 0,
312 "VIA Technologies VT6421 Serial RAID Controller",
313 via_sata_chip_map_new,
314 },
315 { PCI_PRODUCT_VIATECH_VT8237_SATA,
316 0,
317 "VIA Technologies VT8237 SATA Controller",
318 via_sata_chip_map_7,
319 },
320 { PCI_PRODUCT_VIATECH_VT8237A_SATA,
321 0,
322 "VIA Technologies VT8237A SATA Controller",
323 via_sata_chip_map_7,
324 },
325 { PCI_PRODUCT_VIATECH_VT8237A_SATA_2,
326 0,
327 "VIA Technologies VT8237A (5337) SATA Controller",
328 via_sata_chip_map_7,
329 },
330 { PCI_PRODUCT_VIATECH_VT8237R_SATA,
331 0,
332 "VIA Technologies VT8237R SATA Controller",
333 via_sata_chip_map_7,
334 },
335 { PCI_PRODUCT_VIATECH_VT8237S_SATA,
336 0,
337 "VIA Technologies VT8237S SATA Controller",
338 via_sata_chip_map_7,
339 },
340 { 0,
341 0,
342 NULL,
343 NULL
344 }
345 };
346
347 static const struct pciide_product_desc *
348 viaide_lookup(pcireg_t id)
349 {
350
351 switch (PCI_VENDOR(id)) {
352 case PCI_VENDOR_VIATECH:
353 return (pciide_lookup_product(id, pciide_via_products));
354
355 case PCI_VENDOR_AMD:
356 return (pciide_lookup_product(id, pciide_amd_products));
357
358 case PCI_VENDOR_NVIDIA:
359 return (pciide_lookup_product(id, pciide_nvidia_products));
360 }
361 return (NULL);
362 }
363
364 static int
365 viaide_match(device_t parent, cfdata_t match, void *aux)
366 {
367 struct pci_attach_args *pa = aux;
368
369 if (viaide_lookup(pa->pa_id) != NULL)
370 return (2);
371 return (0);
372 }
373
374 static void
375 viaide_attach(device_t parent, device_t self, void *aux)
376 {
377 struct pci_attach_args *pa = aux;
378 struct pciide_softc *sc = device_private(self);
379 const struct pciide_product_desc *pp;
380
381 sc->sc_wdcdev.sc_atac.atac_dev = self;
382
383 pp = viaide_lookup(pa->pa_id);
384 if (pp == NULL)
385 panic("viaide_attach");
386 pciide_common_attach(sc, pa, pp);
387
388 if (!pmf_device_register(self, viaide_suspend, viaide_resume))
389 aprint_error_dev(self, "couldn't establish power handler\n");
390 }
391
392 static int
393 via_pcib_match(struct pci_attach_args *pa)
394 {
395 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
396 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
397 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
398 return (1);
399 return 0;
400 }
401
402 static bool
403 viaide_suspend(device_t dv, pmf_qual_t qual)
404 {
405 struct pciide_softc *sc = device_private(dv);
406
407 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
408 /* APO_DATATIM(sc) includes APO_UDMA(sc) */
409 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
410 /* This two are VIA-only, but should be ignored by other devices. */
411 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc));
412 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc));
413
414 return true;
415 }
416
417 static bool
418 viaide_resume(device_t dv, pmf_qual_t qual)
419 {
420 struct pciide_softc *sc = device_private(dv);
421
422 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc),
423 sc->sc_pm_reg[0]);
424 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc),
425 sc->sc_pm_reg[1]);
426 /* This two are VIA-only, but should be ignored by other devices. */
427 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc),
428 sc->sc_pm_reg[2]);
429 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_MISCTIM(sc),
430 sc->sc_pm_reg[3]);
431
432 return true;
433 }
434
435 static void
436 via_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
437 {
438 struct pciide_channel *cp;
439 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
440 pcireg_t vendor = PCI_VENDOR(pa->pa_id);
441 int channel;
442 u_int32_t ideconf;
443 bus_size_t cmdsize, ctlsize;
444 pcireg_t pcib_id, pcib_class;
445 struct pci_attach_args pcib_pa;
446
447 if (pciide_chipen(sc, pa) == 0)
448 return;
449
450 switch (vendor) {
451 case PCI_VENDOR_VIATECH:
452 /*
453 * get a PCI tag for the ISA bridge.
454 */
455 if (pci_find_device(&pcib_pa, via_pcib_match) == 0)
456 goto unknown;
457 pcib_id = pcib_pa.pa_id;
458 pcib_class = pcib_pa.pa_class;
459 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
460 "VIA Technologies ");
461 switch (PCI_PRODUCT(pcib_id)) {
462 case PCI_PRODUCT_VIATECH_VT82C586_ISA:
463 aprint_normal("VT82C586 (Apollo VP) ");
464 if(PCI_REVISION(pcib_class) >= 0x02) {
465 aprint_normal("ATA33 controller\n");
466 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
467 } else {
468 aprint_normal("controller\n");
469 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
470 }
471 break;
472 case PCI_PRODUCT_VIATECH_VT82C596A:
473 aprint_normal("VT82C596A (Apollo Pro) ");
474 if (PCI_REVISION(pcib_class) >= 0x12) {
475 aprint_normal("ATA66 controller\n");
476 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
477 } else {
478 aprint_normal("ATA33 controller\n");
479 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
480 }
481 break;
482 case PCI_PRODUCT_VIATECH_VT82C686A_ISA:
483 aprint_normal("VT82C686A (Apollo KX133) ");
484 if (PCI_REVISION(pcib_class) >= 0x40) {
485 aprint_normal("ATA100 controller\n");
486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
487 } else {
488 aprint_normal("ATA66 controller\n");
489 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
490 }
491 break;
492 case PCI_PRODUCT_VIATECH_VT8231:
493 aprint_normal("VT8231 ATA100 controller\n");
494 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
495 break;
496 case PCI_PRODUCT_VIATECH_VT8233:
497 aprint_normal("VT8233 ATA100 controller\n");
498 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
499 break;
500 case PCI_PRODUCT_VIATECH_VT8233A:
501 aprint_normal("VT8233A ATA133 controller\n");
502 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
503 break;
504 case PCI_PRODUCT_VIATECH_VT8235:
505 aprint_normal("VT8235 ATA133 controller\n");
506 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
507 break;
508 case PCI_PRODUCT_VIATECH_VT8237:
509 aprint_normal("VT8237 ATA133 controller\n");
510 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
511 break;
512 case PCI_PRODUCT_VIATECH_VT8237A_ISA:
513 aprint_normal("VT8237A ATA133 controller\n");
514 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
515 break;
516 case PCI_PRODUCT_VIATECH_CX700:
517 aprint_normal("CX700 ATA133 controller\n");
518 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
519 break;
520 case PCI_PRODUCT_VIATECH_VT8251:
521 aprint_normal("VT8251 ATA133 controller\n");
522 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
523 break;
524 default:
525 unknown:
526 aprint_normal("unknown VIA ATA controller\n");
527 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
528 }
529 sc->sc_apo_regbase = APO_VIA_REGBASE;
530 break;
531 case PCI_VENDOR_AMD:
532 switch (sc->sc_pp->ide_product) {
533 case PCI_PRODUCT_AMD_PBC8111_IDE:
534 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
535 break;
536 case PCI_PRODUCT_AMD_CS5536_IDE:
537 case PCI_PRODUCT_AMD_PBC766_IDE:
538 case PCI_PRODUCT_AMD_PBC768_IDE:
539 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
540 break;
541 default:
542 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
543 }
544 sc->sc_apo_regbase = APO_AMD_REGBASE;
545 break;
546 case PCI_VENDOR_NVIDIA:
547 switch (sc->sc_pp->ide_product) {
548 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
549 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
550 break;
551 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
552 case PCI_PRODUCT_NVIDIA_NFORCE2_400_ATA133:
553 case PCI_PRODUCT_NVIDIA_NFORCE3_ATA133:
554 case PCI_PRODUCT_NVIDIA_NFORCE3_250_ATA133:
555 case PCI_PRODUCT_NVIDIA_NFORCE4_ATA133:
556 case PCI_PRODUCT_NVIDIA_NFORCE430_ATA133:
557 case PCI_PRODUCT_NVIDIA_MCP04_IDE:
558 case PCI_PRODUCT_NVIDIA_MCP55_IDE:
559 case PCI_PRODUCT_NVIDIA_MCP61_IDE:
560 case PCI_PRODUCT_NVIDIA_MCP65_IDE:
561 case PCI_PRODUCT_NVIDIA_MCP67_IDE:
562 case PCI_PRODUCT_NVIDIA_MCP73_IDE:
563 case PCI_PRODUCT_NVIDIA_MCP77_IDE:
564 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
565 break;
566 }
567 sc->sc_apo_regbase = APO_NVIDIA_REGBASE;
568 break;
569 default:
570 panic("via_chip_map: unknown vendor");
571 }
572
573 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
574 "bus-master DMA support present");
575 pciide_mapreg_dma(sc, pa);
576 aprint_verbose("\n");
577 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
578 if (sc->sc_dma_ok) {
579 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
580 sc->sc_wdcdev.irqack = pciide_irqack;
581 if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 0)
582 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
583 }
584 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
585 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
586 sc->sc_wdcdev.sc_atac.atac_set_modes = via_setup_channel;
587 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
588 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
589
590 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
591 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
592 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
593
594 wdc_allocate_regs(&sc->sc_wdcdev);
595
596 ATADEBUG_PRINT(("via_chip_map: old APO_IDECONF=0x%x, "
597 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
598 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc)),
599 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC(sc)),
600 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
601 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))),
602 DEBUG_PROBE);
603
604 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF(sc));
605 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
606 channel++) {
607 cp = &sc->pciide_channels[channel];
608 if (pciide_chansetup(sc, channel, interface) == 0)
609 continue;
610
611 if ((ideconf & APO_IDECONF_EN(channel)) == 0) {
612 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
613 "%s channel ignored (disabled)\n", cp->name);
614 cp->ata_channel.ch_flags |= ATACH_DISABLED;
615 continue;
616 }
617 via_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
618 pciide_pci_intr);
619 }
620 }
621
622 static void
623 via_mapchan(struct pci_attach_args *pa, struct pciide_channel *cp,
624 pcireg_t interface, bus_size_t *cmdsizep, bus_size_t *ctlsizep,
625 int (*pci_intr)(void *))
626 {
627 struct ata_channel *wdc_cp;
628 struct pciide_softc *sc;
629 prop_bool_t compat_nat_enable;
630
631 wdc_cp = &cp->ata_channel;
632 sc = CHAN_TO_PCIIDE(&cp->ata_channel);
633 compat_nat_enable = prop_dictionary_get(
634 device_properties(sc->sc_wdcdev.sc_atac.atac_dev),
635 "use-compat-native-irq");
636
637 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) {
638 /* native mode with irq 14/15 requested? */
639 if (compat_nat_enable != NULL &&
640 prop_bool_true(compat_nat_enable))
641 via_mapregs_compat_native(pa, cp, cmdsizep, ctlsizep);
642 else
643 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep,
644 pci_intr);
645 } else {
646 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep,
647 ctlsizep);
648 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
649 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
650 }
651 wdcattach(wdc_cp);
652 }
653
654 /*
655 * At least under certain (mis)configurations (e.g. on the "Pegasos" board)
656 * the VT8231-IDE's native mode only works with irq 14/15, and cannot be
657 * programmed to use a single native PCI irq alone. So we install an interrupt
658 * handler for each channel, as in compatibility mode.
659 */
660 static void
661 via_mapregs_compat_native(struct pci_attach_args *pa,
662 struct pciide_channel *cp, bus_size_t *cmdsizep, bus_size_t *ctlsizep)
663 {
664 struct ata_channel *wdc_cp;
665 struct pciide_softc *sc;
666
667 wdc_cp = &cp->ata_channel;
668 sc = CHAN_TO_PCIIDE(&cp->ata_channel);
669
670 /* XXX prevent pciide_mapregs_native from installing a handler */
671 if (sc->sc_pci_ih == NULL)
672 sc->sc_pci_ih = (void *)~0;
673 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, NULL);
674
675 /* interrupts are fixed to 14/15, as in compatibility mode */
676 cp->compat = 1;
677 if ((wdc_cp->ch_flags & ATACH_DISABLED) == 0) {
678 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
679 cp->ih = pciide_machdep_compat_intr_establish(
680 sc->sc_wdcdev.sc_atac.atac_dev, pa, wdc_cp->ch_channel,
681 pciide_compat_intr, cp);
682 if (cp->ih == NULL) {
683 #endif
684 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
685 "no compatibility interrupt for "
686 "use by %s channel\n", cp->name);
687 wdc_cp->ch_flags |= ATACH_DISABLED;
688 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
689 }
690 sc->sc_pci_ih = cp->ih; /* XXX */
691 #endif
692 }
693 }
694
695 static void
696 via_setup_channel(struct ata_channel *chp)
697 {
698 u_int32_t udmatim_reg, datatim_reg;
699 u_int8_t idedma_ctl;
700 int mode, drive, s;
701 struct ata_drive_datas *drvp;
702 struct atac_softc *atac = chp->ch_atac;
703 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
704 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
705 #ifndef PCIIDE_AMD756_ENABLEDMA
706 int rev = PCI_REVISION(
707 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
708 #endif
709
710 idedma_ctl = 0;
711 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc));
712 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc));
713 datatim_reg &= ~APO_DATATIM_MASK(chp->ch_channel);
714 udmatim_reg &= ~APO_UDMA_MASK(chp->ch_channel);
715
716 /* setup DMA if needed */
717 pciide_channel_dma_setup(cp);
718
719 for (drive = 0; drive < 2; drive++) {
720 drvp = &chp->ch_drive[drive];
721 /* If no drive, skip */
722 if ((drvp->drive_flags & DRIVE) == 0)
723 continue;
724 /* add timing values, setup DMA if needed */
725 if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
726 (drvp->drive_flags & DRIVE_UDMA) == 0)) {
727 mode = drvp->PIO_mode;
728 goto pio;
729 }
730 if ((atac->atac_cap & ATAC_CAP_UDMA) &&
731 (drvp->drive_flags & DRIVE_UDMA)) {
732 /* use Ultra/DMA */
733 s = splbio();
734 drvp->drive_flags &= ~DRIVE_DMA;
735 splx(s);
736 udmatim_reg |= APO_UDMA_EN(chp->ch_channel, drive) |
737 APO_UDMA_EN_MTH(chp->ch_channel, drive);
738 switch (PCI_VENDOR(sc->sc_pci_id)) {
739 case PCI_VENDOR_VIATECH:
740 if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 6) {
741 /* 8233a */
742 udmatim_reg |= APO_UDMA_TIME(
743 chp->ch_channel,
744 drive,
745 via_udma133_tim[drvp->UDMA_mode]);
746 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 5) {
747 /* 686b */
748 udmatim_reg |= APO_UDMA_TIME(
749 chp->ch_channel,
750 drive,
751 via_udma100_tim[drvp->UDMA_mode]);
752 } else if (sc->sc_wdcdev.sc_atac.atac_udma_cap == 4) {
753 /* 596b or 686a */
754 udmatim_reg |= APO_UDMA_CLK66(
755 chp->ch_channel);
756 udmatim_reg |= APO_UDMA_TIME(
757 chp->ch_channel,
758 drive,
759 via_udma66_tim[drvp->UDMA_mode]);
760 } else {
761 /* 596a or 586b */
762 udmatim_reg |= APO_UDMA_TIME(
763 chp->ch_channel,
764 drive,
765 via_udma33_tim[drvp->UDMA_mode]);
766 }
767 break;
768 case PCI_VENDOR_AMD:
769 case PCI_VENDOR_NVIDIA:
770 udmatim_reg |= APO_UDMA_TIME(chp->ch_channel,
771 drive, amd7x6_udma_tim[drvp->UDMA_mode]);
772 break;
773 }
774 /* can use PIO timings, MW DMA unused */
775 mode = drvp->PIO_mode;
776 } else {
777 /* use Multiword DMA, but only if revision is OK */
778 s = splbio();
779 drvp->drive_flags &= ~DRIVE_UDMA;
780 splx(s);
781 #ifndef PCIIDE_AMD756_ENABLEDMA
782 /*
783 * The workaround doesn't seem to be necessary
784 * with all drives, so it can be disabled by
785 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if
786 * triggered.
787 */
788 if (PCI_VENDOR(sc->sc_pci_id) == PCI_VENDOR_AMD &&
789 sc->sc_pp->ide_product ==
790 PCI_PRODUCT_AMD_PBC756_IDE &&
791 AMD756_CHIPREV_DISABLEDMA(rev)) {
792 aprint_normal(
793 "%s:%d:%d: multi-word DMA disabled due "
794 "to chip revision\n",
795 device_xname(
796 sc->sc_wdcdev.sc_atac.atac_dev),
797 chp->ch_channel, drive);
798 mode = drvp->PIO_mode;
799 s = splbio();
800 drvp->drive_flags &= ~DRIVE_DMA;
801 splx(s);
802 goto pio;
803 }
804 #endif
805 /* mode = min(pio, dma+2) */
806 if (drvp->PIO_mode <= (drvp->DMA_mode + 2))
807 mode = drvp->PIO_mode;
808 else
809 mode = drvp->DMA_mode + 2;
810 }
811 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
812
813 pio: /* setup PIO mode */
814 if (mode <= 2) {
815 drvp->DMA_mode = 0;
816 drvp->PIO_mode = 0;
817 mode = 0;
818 } else {
819 drvp->PIO_mode = mode;
820 drvp->DMA_mode = mode - 2;
821 }
822 datatim_reg |=
823 APO_DATATIM_PULSE(chp->ch_channel, drive,
824 apollo_pio_set[mode]) |
825 APO_DATATIM_RECOV(chp->ch_channel, drive,
826 apollo_pio_rec[mode]);
827 }
828 if (idedma_ctl != 0) {
829 /* Add software bits in status register */
830 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
831 idedma_ctl);
832 }
833 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc), datatim_reg);
834 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA(sc), udmatim_reg);
835 ATADEBUG_PRINT(("via_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n",
836 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM(sc)),
837 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA(sc))), DEBUG_PROBE);
838 }
839
840 static int
841 via_sata_chip_map_common(struct pciide_softc *sc, struct pci_attach_args *pa)
842 {
843 bus_size_t satasize;
844 int maptype, ret;
845
846 if (pciide_chipen(sc, pa) == 0)
847 return 0;
848
849 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
850 "bus-master DMA support present");
851 pciide_mapreg_dma(sc, pa);
852 aprint_verbose("\n");
853
854 /*
855 * Enable memory-space access if it isn't already there.
856 */
857 if (pa->pa_memt && (pa->pa_flags & PCI_FLAGS_MEM_ENABLED) == 0) {
858 pcireg_t csr;
859
860 pa->pa_flags |= PCI_FLAGS_MEM_ENABLED;
861 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
862 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
863 csr | PCI_COMMAND_MEM_ENABLE);
864 }
865
866 if (sc->sc_dma_ok) {
867 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA;
868 sc->sc_wdcdev.irqack = pciide_irqack;
869 }
870 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
871 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
872 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
873
874 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
875 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
876 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
877 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
878
879 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
880 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
881 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
882
883 wdc_allocate_regs(&sc->sc_wdcdev);
884 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
885 PCI_MAPREG_START + 0x14);
886 switch(maptype) {
887 case PCI_MAPREG_TYPE_IO:
888 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
889 PCI_MAPREG_TYPE_IO, 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
890 NULL, &satasize);
891 break;
892 case PCI_MAPREG_MEM_TYPE_32BIT:
893 ret = pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
894 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
895 0, &sc->sc_ba5_st, &sc->sc_ba5_sh,
896 NULL, &satasize);
897 break;
898 default:
899 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
900 "couldn't map sata regs, unsupported maptype (0x%x)\n",
901 maptype);
902 return 0;
903 }
904 if (ret != 0) {
905 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
906 "couldn't map sata regs\n");
907 return 0;
908 }
909 return 1;
910 }
911
912 static void
913 via_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa,
914 int satareg_shift)
915 {
916 struct pciide_channel *cp;
917 struct ata_channel *wdc_cp;
918 struct wdc_regs *wdr;
919 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
920 int channel;
921 bus_size_t cmdsize, ctlsize;
922
923 if (via_sata_chip_map_common(sc, pa) == 0)
924 return;
925
926 if (interface == 0) {
927 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
928 DEBUG_PROBE);
929 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
930 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
931 }
932
933 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
934 channel++) {
935 cp = &sc->pciide_channels[channel];
936 if (pciide_chansetup(sc, channel, interface) == 0)
937 continue;
938 wdc_cp = &cp->ata_channel;
939 wdr = CHAN_TO_WDC_REGS(wdc_cp);
940 wdr->sata_iot = sc->sc_ba5_st;
941 wdr->sata_baseioh = sc->sc_ba5_sh;
942 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
943 (wdc_cp->ch_channel << satareg_shift) + 0x0, 4,
944 &wdr->sata_status) != 0) {
945 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
946 "couldn't map channel %d sata_status regs\n",
947 wdc_cp->ch_channel);
948 continue;
949 }
950 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
951 (wdc_cp->ch_channel << satareg_shift) + 0x4, 4,
952 &wdr->sata_error) != 0) {
953 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
954 "couldn't map channel %d sata_error regs\n",
955 wdc_cp->ch_channel);
956 continue;
957 }
958 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
959 (wdc_cp->ch_channel << satareg_shift) + 0x8, 4,
960 &wdr->sata_control) != 0) {
961 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
962 "couldn't map channel %d sata_control regs\n",
963 wdc_cp->ch_channel);
964 continue;
965 }
966 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
967 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
968 pciide_pci_intr);
969 }
970 }
971
972 static void
973 via_sata_chip_map_6(struct pciide_softc *sc, struct pci_attach_args *pa)
974 {
975 via_sata_chip_map(sc, pa, 6);
976 }
977
978 static void
979 via_sata_chip_map_7(struct pciide_softc *sc, struct pci_attach_args *pa)
980 {
981 via_sata_chip_map(sc, pa, 7);
982 }
983
984 static void
985 via_sata_chip_map_new(struct pciide_softc *sc, struct pci_attach_args *pa)
986 {
987 struct pciide_channel *cp;
988 struct ata_channel *wdc_cp;
989 struct wdc_regs *wdr;
990 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
991 int channel;
992 bus_size_t cmdsize;
993 pci_intr_handle_t intrhandle;
994 const char *intrstr;
995 int i;
996
997 if (via_sata_chip_map_common(sc, pa) == 0)
998 return;
999
1000 if (interface == 0) {
1001 ATADEBUG_PRINT(("via_sata_chip_map interface == 0\n"),
1002 DEBUG_PROBE);
1003 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
1004 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
1005 }
1006
1007 if (pci_intr_map(pa, &intrhandle) != 0) {
1008 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1009 "couldn't map native-PCI interrupt\n");
1010 return;
1011 }
1012 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
1013 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
1014 intrhandle, IPL_BIO, pciide_pci_intr, sc);
1015 if (sc->sc_pci_ih == NULL) {
1016 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1017 "couldn't establish native-PCI interrupt");
1018 if (intrstr != NULL)
1019 aprint_error(" at %s", intrstr);
1020 aprint_error("\n");
1021 return;
1022 }
1023 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1024 "using %s for native-PCI interrupt\n",
1025 intrstr ? intrstr : "unknown interrupt");
1026
1027 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1028 channel++) {
1029 cp = &sc->pciide_channels[channel];
1030 if (pciide_chansetup(sc, channel, interface) == 0)
1031 continue;
1032 cp->ata_channel.ch_ndrive = 1;
1033 wdc_cp = &cp->ata_channel;
1034 wdr = CHAN_TO_WDC_REGS(wdc_cp);
1035
1036 wdr->sata_iot = sc->sc_ba5_st;
1037 wdr->sata_baseioh = sc->sc_ba5_sh;
1038 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1039 (wdc_cp->ch_channel << 6) + 0x0, 4,
1040 &wdr->sata_status) != 0) {
1041 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1042 "couldn't map channel %d sata_status regs\n",
1043 wdc_cp->ch_channel);
1044 continue;
1045 }
1046 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1047 (wdc_cp->ch_channel << 6) + 0x4, 4,
1048 &wdr->sata_error) != 0) {
1049 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1050 "couldn't map channel %d sata_error regs\n",
1051 wdc_cp->ch_channel);
1052 continue;
1053 }
1054 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
1055 (wdc_cp->ch_channel << 6) + 0x8, 4,
1056 &wdr->sata_control) != 0) {
1057 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1058 "couldn't map channel %d sata_control regs\n",
1059 wdc_cp->ch_channel);
1060 continue;
1061 }
1062 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
1063
1064 if (pci_mapreg_map(pa, (PCI_MAPREG_START + (4 * (channel))),
1065 PCI_MAPREG_TYPE_IO, 0, &wdr->cmd_iot, &wdr->cmd_baseioh,
1066 NULL, &cmdsize) != 0) {
1067 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1068 "couldn't map %s channel regs\n", cp->name);
1069 }
1070 wdr->ctl_iot = wdr->cmd_iot;
1071 for (i = 0; i < WDC_NREG; i++) {
1072 if (bus_space_subregion(wdr->cmd_iot,
1073 wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
1074 &wdr->cmd_iohs[i]) != 0) {
1075 aprint_error_dev(
1076 sc->sc_wdcdev.sc_atac.atac_dev,
1077 "couldn't subregion %s "
1078 "channel cmd regs\n", cp->name);
1079 return;
1080 }
1081 }
1082 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
1083 WDC_NREG + 2, 1, &wdr->ctl_ioh) != 0) {
1084 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1085 "couldn't map channel %d ctl regs\n", channel);
1086 return;
1087 }
1088 wdc_init_shadow_regs(wdc_cp);
1089 wdr->data32iot = wdr->cmd_iot;
1090 wdr->data32ioh = wdr->cmd_iohs[wd_data];
1091 wdcattach(wdc_cp);
1092 }
1093 }
NetBSD on the FriendlyARM MINI2440