sys/dev/sdmmc/sdmmcreg.h

   1 /*      $NetBSD: sdmmcreg.h,v 1.2 2009/04/26 07:21:13 nonaka Exp $      */
   2 /*      $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $        */
   3
   4 /*
   5  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
   6  *
   7  * Permission to use, copy, modify, and distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  */
  19
  20 #ifndef _SDMMCREG_H_
  21 #define _SDMMCREG_H_
  22
  23 /* MMC commands */                              /* response type */
  24 #define MMC_GO_IDLE_STATE               0       /* R0 */
  25 #define MMC_SEND_OP_COND                1       /* R3 */
  26 #define MMC_ALL_SEND_CID                2       /* R2 */
  27 #define MMC_SET_RELATIVE_ADDR           3       /* R1 */
  28 #define MMC_SWITCH                      6       /* R1b */
  29 #define MMC_SELECT_CARD                 7       /* R1 */
  30 #define MMC_SEND_EXT_CSD                8       /* R1 */
  31 #define MMC_SEND_CSD                    9       /* R2 */
  32 #define MMC_SEND_CID                    10      /* R2 */
  33 #define MMC_STOP_TRANSMISSION           12      /* R1b */
  34 #define MMC_SEND_STATUS                 13      /* R1 */
  35 #define MMC_INACTIVE_STATE              15      /* R0 */
  36 #define MMC_SET_BLOCKLEN                16      /* R1 */
  37 #define MMC_READ_BLOCK_SINGLE           17      /* R1 */
  38 #define MMC_READ_BLOCK_MULTIPLE         18      /* R1 */
  39 #define MMC_SET_BLOCK_COUNT             23      /* R1 */
  40 #define MMC_WRITE_BLOCK_SINGLE          24      /* R1 */
  41 #define MMC_WRITE_BLOCK_MULTIPLE        25      /* R1 */
  42 #define MMC_PROGRAM_CSD                 27      /* R1 */
  43 #define MMC_SET_WRITE_PROT              28      /* R1b */
  44 #define MMC_SET_CLR_WRITE_PROT          29      /* R1b */
  45 #define MMC_SET_SEND_WRITE_PROT         30      /* R1 */
  46 #define MMC_TAG_SECTOR_START            32      /* R1 */
  47 #define MMC_TAG_SECTOR_END              33      /* R1 */
  48 #define MMC_UNTAG_SECTOR                34      /* R1 */
  49 #define MMC_TAG_ERASE_GROUP_START       35      /* R1 */
  50 #define MMC_TAG_ERASE_GROUP_END         36      /* R1 */
  51 #define MMC_UNTAG_ERASE_GROUP           37      /* R1 */
  52 #define MMC_ERASE                       38      /* R1b */
  53 #define MMC_LOCK_UNLOCK                 42      /* R1b */
  54 #define MMC_APP_CMD                     55      /* R1 */
  55 #define MMC_READ_OCR                    58      /* R3 */
  56
  57 /* SD commands */                       /* response type */
  58 #define SD_SEND_RELATIVE_ADDR           3       /* R6 */
  59 #define SD_SEND_IF_COND                 8       /* R7 */
  60
  61 /* SD application commands */                   /* response type */
  62 #define SD_APP_SET_BUS_WIDTH            6       /* R1 */
  63 #define SD_APP_OP_COND                  41      /* R3 */
  64 #define SD_APP_SEND_SCR                 51      /* R1 */
  65
  66 /* OCR bits */
  67 #define MMC_OCR_MEM_READY               (1U<<31)/* memory power-up status bit */
  68 #define MMC_OCR_HCS                     (1<<30)
  69 #define MMC_OCR_3_5V_3_6V               (1<<23)
  70 #define MMC_OCR_3_4V_3_5V               (1<<22)
  71 #define MMC_OCR_3_3V_3_4V               (1<<21)
  72 #define MMC_OCR_3_2V_3_3V               (1<<20)
  73 #define MMC_OCR_3_1V_3_2V               (1<<19)
  74 #define MMC_OCR_3_0V_3_1V               (1<<18)
  75 #define MMC_OCR_2_9V_3_0V               (1<<17)
  76 #define MMC_OCR_2_8V_2_9V               (1<<16)
  77 #define MMC_OCR_2_7V_2_8V               (1<<15)
  78 #define MMC_OCR_2_6V_2_7V               (1<<14)
  79 #define MMC_OCR_2_5V_2_6V               (1<<13)
  80 #define MMC_OCR_2_4V_2_5V               (1<<12)
  81 #define MMC_OCR_2_3V_2_4V               (1<<11)
  82 #define MMC_OCR_2_2V_2_3V               (1<<10)
  83 #define MMC_OCR_2_1V_2_2V               (1<<9)
  84 #define MMC_OCR_2_0V_2_1V               (1<<8)
  85 #define MMC_OCR_1_9V_2_0V               (1<<7)
  86 #define MMC_OCR_1_8V_1_9V               (1<<6)
  87 #define MMC_OCR_1_7V_1_8V               (1<<5)
  88 #define MMC_OCR_1_6V_1_7V               (1<<4)
  89
  90 /* R1 response type bits */
  91 #define MMC_R1_READY_FOR_DATA           (1<<8)  /* ready for next transfer */
  92 #define MMC_R1_APP_CMD                  (1<<5)  /* app. commands supported */
  93
  94 /* 48-bit response decoding (32 bits w/o CRC) */
  95 #define MMC_R1(resp)                    ((resp)[0])
  96 #define MMC_R3(resp)                    ((resp)[0])
  97 #define SD_R6(resp)                     ((resp)[0])
  98 #define MMC_R7(resp)                    ((resp)[0])
  99
 100 /* RCA argument and response */
 101 #define MMC_ARG_RCA(rca)                ((rca) << 16)
 102 #define SD_R6_RCA(resp)                 (SD_R6((resp)) >> 16)
 103
 104 /* bus width argument */
 105 #define SD_ARG_BUS_WIDTH_1              0
 106 #define SD_ARG_BUS_WIDTH_4              2
 107
 108 /* MMC R2 response (CSD) */
 109 #define MMC_CSD_CSDVER(resp)            MMC_RSP_BITS((resp), 126, 2)
 110 #define  MMC_CSD_CSDVER_1_0             1
 111 #define  MMC_CSD_CSDVER_2_0             2
 112 #define MMC_CSD_MMCVER(resp)            MMC_RSP_BITS((resp), 122, 4)
 113 #define  MMC_CSD_MMCVER_1_0             0 /* MMC 1.0 - 1.2 */
 114 #define  MMC_CSD_MMCVER_1_4             1 /* MMC 1.4 */
 115 #define  MMC_CSD_MMCVER_2_0             2 /* MMC 2.0 - 2.2 */
 116 #define  MMC_CSD_MMCVER_3_1             3 /* MMC 3.1 - 3.3 */
 117 #define  MMC_CSD_MMCVER_4_0             4 /* MMC 4 */
 118 #define MMC_CSD_TAAC(resp)              MMC_RSP_BITS((resp), 112, 8)
 119 #define MMC_CSD_TAAC_MANT(resp)         MMC_RSP_BITS((resp), 115, 4)
 120 #define MMC_CSD_TAAC_EXP(resp)          MMC_RSP_BITS((resp), 112, 3)
 121 #define MMC_CSD_NSAC(resp)              MMC_RSP_BITS((resp), 104, 8)
 122 #define MMC_CSD_TRAN_SPEED(resp)        MMC_RSP_BITS((resp), 96, 8)
 123 #define MMC_CSD_TRAN_SPEED_MANT(resp)   MMC_RSP_BITS((resp), 99, 4)
 124 #define MMC_CSD_TRAN_SPEED_EXP(resp)    MMC_RSP_BITS((resp), 96, 3)
 125 #define MMC_CSD_READ_BL_LEN(resp)       MMC_RSP_BITS((resp), 80, 4)
 126 #define MMC_CSD_C_SIZE(resp)            MMC_RSP_BITS((resp), 62, 12)
 127 #define MMC_CSD_CAPACITY(resp)          ((MMC_CSD_C_SIZE((resp))+1) << \
 128                                          (MMC_CSD_C_SIZE_MULT((resp))+2))
 129 #define MMC_CSD_C_SIZE_MULT(resp)       MMC_RSP_BITS((resp), 47, 3)
 130 #define MMC_CSD_R2W_FACTOR(resp)        MMC_RSP_BITS((resp), 26, 3)
 131 #define MMC_CSD_WRITE_BL_LEN(resp)      MMC_RSP_BITS((resp), 22, 4)
 132
 133 /* MMC v1 R2 response (CID) */
 134 #define MMC_CID_MID_V1(resp)            MMC_RSP_BITS((resp), 104, 24)
 135 #define MMC_CID_PNM_V1_CPY(resp, pnm)                                   \
 136         do {                                                            \
 137                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
 138                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
 139                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
 140                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
 141                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
 142                 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
 143                 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8);                 \
 144                 (pnm)[7] = '\0';                                        \
 145         } while (/*CONSTCOND*/0)
 146 #define MMC_CID_REV_V1(resp)            MMC_RSP_BITS((resp), 40, 8)
 147 #define MMC_CID_PSN_V1(resp)            MMC_RSP_BITS((resp), 16, 24)
 148 #define MMC_CID_MDT_V1(resp)            MMC_RSP_BITS((resp), 8, 8)
 149
 150 /* MMC v2 R2 response (CID) */
 151 #define MMC_CID_MID_V2(resp)            MMC_RSP_BITS((resp), 120, 8)
 152 #define MMC_CID_OID_V2(resp)            MMC_RSP_BITS((resp), 104, 16)
 153 #define MMC_CID_PNM_V2_CPY(resp, pnm)                                   \
 154         do {                                                            \
 155                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
 156                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
 157                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
 158                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
 159                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
 160                 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
 161                 (pnm)[6] = '\0';                                        \
 162         } while (/*CONSTCOND*/0)
 163 #define MMC_CID_PSN_V2(resp)            MMC_RSP_BITS((resp), 16, 32)
 164
 165 /* SD R2 response (CSD) */
 166 #define SD_CSD_CSDVER(resp)             MMC_RSP_BITS((resp), 126, 2)
 167 #define  SD_CSD_CSDVER_1_0              0
 168 #define  SD_CSD_CSDVER_2_0              1
 169 #define SD_CSD_MMCVER(resp)             MMC_RSP_BITS((resp), 122, 4)
 170 #define SD_CSD_TAAC(resp)               MMC_RSP_BITS((resp), 112, 8)
 171 #define SD_CSD_TAAC_EXP(resp)           MMC_RSP_BITS((resp), 115, 4)
 172 #define SD_CSD_TAAC_MANT(resp)          MMC_RSP_BITS((resp), 112, 3)
 173 #define  SD_CSD_TAAC_1_5_MSEC           0x26
 174 #define SD_CSD_NSAC(resp)               MMC_RSP_BITS((resp), 104, 8)
 175 #define SD_CSD_SPEED(resp)              MMC_RSP_BITS((resp), 96, 8)
 176 #define SD_CSD_SPEED_MANT(resp)         MMC_RSP_BITS((resp), 99, 4)
 177 #define SD_CSD_SPEED_EXP(resp)          MMC_RSP_BITS((resp), 96, 3)
 178 #define  SD_CSD_SPEED_25_MHZ            0x32
 179 #define  SD_CSD_SPEED_50_MHZ            0x5a
 180 #define SD_CSD_CCC(resp)                MMC_RSP_BITS((resp), 84, 12)
 181 #define  SD_CSD_CCC_ALL                 0x5f5
 182 #define SD_CSD_READ_BL_LEN(resp)        MMC_RSP_BITS((resp), 80, 4)
 183 #define SD_CSD_READ_BL_PARTIAL(resp)    MMC_RSP_BITS((resp), 79, 1)
 184 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
 185 #define SD_CSD_READ_BLK_MISALIGN(resp)  MMC_RSP_BITS((resp), 77, 1)
 186 #define SD_CSD_DSR_IMP(resp)            MMC_RSP_BITS((resp), 76, 1)
 187 #define SD_CSD_C_SIZE(resp)             MMC_RSP_BITS((resp), 62, 12)
 188 #define SD_CSD_CAPACITY(resp)           ((SD_CSD_C_SIZE((resp))+1) << \
 189                                          (SD_CSD_C_SIZE_MULT((resp))+2))
 190 #define SD_CSD_VDD_R_CURR_MIN(resp)     MMC_RSP_BITS((resp), 59, 3)
 191 #define SD_CSD_VDD_R_CURR_MAX(resp)     MMC_RSP_BITS((resp), 56, 3)
 192 #define SD_CSD_VDD_W_CURR_MIN(resp)     MMC_RSP_BITS((resp), 53, 3)
 193 #define SD_CSD_VDD_W_CURR_MAX(resp)     MMC_RSP_BITS((resp), 50, 3)
 194 #define  SD_CSD_VDD_RW_CURR_100mA       0x7
 195 #define  SD_CSD_VDD_RW_CURR_80mA        0x6
 196 #define SD_CSD_V2_C_SIZE(resp)          MMC_RSP_BITS((resp), 48, 22)
 197 #define SD_CSD_V2_CAPACITY(resp)        ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
 198 #define SD_CSD_V2_BL_LEN                0x9 /* 512 */
 199 #define SD_CSD_C_SIZE_MULT(resp)        MMC_RSP_BITS((resp), 47, 3)
 200 #define SD_CSD_ERASE_BLK_EN(resp)       MMC_RSP_BITS((resp), 46, 1)
 201 #define SD_CSD_SECTOR_SIZE(resp)        MMC_RSP_BITS((resp), 39, 7) /* +1 */
 202 #define SD_CSD_WP_GRP_SIZE(resp)        MMC_RSP_BITS((resp), 32, 7) /* +1 */
 203 #define SD_CSD_WP_GRP_ENABLE(resp)      MMC_RSP_BITS((resp), 31, 1)
 204 #define SD_CSD_R2W_FACTOR(resp)         MMC_RSP_BITS((resp), 26, 3)
 205 #define SD_CSD_WRITE_BL_LEN(resp)       MMC_RSP_BITS((resp), 22, 4)
 206 #define  SD_CSD_RW_BL_LEN_2G            0xa
 207 #define  SD_CSD_RW_BL_LEN_1G            0x9
 208 #define SD_CSD_WRITE_BL_PARTIAL(resp)   MMC_RSP_BITS((resp), 21, 1)
 209 #define SD_CSD_FILE_FORMAT_GRP(resp)    MMC_RSP_BITS((resp), 15, 1)
 210 #define SD_CSD_COPY(resp)               MMC_RSP_BITS((resp), 14, 1)
 211 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
 212 #define SD_CSD_TMP_WRITE_PROTECT(resp)  MMC_RSP_BITS((resp), 12, 1)
 213 #define SD_CSD_FILE_FORMAT(resp)        MMC_RSP_BITS((resp), 10, 2)
 214
 215 /* SD R2 response (CID) */
 216 #define SD_CID_MID(resp)                MMC_RSP_BITS((resp), 120, 8)
 217 #define SD_CID_OID(resp)                MMC_RSP_BITS((resp), 104, 16)
 218 #define SD_CID_PNM_CPY(resp, pnm)                                       \
 219         do {                                                            \
 220                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
 221                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
 222                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
 223                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
 224                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
 225                 (pnm)[5] = '\0';                                        \
 226         } while (/*CONSTCOND*/0)
 227 #define SD_CID_REV(resp)                MMC_RSP_BITS((resp), 56, 8)
 228 #define SD_CID_PSN(resp)                MMC_RSP_BITS((resp), 24, 32)
 229 #define SD_CID_MDT(resp)                MMC_RSP_BITS((resp), 8, 12)
 230
 231 /* SCR (SD Configuration Register) */
 232 #define SCR_STRUCTURE(scr)              MMC_RSP_BITS((scr), 60, 4)
 233 #define  SCR_STRUCTURE_VER_1_0          0 /* Version 1.0 */
 234 #define SCR_SD_SPEC(scr)                MMC_RSP_BITS((scr), 56, 4)
 235 #define  SCR_SD_SPEC_VER_1_0            0 /* Version 1.0 */
 236 #define SCR_DATA_STAT_AFTER_ERASE(scr)  MMC_RSP_BITS((scr), 55, 1)
 237 #define SCR_SD_SECURITY(scr)            MMC_RSP_BITS((scr), 52, 3)
 238 #define  SCR_SD_SECURITY_NONE           0 /* no security */
 239 #define  SCR_SD_SECURITY_1_0            1 /* security protocol 1.0 */
 240 #define  SCR_SD_SECURITY_1_0_2          2 /* security protocol 1.0 */
 241 #define SCR_SD_BUS_WIDTHS(scr)          MMC_RSP_BITS((scr), 48, 4)
 242 #define  SCR_SD_BUS_WIDTHS_1BIT         (1 << 0) /* 1bit (DAT0) */
 243 #define  SCR_SD_BUS_WIDTHS_4BIT         (1 << 2) /* 4bit (DAT0-3) */
 244 #define SCR_RESERVED(scr)               MMC_RSP_BITS((scr), 32, 16)
 245 #define SCR_RESERVED2(scr)              MMC_RSP_BITS((scr), 0, 32)
 246
 247 /* Might be slow, but it should work on big and little endian systems. */
 248 #define MMC_RSP_BITS(resp, start, len)  __bitfield((resp), (start)-8, (len))
 249 static inline int
 250 __bitfield(uint32_t *src, int start, int len)
 251 {
 252         uint8_t *sp;
 253         uint32_t dst, mask;
 254         int shift, bs, bc;
 255
 256         if (start < 0 || len < 0 || len > 32)
 257                 return 0;
 258
 259         dst = 0;
 260         mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
 261         shift = 0;
 262
 263         while (len > 0) {
 264                 sp = (uint8_t *)src + start / 8;
 265                 bs = start % 8;
 266                 bc = 8 - bs;
 267                 if (bc > len)
 268                         bc = len;
 269                 dst |= (*sp++ >> bs) << shift;
 270                 shift += bc;
 271                 start += bc;
 272                 len -= bc;
 273         }
 274
 275         dst &= mask;
 276         return (int)dst;
 277 }
 278
 279 #endif  /* _SDMMCREG_H_ */