sys/dev/vme/sireg.h

   1 /*      $NetBSD: sireg.h,v 1.2 2003/05/03 18:11:42 wiz Exp $    */
   2
   3 /*-
   4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Paul Kranenburg.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Register map for the VME SCSI-3 adpater (si)
  34  * The first part of this register map is an NCR5380
  35  * SCSI Bus Interface Controller (SBIC).  The rest is a
  36  * DMA controller and custom logic.
  37  */
  38
  39
  40 #if __for_reference_only__
  41 /*
  42  * Am5380 Register map (no padding). See dev/ic/ncr5380reg.h
  43  */
  44 struct ncr5380regs {
  45         u_char r[8];
  46 };
  47
  48 struct si_regs {
  49         struct ncr5380regs sci;
  50
  51         /* DMA controller registers */
  52         u_short dma_addrh;      /* DMA address (VME only) */
  53         u_short dma_addrl;      /* (high word, low word)  */
  54         u_short dma_counth;     /* DMA count   (VME only) */
  55         u_short dma_countl;     /* (high word, low word)  */
  56
  57         u_int   pad0;           /* no-existent register */
  58
  59         u_short fifo_data;      /* fifo data register */
  60         u_short fifo_count;     /* fifo count register */
  61         u_short si_csr;         /* si control/status */
  62         u_short bprh;           /* VME byte pack high */
  63         u_short bprl;           /* VME byte pack low */
  64         u_short iv_am;          /* bits 0-7: intr vector */
  65                                 /* bits 8-13: addr modifier (VME only) */
  66                                 /* bits 14-15: unused */
  67         u_short fifo_cnt_hi;    /* high part of fifo_count (VME only) */
  68
  69         /* Whole thing repeats after 32 bytes. */
  70         u_short _space[3];
  71 };
  72 #endif
  73
  74 /*
  75  * Size of NCR5380 registers located at the bottom of the register bank
  76  */
  77 #define NCR5380REGS_SZ  8
  78
  79 /*
  80  * Register definition for the `si' VME controller
  81  */
  82 #define SIREG_DMA_ADDRH (NCR5380REGS_SZ + 0)    /* DMA address, high word */
  83 #define SIREG_DMA_ADDRL (NCR5380REGS_SZ + 2)    /* DMA address, low word */
  84 #define SIREG_DMA_CNTH  (NCR5380REGS_SZ + 4)    /* DMA count, high word */
  85 #define SIREG_DMA_CNTL  (NCR5380REGS_SZ + 6)    /* DMA count, low word */
  86 #define SIREG_FIFO_DATA (NCR5380REGS_SZ + 12)   /* FIFO data */
  87 #define SIREG_FIFO_CNT  (NCR5380REGS_SZ + 14)   /* FIFO count, low word */
  88 #define SIREG_CSR       (NCR5380REGS_SZ + 16)   /* Control/status register */
  89 #define SIREG_BPRH      (NCR5380REGS_SZ + 18)   /* VME byte pack, high word */
  90 #define SIREG_BPRL      (NCR5380REGS_SZ + 20)   /* VME byte pack, low word */
  91 #define SIREG_IV_AM     (NCR5380REGS_SZ + 22)   /* bits 0-7: intr vector;
  92                                                    bits 8-13: addr modifier */
  93 #define SIREG_FIFO_CNTH (NCR5380REGS_SZ + 24)   /* FIFO count, high word */
  94 #define SIREG_BANK_SZ   (NCR5380REGS_SZ + 26)
  95
  96 /*
  97  * Status Register.
  98  * Note:
  99  *      (r)     indicates bit is read only.
 100  *      (rw)    indicates bit is read or write.
 101  *      (v)     vme host adaptor interface only.
 102  *      (o)     sun3/50 onboard host adaptor interface only.
 103  *      (b)     both vme and sun3/50 host adaptor interfaces.
 104  *
 105  * Note 2: because of the historical connections of this VME driver
 106  * with the on-board SCSI interfaces found in sun3/50, sun3/60 and sun4/100
 107  * systems, the (v), (o) and (b) qualifications are left in for
 108  * cross-reference.
 109  */
 110 #define SI_CSR_DMA_ACTIVE       0x8000  /* (r,o) DMA transfer active */
 111 #define SI_CSR_DMA_CONFLICT     0x4000  /* (r,b) reg accessed while DMA'ing */
 112 #define SI_CSR_DMA_BUS_ERR      0x2000  /* (r,b) bus error during DMA */
 113 #define SI_CSR_ID               0x1000  /* (r,b) 0 for 3/50, 1 for SCSI-3, */
 114                                         /* 0 if SCSI-3 unmodified */
 115 #define SI_CSR_FIFO_FULL        0x0800  /* (r,b) fifo full */
 116 #define SI_CSR_FIFO_EMPTY       0x0400  /* (r,b) fifo empty */
 117 #define SI_CSR_SBC_IP           0x0200  /* (r,b) sbc interrupt pending */
 118 #define SI_CSR_DMA_IP           0x0100  /* (r,b) DMA interrupt pending */
 119 #define SI_CSR_LOB              0x00c0  /* (r,v) number of leftover bytes */
 120 #define   SI_CSR_LOB_THREE      0x00c0  /* (r,v) three leftover bytes */
 121 #define   SI_CSR_LOB_TWO        0x0080  /* (r,v) two leftover bytes */
 122 #define   SI_CSR_LOB_ONE        0x0040  /* (r,v) one leftover byte */
 123 #define SI_CSR_BPCON            0x0020  /* (rw,v) byte packing control */
 124                                         /* DMA is in 0=longwords, 1=words */
 125 #define SI_CSR_DMA_EN           0x0010  /* (rw,v) DMA/interrupt enable */
 126 #define SI_CSR_SEND             0x0008  /* (rw,b) DMA dir, 1=to device */
 127 #define SI_CSR_INTR_EN          0x0004  /* (rw,b) interrupts enable */
 128 #define SI_CSR_FIFO_RES         0x0002  /* (rw,b) inits fifo, 0=reset */
 129 #define SI_CSR_SCSI_RES         0x0001  /* (rw,b) reset sbc and udc, 0=reset */